[mirror_edk2.git] / IntelSiliconPkg / IntelVTdDxe / VtdReg.c

/** @file\r
\r
  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "DmaProtection.h"\r
\r
UINT64                           mVtdHostAddressWidthMask;\r
UINTN                            mVtdUnitNumber;\r
VTD_UNIT_INFORMATION             *mVtdUnitInformation;\r
\r
BOOLEAN  mVtdEnabled;\r
\r
/**\r
  Invalid VTd global IOTLB.\r
\r
  @param[in]  VtdIndex              The index of VTd engine.\r
\r
  @retval EFI_SUCCESS           VTd global IOTLB is invalidated.\r
  @retval EFI_DEVICE_ERROR      VTd global IOTLB is not invalidated.\r
**/\r
EFI_STATUS\r
InvalidateVtdIOTLBGlobal (\r
  IN UINTN  VtdIndex\r
  )\r
{\r
  UINT64  Reg64;\r
  UINT32  Reg32;\r
\r
  if (!mVtdEnabled) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  DEBUG((DEBUG_VERBOSE, "InvalidateVtdIOTLBGlobal(%d)\n", VtdIndex));\r
\r
  AsmWbinvd();\r
\r
  //\r
  // Write Buffer Flush before invalidation\r
  //\r
  Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CAP_REG);\r
  if ((Reg32 & B_CAP_REG_RWBF) != 0) {\r
    MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_WBF);\r
  }\r
\r
  //\r
  // Invalidate the context cache\r
  //\r
  Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG);\r
  if ((Reg64 & B_CCMD_REG_ICC) != 0) {\r
    DEBUG ((DEBUG_ERROR,"ERROR: InvalidateVtdIOTLBGlobal: B_CCMD_REG_ICC is set for VTD(%d)\n",VtdIndex));\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  Reg64 &= ((~B_CCMD_REG_ICC) & (~B_CCMD_REG_CIRG_MASK));\r
  Reg64 |= (B_CCMD_REG_ICC | V_CCMD_REG_CIRG_GLOBAL);\r
  MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG, Reg64);\r
\r
  do {\r
    Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG);\r
  } while ((Reg64 & B_CCMD_REG_ICC) != 0);\r
\r
  //\r
  // Invalidate the IOTLB cache\r
  //\r
\r
  Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);\r
  if ((Reg64 & B_IOTLB_REG_IVT) != 0) {\r
    DEBUG ((DEBUG_ERROR,"ERROR: InvalidateVtdIOTLBGlobal: B_IOTLB_REG_IVT is set for VTD(%d)\n", VtdIndex));\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  Reg64 &= ((~B_IOTLB_REG_IVT) & (~B_IOTLB_REG_IIRG_MASK));\r
  Reg64 |= (B_IOTLB_REG_IVT | V_IOTLB_REG_IIRG_GLOBAL);\r
  MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG, Reg64);\r
\r
  do {\r
    Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);\r
  } while ((Reg64 & B_IOTLB_REG_IVT) != 0);\r
\r
  //\r
  // Disable VTd\r
  //\r
  MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP);\r
  do {\r
    Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);\r
  } while((Reg32 & B_GSTS_REG_RTPS) == 0);\r
\r
  //\r
  // Enable VTd\r
  //\r
  MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_TE);\r
  do {\r
    Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);\r
  } while ((Reg32 & B_GSTS_REG_TE) == 0);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Invalid VTd IOTLB domain.\r
\r
  @param[in]  VtdIndex              The index of VTd engine.\r
  @param[in]  DomainIdentifier      The domain ID of the source.\r
\r
  @retval EFI_SUCCESS           VTd IOTLB domain is invalidated.\r
  @retval EFI_DEVICE_ERROR      VTd IOTLB domain is not invalidated.\r
**/\r
EFI_STATUS\r
InvalidateVtdIOTLBDomain (\r
  IN UINTN  VtdIndex,\r
  IN UINT16 DomainIdentifier\r
  )\r
{\r
  UINT64  Reg64;\r
\r
  if (!mVtdEnabled) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  DEBUG((DEBUG_VERBOSE, "InvalidateVtdIOTLBDomain(%d): 0x%016lx (0x%04x)\n", VtdIndex, DomainIdentifier));\r
\r
  //\r
  // Invalidate the context cache\r
  //\r
  Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG);\r
  if ((Reg64 & B_CCMD_REG_ICC) != 0) {\r
    DEBUG ((DEBUG_ERROR,"ERROR: InvalidateVtdIOTLBDomain: B_CCMD_REG_ICC is set for VTD(%d)\n",VtdIndex));\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  Reg64 &= ((~B_CCMD_REG_ICC) & (~B_CCMD_REG_CIRG_MASK));\r
  Reg64 |= (B_CCMD_REG_ICC | V_CCMD_REG_CIRG_DOMAIN);\r
  Reg64 |= (B_CCMD_REG_ICC | V_CCMD_REG_CIRG_DOMAIN);\r
  MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG, Reg64);\r
\r
  do {\r
    Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG);\r
  } while ((Reg64 & B_CCMD_REG_ICC) != 0);\r
\r
  //\r
  // Invalidate the IOTLB cache\r
  //\r
\r
  Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);\r
  if ((Reg64 & B_IOTLB_REG_IVT) != 0) {\r
    DEBUG ((DEBUG_ERROR,"ERROR: InvalidateVtdIOTLBDomain: B_IOTLB_REG_IVT is set for VTD(%d)\n", VtdIndex));\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  Reg64 &= ((~B_IOTLB_REG_IVT) & (~B_IOTLB_REG_IIRG_MASK));\r
  Reg64 |= (B_IOTLB_REG_IVT | V_IOTLB_REG_IIRG_DOMAIN);\r
  Reg64 |= LShiftU64 (DomainIdentifier, 32);\r
  MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG, Reg64);\r
\r
  do {\r
    Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);\r
  } while ((Reg64 & B_IOTLB_REG_IVT) != 0);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Invalid VTd IOTLB page.\r
\r
  @param[in]  VtdIndex              The index of VTd engine.\r
  @param[in]  Address               The address of IOTLB page.\r
  @param[in]  AddressMode           The address mode of IOTLB page.\r
  @param[in]  DomainIdentifier      The domain ID of the source.\r
\r
  @retval EFI_SUCCESS           VTd IOTLB page is invalidated.\r
  @retval EFI_DEVICE_ERROR      VTd IOTLB page is not invalidated.\r
**/\r
EFI_STATUS\r
InvalidateVtdIOTLBPage (\r
  IN UINTN  VtdIndex,\r
  IN UINT64 Address,\r
  IN UINT8  AddressMode,\r
  IN UINT16 DomainIdentifier\r
  )\r
{\r
  UINT64  Reg64;\r
  UINT64  Data64;\r
\r
  if (!mVtdEnabled) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  DEBUG((DEBUG_VERBOSE, "InvalidateVtdIOTLBPage(%d): 0x%016lx (0x%02x)\n", VtdIndex, Address, AddressMode));\r
\r
  if (mVtdUnitInformation[VtdIndex].CapReg.Bits.PSI != 0) {\r
    Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);\r
    if ((Reg64 & B_IOTLB_REG_IVT) != 0) {\r
      DEBUG ((DEBUG_ERROR,"ERROR: InvalidateVtdIOTLBPage: B_IOTLB_REG_IVT is set for VTD(%d)\n", VtdIndex));\r
      return EFI_DEVICE_ERROR;\r
    }\r
\r
    Data64 = Address | AddressMode;\r
    MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IVA_REG, Data64);\r
\r
    Reg64 &= ((~B_IOTLB_REG_IVT) & (~B_IOTLB_REG_IIRG_MASK));\r
    Reg64 |= (B_IOTLB_REG_IVT | V_IOTLB_REG_IIRG_PAGE);\r
    Reg64 |= LShiftU64 (DomainIdentifier, 32);\r
    MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG, Reg64);\r
\r
    do {\r
      Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);\r
    } while ((Reg64 & B_IOTLB_REG_IVT) != 0);\r
  } else {\r
    InvalidateVtdIOTLBGlobal (VtdIndex);\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Prepare VTD configuration.\r
**/\r
VOID\r
PrepareVtdConfig (\r
  VOID\r
  )\r
{\r
  UINTN         Index;\r
  UINTN         DomainNumber;\r
\r
  for (Index = 0; Index < mVtdUnitNumber; Index++) {\r
    DEBUG ((DEBUG_INFO, "Dump VTd Capability (%d)\n", Index));\r
    mVtdUnitInformation[Index].CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CAP_REG);\r
    DumpVtdCapRegs (&mVtdUnitInformation[Index].CapReg);\r
    mVtdUnitInformation[Index].ECapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_ECAP_REG);\r
    DumpVtdECapRegs (&mVtdUnitInformation[Index].ECapReg);\r
\r
    if ((mVtdUnitInformation[Index].CapReg.Bits.SLLPS & BIT0) == 0) {\r
      DEBUG((DEBUG_WARN, "!!!! 2MB super page is not supported on VTD %d !!!!\n", Index));\r
    }\r
    if ((mVtdUnitInformation[Index].CapReg.Bits.SAGAW & BIT2) == 0) {\r
      DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n", Index));\r
      return ;\r
    }\r
\r
    DomainNumber = (UINTN)1 << (UINT8)((UINTN)mVtdUnitInformation[Index].CapReg.Bits.ND * 2 + 4);\r
    if (mVtdUnitInformation[Index].PciDeviceInfo.PciDescriptorNumber >= DomainNumber) {\r
      DEBUG((DEBUG_ERROR, "!!!! Pci device Number(0x%x) >= DomainNumber(0x%x) !!!!\n", mVtdUnitInformation[Index].PciDeviceInfo.PciDescriptorNumber, DomainNumber));\r
      return ;\r
    }\r
  }\r
  return ;\r
}\r
\r
/**\r
  Enable DMAR translation.\r
\r
  @retval EFI_SUCCESS           DMAR translation is enabled.\r
  @retval EFI_DEVICE_ERROR      DMAR translation is not enabled.\r
**/\r
EFI_STATUS\r
EnableDmar (\r
  VOID\r
  )\r
{\r
  UINTN     Index;\r
  UINT64    Reg64;\r
  UINT32    Reg32;\r
\r
  AsmWbinvd();\r
\r
  for (Index = 0; Index < mVtdUnitNumber; Index++) {\r
    DEBUG((DEBUG_INFO, ">>>>>>EnableDmar() for engine [%d] \n", Index));\r
\r
    if (mVtdUnitInformation[Index].ExtRootEntryTable != NULL) {\r
      DEBUG((DEBUG_INFO, "ExtRootEntryTable 0x%x \n", mVtdUnitInformation[Index].ExtRootEntryTable));\r
      MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADDR_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].ExtRootEntryTable | BIT11);\r
    } else {\r
      DEBUG((DEBUG_INFO, "RootEntryTable 0x%x \n", mVtdUnitInformation[Index].RootEntryTable));\r
      MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADDR_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].RootEntryTable);\r
    }\r
\r
    MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP);\r
\r
    DEBUG((DEBUG_INFO, "EnableDmar: waiting for RTPS bit to be set... \n"));\r
    do {\r
      Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);\r
    } while((Reg32 & B_GSTS_REG_RTPS) == 0);\r
\r
    //\r
    // Init DMAr Fault Event and Data registers\r
    //\r
    Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_FEDATA_REG);\r
\r
    //\r
    // Write Buffer Flush before invalidation\r
    //\r
    Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CAP_REG);\r
    if ((Reg32 & B_CAP_REG_RWBF) != 0) {\r
      MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_WBF);\r
    }\r
\r
    //\r
    // Invalidate the context cache\r
    //\r
    Reg64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CCMD_REG);\r
    if ((Reg64 & B_CCMD_REG_ICC) != 0) {\r
      DEBUG ((DEBUG_INFO,"ERROR: EnableDmar: B_CCMD_REG_ICC is set for VTD(%d)\n",Index));\r
      return EFI_DEVICE_ERROR;\r
    }\r
\r
    Reg64 &= ((~B_CCMD_REG_ICC) & (~B_CCMD_REG_CIRG_MASK));\r
    Reg64 |= (B_CCMD_REG_ICC | V_CCMD_REG_CIRG_GLOBAL);\r
    MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CCMD_REG, Reg64);\r
\r
    DEBUG((DEBUG_INFO, "EnableDmar: Waiting B_CCMD_REG_ICC ...\n"));\r
    do {\r
      Reg64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CCMD_REG);\r
    } while ((Reg64 & B_CCMD_REG_ICC) != 0);\r
\r
    //\r
    // Invalidate the IOTLB cache\r
    //\r
    DEBUG((DEBUG_INFO, "EnableDmar: IRO 0x%x\n", mVtdUnitInformation[Index].ECapReg.Bits.IRO));\r
\r
    Reg64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + (mVtdUnitInformation[Index].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);\r
    if ((Reg64 & B_IOTLB_REG_IVT) != 0) {\r
      DEBUG ((DEBUG_INFO,"ERROR: EnableDmar: B_IOTLB_REG_IVT is set for VTD(%d)\n", Index));\r
      return EFI_DEVICE_ERROR;\r
    }\r
\r
    Reg64 &= ((~B_IOTLB_REG_IVT) & (~B_IOTLB_REG_IIRG_MASK));\r
    Reg64 |= (B_IOTLB_REG_IVT | V_IOTLB_REG_IIRG_GLOBAL);\r
    MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + (mVtdUnitInformation[Index].ECapReg.Bits.IRO * 16) + R_IOTLB_REG, Reg64);\r
\r
    DEBUG((DEBUG_INFO, "EnableDmar: Waiting B_IOTLB_REG_IVT ...\n"));\r
    do {\r
      Reg64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + (mVtdUnitInformation[Index].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);\r
    } while ((Reg64 & B_IOTLB_REG_IVT) != 0);\r
\r
    //\r
    // Enable VTd\r
    //\r
    MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_TE);\r
    DEBUG((DEBUG_INFO, "EnableDmar: Waiting B_GSTS_REG_TE ...\n"));\r
    do {\r
      Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);\r
    } while ((Reg32 & B_GSTS_REG_TE) == 0);\r
\r
    DEBUG ((DEBUG_INFO,"VTD (%d) enabled!<<<<<<\n",Index));\r
  }\r
\r
  mVtdEnabled = TRUE;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Disable DMAR translation.\r
\r
  @retval EFI_SUCCESS           DMAR translation is disabled.\r
  @retval EFI_DEVICE_ERROR      DMAR translation is not disabled.\r
**/\r
EFI_STATUS\r
DisableDmar (\r
  VOID\r
  )\r
{\r
  UINTN     Index;\r
  UINT32    Reg32;\r
\r
  AsmWbinvd();\r
\r
  for (Index = 0; Index < mVtdUnitNumber; Index++) {\r
    DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n", Index));\r
\r
    //\r
    // Write Buffer Flush before invalidation\r
    //\r
    Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CAP_REG);\r
    if ((Reg32 & B_CAP_REG_RWBF) != 0) {\r
      MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_WBF);\r
    }\r
\r
    //\r
    // Disable VTd\r
    //\r
    MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP);\r
    do {\r
      Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);\r
    } while((Reg32 & B_GSTS_REG_RTPS) == 0);\r
\r
    Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);\r
    DEBUG((DEBUG_INFO, "DisableDmar: GSTS_REG - 0x%08x\n", Reg32));\r
\r
    DEBUG ((DEBUG_INFO,"VTD (%d) Disabled!<<<<<<\n",Index));\r
  }\r
\r
  mVtdEnabled = FALSE;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Dump VTd capability registers.\r
\r
  @param[in]  CapReg              The capability register.\r
**/\r
VOID\r
DumpVtdCapRegs (\r
  IN VTD_CAP_REG *CapReg\r
  )\r
{\r
  DEBUG((DEBUG_INFO, "  CapReg:\n", CapReg->Uint64));\r
  DEBUG((DEBUG_INFO, "    ND     - 0x%x\n", CapReg->Bits.ND));\r
  DEBUG((DEBUG_INFO, "    AFL    - 0x%x\n", CapReg->Bits.AFL));\r
  DEBUG((DEBUG_INFO, "    RWBF   - 0x%x\n", CapReg->Bits.RWBF));\r
  DEBUG((DEBUG_INFO, "    PLMR   - 0x%x\n", CapReg->Bits.PLMR));\r
  DEBUG((DEBUG_INFO, "    PHMR   - 0x%x\n", CapReg->Bits.PHMR));\r
  DEBUG((DEBUG_INFO, "    CM     - 0x%x\n", CapReg->Bits.CM));\r
  DEBUG((DEBUG_INFO, "    SAGAW  - 0x%x\n", CapReg->Bits.SAGAW));\r
  DEBUG((DEBUG_INFO, "    MGAW   - 0x%x\n", CapReg->Bits.MGAW));\r
  DEBUG((DEBUG_INFO, "    ZLR    - 0x%x\n", CapReg->Bits.ZLR));\r
  DEBUG((DEBUG_INFO, "    FRO    - 0x%x\n", CapReg->Bits.FRO));\r
  DEBUG((DEBUG_INFO, "    SLLPS  - 0x%x\n", CapReg->Bits.SLLPS));\r
  DEBUG((DEBUG_INFO, "    PSI    - 0x%x\n", CapReg->Bits.PSI));\r
  DEBUG((DEBUG_INFO, "    NFR    - 0x%x\n", CapReg->Bits.NFR));\r
  DEBUG((DEBUG_INFO, "    MAMV   - 0x%x\n", CapReg->Bits.MAMV));\r
  DEBUG((DEBUG_INFO, "    DWD    - 0x%x\n", CapReg->Bits.DWD));\r
  DEBUG((DEBUG_INFO, "    DRD    - 0x%x\n", CapReg->Bits.DRD));\r
  DEBUG((DEBUG_INFO, "    FL1GP  - 0x%x\n", CapReg->Bits.FL1GP));\r
  DEBUG((DEBUG_INFO, "    PI     - 0x%x\n", CapReg->Bits.PI));\r
}\r
\r
/**\r
  Dump VTd extended capability registers.\r
\r
  @param[in]  ECapReg              The extended capability register.\r
**/\r
VOID\r
DumpVtdECapRegs (\r
  IN VTD_ECAP_REG *ECapReg\r
  )\r
{\r
  DEBUG((DEBUG_INFO, "  ECapReg:\n", ECapReg->Uint64));\r
  DEBUG((DEBUG_INFO, "    C      - 0x%x\n", ECapReg->Bits.C));\r
  DEBUG((DEBUG_INFO, "    QI     - 0x%x\n", ECapReg->Bits.QI));\r
  DEBUG((DEBUG_INFO, "    DT     - 0x%x\n", ECapReg->Bits.DT));\r
  DEBUG((DEBUG_INFO, "    IR     - 0x%x\n", ECapReg->Bits.IR));\r
  DEBUG((DEBUG_INFO, "    EIM    - 0x%x\n", ECapReg->Bits.EIM));\r
  DEBUG((DEBUG_INFO, "    PT     - 0x%x\n", ECapReg->Bits.PT));\r
  DEBUG((DEBUG_INFO, "    SC     - 0x%x\n", ECapReg->Bits.SC));\r
  DEBUG((DEBUG_INFO, "    IRO    - 0x%x\n", ECapReg->Bits.IRO));\r
  DEBUG((DEBUG_INFO, "    MHMV   - 0x%x\n", ECapReg->Bits.MHMV));\r
  DEBUG((DEBUG_INFO, "    ECS    - 0x%x\n", ECapReg->Bits.ECS));\r
  DEBUG((DEBUG_INFO, "    MTS    - 0x%x\n", ECapReg->Bits.MTS));\r
  DEBUG((DEBUG_INFO, "    NEST   - 0x%x\n", ECapReg->Bits.NEST));\r
  DEBUG((DEBUG_INFO, "    DIS    - 0x%x\n", ECapReg->Bits.DIS));\r
  DEBUG((DEBUG_INFO, "    PASID  - 0x%x\n", ECapReg->Bits.PASID));\r
  DEBUG((DEBUG_INFO, "    PRS    - 0x%x\n", ECapReg->Bits.PRS));\r
  DEBUG((DEBUG_INFO, "    ERS    - 0x%x\n", ECapReg->Bits.ERS));\r
  DEBUG((DEBUG_INFO, "    SRS    - 0x%x\n", ECapReg->Bits.SRS));\r
  DEBUG((DEBUG_INFO, "    NWFS   - 0x%x\n", ECapReg->Bits.NWFS));\r
  DEBUG((DEBUG_INFO, "    EAFS   - 0x%x\n", ECapReg->Bits.EAFS));\r
  DEBUG((DEBUG_INFO, "    PSS    - 0x%x\n", ECapReg->Bits.PSS));\r
}\r
\r
/**\r
  Dump VTd registers.\r
\r
  @param[in]  VtdIndex              The index of VTd engine.\r
**/\r
VOID\r
DumpVtdRegs (\r
  IN UINTN  VtdIndex\r
  )\r
{\r
  UINTN         Index;\r
  UINT64        Reg64;\r
  VTD_FRCD_REG  FrcdReg;\r
  VTD_CAP_REG   CapReg;\r
  UINT32        Reg32;\r
  VTD_SOURCE_ID SourceId;\r
\r
  DEBUG((DEBUG_INFO, "#### DumpVtdRegs(%d) Begin ####\n", VtdIndex));\r
\r
  Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_VER_REG);\r
  DEBUG((DEBUG_INFO, "  VER_REG     - 0x%08x\n", Reg32));\r
\r
  CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CAP_REG);\r
  DEBUG((DEBUG_INFO, "  CAP_REG     - 0x%016lx\n", CapReg.Uint64));\r
\r
  Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_ECAP_REG);\r
  DEBUG((DEBUG_INFO, "  ECAP_REG    - 0x%016lx\n", Reg64));\r
\r
  Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);\r
  DEBUG((DEBUG_INFO, "  GSTS_REG    - 0x%08x \n", Reg32));\r
\r
  Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_RTADDR_REG);\r
  DEBUG((DEBUG_INFO, "  RTADDR_REG  - 0x%016lx\n", Reg64));\r
\r
  Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG);\r
  DEBUG((DEBUG_INFO, "  CCMD_REG    - 0x%016lx\n", Reg64));\r
\r
  Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FSTS_REG);\r
  DEBUG((DEBUG_INFO, "  FSTS_REG    - 0x%08x\n", Reg32));\r
\r
  Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FECTL_REG);\r
  DEBUG((DEBUG_INFO, "  FECTL_REG   - 0x%08x\n", Reg32));\r
\r
  Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FEDATA_REG);\r
  DEBUG((DEBUG_INFO, "  FEDATA_REG  - 0x%08x\n", Reg32));\r
\r
  Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FEADDR_REG);\r
  DEBUG((DEBUG_INFO, "  FEADDR_REG  - 0x%08x\n",Reg32));\r
\r
  Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FEUADDR_REG);\r
  DEBUG((DEBUG_INFO, "  FEUADDR_REG - 0x%08x\n",Reg32));\r
\r
  for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {\r
    FrcdReg.Uint64[0] = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG));\r
    FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));\r
    DEBUG((DEBUG_INFO, "  FRCD_REG[%d] - 0x%016lx %016lx\n", Index, FrcdReg.Uint64[1], FrcdReg.Uint64[0]));\r
    if (FrcdReg.Uint64[1] != 0 || FrcdReg.Uint64[0] != 0) {\r
      DEBUG((DEBUG_INFO, "    Fault Info - 0x%016lx\n", LShiftU64(FrcdReg.Bits.FI, 12)));\r
      SourceId.Uint16 = (UINT16)FrcdReg.Bits.SID;\r
      DEBUG((DEBUG_INFO, "    Source - B%02x D%02x F%02x\n", SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));\r
      DEBUG((DEBUG_INFO, "    Type - %x (%a)\n", FrcdReg.Bits.T, FrcdReg.Bits.T ? "read" : "write"));\r
      DEBUG((DEBUG_INFO, "    Reason - %x\n", FrcdReg.Bits.FR));\r
    }\r
  }\r
\r
  Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IVA_REG);\r
  DEBUG((DEBUG_INFO, "  IVA_REG     - 0x%016lx\n",Reg64));\r
\r
  Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);\r
  DEBUG((DEBUG_INFO, "  IOTLB_REG   - 0x%016lx\n",Reg64));\r
\r
  DEBUG((DEBUG_INFO, "#### DumpVtdRegs(%d) End ####\n", VtdIndex));\r
}\r
\r
/**\r
  Dump VTd registers for all VTd engine.\r
**/\r
VOID\r
DumpVtdRegsAll (\r
  VOID\r
  )\r
{\r
  UINTN       Num;\r
\r
  for (Num = 0; Num < mVtdUnitNumber; Num++) {\r
    DumpVtdRegs (Num);\r
  }\r
}\r
\r
/**\r
  Dump VTd registers if there is error.\r
**/\r
VOID\r
DumpVtdIfError (\r
  VOID\r
  )\r
{\r
  UINTN         Num;\r
  UINTN         Index;\r
  VTD_FRCD_REG  FrcdReg;\r
  VTD_CAP_REG   CapReg;\r
  UINT32        Reg32;\r
  BOOLEAN       HasError;\r
\r
  for (Num = 0; Num < mVtdUnitNumber; Num++) {\r
    HasError = FALSE;\r
    Reg32 = MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG);\r
    if (Reg32 != 0) {\r
      HasError = TRUE;\r
    }\r
    Reg32 = MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FECTL_REG);\r
    if ((Reg32 & BIT30) != 0) {\r
      HasError = TRUE;\r
    }\r
\r
    CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_CAP_REG);\r
    for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {\r
      FrcdReg.Uint64[0] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG));\r
      FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));\r
      if ((FrcdReg.Uint64[0] != 0) || (FrcdReg.Uint64[1] != 0)) {\r
        HasError = TRUE;\r
      }\r
    }\r
\r
    if (HasError) {\r
      DEBUG((DEBUG_INFO, "#### ERROR ####\n"));\r
      DumpVtdRegs (Num);\r
      DEBUG((DEBUG_INFO, "#### ERROR ####\n"));\r
    }\r
  }\r
}\r