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MdeModulePkg/AhciPei: Add AHCI mode ATA device support in PEI
[mirror_edk2.git] / MdeModulePkg / Bus / Ata / AhciPei / AhciPei.h
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HW		 1/** @file\r
2 The AhciPei driver is used to manage ATA hard disk device working under AHCI\r
3 mode at PEI phase.\r
4\r
5 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>\r
6\r
7 This program and the accompanying materials\r
8 are licensed and made available under the terms and conditions\r
9 of the BSD License which accompanies this distribution. The\r
10 full text of the license may be found at\r
11 http://opensource.org/licenses/bsd-license.php\r
12\r
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
15\r
16**/\r
17\r
18#ifndef _AHCI_PEI_H_\r
19#define _AHCI_PEI_H_\r
20\r
21#include <PiPei.h>\r
22\r
23#include <IndustryStandard/Atapi.h>\r
24\r
25#include <Ppi/AtaAhciController.h>\r
26#include <Ppi/IoMmu.h>\r
27#include <Ppi/EndOfPeiPhase.h>\r
28#include <Ppi/AtaPassThru.h>\r
29#include <Ppi/BlockIo2.h>\r
30#include <Ppi/StorageSecurityCommand.h>\r
31\r
32#include <Library/DebugLib.h>\r
33#include <Library/PeiServicesLib.h>\r
34#include <Library/MemoryAllocationLib.h>\r
35#include <Library/BaseMemoryLib.h>\r
36#include <Library/IoLib.h>\r
37#include <Library/TimerLib.h>\r
38\r
39//\r
40// Structure forward declarations\r
41//\r
42typedef struct _PEI_AHCI_CONTROLLER_PRIVATE_DATA PEI_AHCI_CONTROLLER_PRIVATE_DATA;\r
43\r
44#include "AhciPeiPassThru.h"\r
45#include "AhciPeiStorageSecurity.h"\r
46\r
47//\r
48// ATA AHCI driver implementation related definitions\r
49//\r
50//\r
51// Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.\r
52// The value is in millisecond units. Add a bit of margin for robustness.\r
53//\r
54#define AHCI_BUS_PHY_DETECT_TIMEOUT 15\r
55//\r
56// Refer SATA1.0a spec, the bus reset time should be less than 1s.\r
57// The value is in 100ns units.\r
58//\r
59#define AHCI_PEI_RESET_TIMEOUT 10000000\r
60//\r
61// Time out Value for ATA pass through protocol, in 100ns units.\r
62//\r
63#define ATA_TIMEOUT 30000000\r
64//\r
65// Maximal number of Physical Region Descriptor Table entries supported.\r
66//\r
67#define AHCI_MAX_PRDT_NUMBER 8\r
68\r
69#define AHCI_CAPABILITY_OFFSET 0x0000\r
70#define AHCI_CAP_SAM BIT18\r
71#define AHCI_CAP_SSS BIT27\r
72\r
73#define AHCI_GHC_OFFSET 0x0004\r
74#define AHCI_GHC_RESET BIT0\r
75#define AHCI_GHC_ENABLE BIT31\r
76\r
77#define AHCI_IS_OFFSET 0x0008\r
78#define AHCI_PI_OFFSET 0x000C\r
79\r
80#define AHCI_MAX_PORTS 32\r
81\r
82typedef struct {\r
83 UINT32 Lower32;\r
84 UINT32 Upper32;\r
85} DATA_32;\r
86\r
87typedef union {\r
88 DATA_32 Uint32;\r
89 UINT64 Uint64;\r
90} DATA_64;\r
91\r
92#define AHCI_ATAPI_SIG_MASK 0xFFFF0000\r
93#define AHCI_ATA_DEVICE_SIG 0x00000000\r
94\r
95//\r
96// Each PRDT entry can point to a memory block up to 4M byte\r
97//\r
98#define AHCI_MAX_DATA_PER_PRDT 0x400000\r
99\r
100#define AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device\r
101#define AHCI_FIS_REGISTER_H2D_LENGTH 20\r
102#define AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host\r
103#define AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host\r
104\r
105#define AHCI_D2H_FIS_OFFSET 0x40\r
106#define AHCI_PIO_FIS_OFFSET 0x20\r
107#define AHCI_FIS_TYPE_MASK 0xFF\r
108\r
109//\r
110// Port register\r
111//\r
112#define AHCI_PORT_START 0x0100\r
113#define AHCI_PORT_REG_WIDTH 0x0080\r
114#define AHCI_PORT_CLB 0x0000\r
115#define AHCI_PORT_CLBU 0x0004\r
116#define AHCI_PORT_FB 0x0008\r
117#define AHCI_PORT_FBU 0x000C\r
118#define AHCI_PORT_IS 0x0010\r
119#define AHCI_PORT_IE 0x0014\r
120#define AHCI_PORT_CMD 0x0018\r
121#define AHCI_PORT_CMD_ST BIT0\r
122#define AHCI_PORT_CMD_SUD BIT1\r
123#define AHCI_PORT_CMD_POD BIT2\r
124#define AHCI_PORT_CMD_CLO BIT3\r
125#define AHCI_PORT_CMD_FRE BIT4\r
126#define AHCI_PORT_CMD_FR BIT14\r
127#define AHCI_PORT_CMD_CR BIT15\r
128#define AHCI_PORT_CMD_CPD BIT20\r
129#define AHCI_PORT_CMD_ATAPI BIT24\r
130#define AHCI_PORT_CMD_DLAE BIT25\r
131#define AHCI_PORT_CMD_ALPE BIT26\r
132#define AHCI_PORT_CMD_ACTIVE (1 << 28)\r
133#define AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)\r
134\r
135#define AHCI_PORT_TFD 0x0020\r
136#define AHCI_PORT_TFD_ERR BIT0\r
137#define AHCI_PORT_TFD_DRQ BIT3\r
138#define AHCI_PORT_TFD_BSY BIT7\r
139#define AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)\r
140\r
141#define AHCI_PORT_SIG 0x0024\r
142#define AHCI_PORT_SSTS 0x0028\r
143#define AHCI_PORT_SSTS_DET_MASK 0x000F\r
144#define AHCI_PORT_SSTS_DET 0x0001\r
145#define AHCI_PORT_SSTS_DET_PCE 0x0003\r
146\r
147#define AHCI_PORT_SCTL 0x002C\r
148#define AHCI_PORT_SCTL_IPM_INIT 0x0300\r
149\r
150#define AHCI_PORT_SERR 0x0030\r
151#define AHCI_PORT_CI 0x0038\r
152\r
153#define IS_ALIGNED(addr, size) (((UINTN) (addr) & (size - 1)) == 0)\r
154#define TIMER_PERIOD_SECONDS(Seconds) MultU64x32((UINT64)(Seconds), 10000000)\r
155\r
156#pragma pack(1)\r
157\r
158//\r
159// Received FIS structure\r
160//\r
161typedef struct {\r
162 UINT8 AhciDmaSetupFis[0x1C]; // Dma Setup Fis: offset 0x00\r
163 UINT8 AhciDmaSetupFisRsvd[0x04];\r
164 UINT8 AhciPioSetupFis[0x14]; // Pio Setup Fis: offset 0x20\r
165 UINT8 AhciPioSetupFisRsvd[0x0C];\r
166 UINT8 AhciD2HRegisterFis[0x14]; // D2H Register Fis: offset 0x40\r
167 UINT8 AhciD2HRegisterFisRsvd[0x04];\r
168 UINT64 AhciSetDeviceBitsFis; // Set Device Bits Fix: offset 0x58\r
169 UINT8 AhciUnknownFis[0x40]; // Unkonwn Fis: offset 0x60\r
170 UINT8 AhciUnknownFisRsvd[0x60];\r
171} EFI_AHCI_RECEIVED_FIS;\r
172\r
173//\r
174// Command List structure includes total 32 entries.\r
175// The entry Data structure is listed at the following.\r
176//\r
177typedef struct {\r
178 UINT32 AhciCmdCfl:5; //Command FIS Length\r
179 UINT32 AhciCmdA:1; //ATAPI\r
180 UINT32 AhciCmdW:1; //Write\r
181 UINT32 AhciCmdP:1; //Prefetchable\r
182 UINT32 AhciCmdR:1; //Reset\r
183 UINT32 AhciCmdB:1; //BIST\r
184 UINT32 AhciCmdC:1; //Clear Busy upon R_OK\r
185 UINT32 AhciCmdRsvd:1;\r
186 UINT32 AhciCmdPmp:4; //Port Multiplier Port\r
187 UINT32 AhciCmdPrdtl:16; //Physical Region Descriptor Table Length\r
188 UINT32 AhciCmdPrdbc; //Physical Region Descriptor Byte Count\r
189 UINT32 AhciCmdCtba; //Command Table Descriptor Base Address\r
190 UINT32 AhciCmdCtbau; //Command Table Descriptor Base Address Upper 32-BITs\r
191 UINT32 AhciCmdRsvd1[4];\r
192} EFI_AHCI_COMMAND_LIST;\r
193\r
194//\r
195// This is a software constructed FIS.\r
196// For Data transfer operations, this is the H2D Register FIS format as\r
197// specified in the Serial ATA Revision 2.6 specification.\r
198//\r
199typedef struct {\r
200 UINT8 AhciCFisType;\r
201 UINT8 AhciCFisPmNum:4;\r
202 UINT8 AhciCFisRsvd:1;\r
203 UINT8 AhciCFisRsvd1:1;\r
204 UINT8 AhciCFisRsvd2:1;\r
205 UINT8 AhciCFisCmdInd:1;\r
206 UINT8 AhciCFisCmd;\r
207 UINT8 AhciCFisFeature;\r
208 UINT8 AhciCFisSecNum;\r
209 UINT8 AhciCFisClyLow;\r
210 UINT8 AhciCFisClyHigh;\r
211 UINT8 AhciCFisDevHead;\r
212 UINT8 AhciCFisSecNumExp;\r
213 UINT8 AhciCFisClyLowExp;\r
214 UINT8 AhciCFisClyHighExp;\r
215 UINT8 AhciCFisFeatureExp;\r
216 UINT8 AhciCFisSecCount;\r
217 UINT8 AhciCFisSecCountExp;\r
218 UINT8 AhciCFisRsvd3;\r
219 UINT8 AhciCFisControl;\r
220 UINT8 AhciCFisRsvd4[4];\r
221 UINT8 AhciCFisRsvd5[44];\r
222} EFI_AHCI_COMMAND_FIS;\r
223\r
224//\r
225// ACMD: ATAPI command (12 or 16 bytes)\r
226//\r
227typedef struct {\r
228 UINT8 AtapiCmd[0x10];\r
229} EFI_AHCI_ATAPI_COMMAND;\r
230\r
231//\r
232// Physical Region Descriptor Table includes up to 65535 entries\r
233// The entry data structure is listed at the following.\r
234// the actual entry number comes from the PRDTL field in the command\r
235// list entry for this command slot.\r
236//\r
237typedef struct {\r
238 UINT32 AhciPrdtDba; //Data Base Address\r
239 UINT32 AhciPrdtDbau; //Data Base Address Upper 32-BITs\r
240 UINT32 AhciPrdtRsvd;\r
241 UINT32 AhciPrdtDbc:22; //Data Byte Count\r
242 UINT32 AhciPrdtRsvd1:9;\r
243 UINT32 AhciPrdtIoc:1; //Interrupt on Completion\r
244} EFI_AHCI_COMMAND_PRDT;\r
245\r
246//\r
247// Command table Data strucute which is pointed to by the entry in the command list\r
248//\r
249typedef struct {\r
250 EFI_AHCI_COMMAND_FIS CommandFis; // A software constructed FIS.\r
251 EFI_AHCI_ATAPI_COMMAND AtapiCmd; // 12 or 16 bytes ATAPI cmd.\r
252 UINT8 Reserved[0x30];\r
253 //\r
254 // The scatter/gather list for Data transfer.\r
255 //\r
256 EFI_AHCI_COMMAND_PRDT PrdtTable[AHCI_MAX_PRDT_NUMBER];\r
257} EFI_AHCI_COMMAND_TABLE;\r
258\r
259#pragma pack()\r
260\r
261typedef struct {\r
262 EFI_AHCI_RECEIVED_FIS *AhciRFis;\r
263 EFI_AHCI_COMMAND_LIST *AhciCmdList;\r
264 EFI_AHCI_COMMAND_TABLE *AhciCmdTable;\r
265 UINTN MaxRFisSize;\r
266 UINTN MaxCmdListSize;\r
267 UINTN MaxCmdTableSize;\r
268 VOID *AhciRFisMap;\r
269 VOID *AhciCmdListMap;\r
270 VOID *AhciCmdTableMap;\r
271} EFI_AHCI_REGISTERS;\r
272\r
273//\r
274// Unique signature for AHCI ATA device information structure.\r
275//\r
276#define AHCI_PEI_ATA_DEVICE_DATA_SIGNATURE SIGNATURE_32 ('A', 'P', 'A', 'D')\r
277\r
278//\r
279// AHCI mode device information structure.\r
280//\r
281typedef struct {\r
282 UINT32 Signature;\r
283 LIST_ENTRY Link;\r
284\r
285 UINT16 Port;\r
286 UINT16 PortMultiplier;\r
287 UINT8 FisIndex;\r
288 UINTN DeviceIndex;\r
289 ATA_IDENTIFY_DATA *IdentifyData;\r
290\r
291 BOOLEAN Lba48Bit;\r
292 BOOLEAN TrustComputing;\r
293 UINTN TrustComputingDeviceIndex;\r
294 EFI_PEI_BLOCK_IO2_MEDIA Media;\r
295\r
296 PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private;\r
297} PEI_AHCI_ATA_DEVICE_DATA;\r
298\r
299#define AHCI_PEI_ATA_DEVICE_INFO_FROM_THIS(a) \\r
300 CR (a, \\r
301 PEI_AHCI_ATA_DEVICE_DATA, \\r
302 Link, \\r
303 AHCI_PEI_ATA_DEVICE_DATA_SIGNATURE \\r
304 );\r
305\r
306//\r
307// Unique signature for private data structure.\r
308//\r
309#define AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('A','P','C','P')\r
310\r
311//\r
312// ATA AHCI controller private data structure.\r
313//\r
314struct _PEI_AHCI_CONTROLLER_PRIVATE_DATA {\r
315 UINT32 Signature;\r
316 UINTN MmioBase;\r
317 UINTN DevicePathLength;\r
318 EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
319\r
320 EFI_ATA_PASS_THRU_MODE AtaPassThruMode;\r
321 EDKII_PEI_ATA_PASS_THRU_PPI AtaPassThruPpi;\r
322 EDKII_PEI_STORAGE_SECURITY_CMD_PPI StorageSecurityPpi;\r
323 EFI_PEI_PPI_DESCRIPTOR AtaPassThruPpiList;\r
324 EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;\r
325 EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList;\r
326 EFI_PEI_PPI_DESCRIPTOR StorageSecurityPpiList;\r
327 EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;\r
328\r
329 EFI_AHCI_REGISTERS AhciRegisters;\r
330\r
331 UINT32 PortBitMap;\r
332 UINT32 ActiveDevices;\r
333 UINT32 TrustComputingDevices;\r
334 LIST_ENTRY DeviceList;\r
335\r
336 UINT16 PreviousPort;\r
337 UINT16 PreviousPortMultiplier;\r
338};\r
339\r
340#define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_PASS_THRU(a) \\r
341 CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, AtaPassThruPpi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
342#define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a) \\r
343 CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, BlkIoPpi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
344#define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2(a) \\r
345 CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, BlkIo2Ppi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
346#define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_STROAGE_SECURITY(a) \\r
347 CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, StorageSecurityPpi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
348#define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a) \\r
349 CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
350\r
351//\r
352// Global variables\r
353//\r
354extern UINT32 mMaxTransferBlockNumber[2];\r
355\r
356//\r
357// Internal functions\r
358//\r
359\r
360/**\r
361 Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r
362 OperationBusMasterCommonBuffer64 mapping.\r
363\r
364 @param Pages The number of pages to allocate.\r
365 @param HostAddress A pointer to store the base system memory address of the\r
366 allocated range.\r
367 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
368 access the hosts HostAddress.\r
369 @param Mapping A resulting value to pass to Unmap().\r
370\r
371 @retval EFI_SUCCESS The requested memory pages were allocated.\r
372 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
373 MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
374 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
375 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
376\r
377**/\r
378EFI_STATUS\r
379IoMmuAllocateBuffer (\r
380 IN UINTN Pages,\r
381 OUT VOID **HostAddress,\r
382 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
383 OUT VOID **Mapping\r
384 );\r
385\r
386/**\r
387 Frees memory that was allocated with AllocateBuffer().\r
388\r
389 @param Pages The number of pages to free.\r
390 @param HostAddress The base system memory address of the allocated range.\r
391 @param Mapping The mapping value returned from Map().\r
392\r
393 @retval EFI_SUCCESS The requested memory pages were freed.\r
394 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
395 was not allocated with AllocateBuffer().\r
396\r
397**/\r
398EFI_STATUS\r
399IoMmuFreeBuffer (\r
400 IN UINTN Pages,\r
401 IN VOID *HostAddress,\r
402 IN VOID *Mapping\r
403 );\r
404\r
405/**\r
406 Provides the controller-specific addresses required to access system memory from a\r
407 DMA bus master.\r
408\r
409 @param Operation Indicates if the bus master is going to read or write to system memory.\r
410 @param HostAddress The system memory address to map to the PCI controller.\r
411 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
412 that were mapped.\r
413 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
414 access the hosts HostAddress.\r
415 @param Mapping A resulting value to pass to Unmap().\r
416\r
417 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
418 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
419 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
420 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
421 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
422\r
423**/\r
424EFI_STATUS\r
425IoMmuMap (\r
426 IN EDKII_IOMMU_OPERATION Operation,\r
427 IN VOID *HostAddress,\r
428 IN OUT UINTN *NumberOfBytes,\r
429 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
430 OUT VOID **Mapping\r
431 );\r
432\r
433/**\r
434 Completes the Map() operation and releases any corresponding resources.\r
435\r
436 @param Mapping The mapping value returned from Map().\r
437\r
438 @retval EFI_SUCCESS The range was unmapped.\r
439 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
440 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
441**/\r
442EFI_STATUS\r
443IoMmuUnmap (\r
444 IN VOID *Mapping\r
445 );\r
446\r
447/**\r
448 One notified function to cleanup the allocated DMA buffers at EndOfPei.\r
449\r
450 @param[in] PeiServices Pointer to PEI Services Table.\r
451 @param[in] NotifyDescriptor Pointer to the descriptor for the Notification\r
452 event that caused this function to execute.\r
453 @param[in] Ppi Pointer to the PPI data associated with this function.\r
454\r
455 @retval EFI_SUCCESS The function completes successfully\r
456\r
457**/\r
458EFI_STATUS\r
459EFIAPI\r
460AhciPeimEndOfPei (\r
461 IN EFI_PEI_SERVICES **PeiServices,\r
462 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
463 IN VOID *Ppi\r
464 );\r
465\r
466/**\r
467 Collect the number of bits set within a port bitmap.\r
468\r
469 @param[in] PortBitMap A 32-bit wide bit map of ATA AHCI ports.\r
470\r
471 @retval The number of bits set in the bitmap.\r
472\r
473**/\r
474UINT8\r
475AhciGetNumberOfPortsFromMap (\r
476 IN UINT32 PortBitMap\r
477 );\r
478\r
479/**\r
480 Start a PIO Data transfer on specific port.\r
481\r
482 @param[in] Private The pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA.\r
483 @param[in] Port The number of port.\r
484 @param[in] PortMultiplier The number of port multiplier.\r
485 @param[in] FisIndex The offset index of the FIS base address.\r
486 @param[in] Read The transfer direction.\r
487 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.\r
488 @param[in,out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.\r
489 @param[in,out] MemoryAddr The pointer to the data buffer.\r
490 @param[in] DataCount The data count to be transferred.\r
491 @param[in] Timeout The timeout value of PIO data transfer, uses\r
492 100ns as a unit.\r
493\r
494 @retval EFI_DEVICE_ERROR The PIO data transfer abort with error occurs.\r
495 @retval EFI_TIMEOUT The operation is time out.\r
496 @retval EFI_UNSUPPORTED The device is not ready for transfer.\r
497 @retval EFI_OUT_OF_RESOURCES The operation fails due to lack of resources.\r
498 @retval EFI_SUCCESS The PIO data transfer executes successfully.\r
499\r
500**/\r
501EFI_STATUS\r
502AhciPioTransfer (\r
503 IN PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private,\r
504 IN UINT8 Port,\r
505 IN UINT8 PortMultiplier,\r
506 IN UINT8 FisIndex,\r
507 IN BOOLEAN Read,\r
508 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
509 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
510 IN OUT VOID *MemoryAddr,\r
511 IN UINT32 DataCount,\r
512 IN UINT64 Timeout\r
513 );\r
514\r
515/**\r
516 Start a non data transfer on specific port.\r
517\r
518 @param[in] Private The pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA.\r
519 @param[in] Port The number of port.\r
520 @param[in] PortMultiplier The number of port multiplier.\r
521 @param[in] FisIndex The offset index of the FIS base address.\r
522 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.\r
523 @param[in,out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.\r
524 @param[in] Timeout The timeout value of non data transfer, uses\r
525 100ns as a unit.\r
526\r
527 @retval EFI_DEVICE_ERROR The non data transfer abort with error occurs.\r
528 @retval EFI_TIMEOUT The operation is time out.\r
529 @retval EFI_UNSUPPORTED The device is not ready for transfer.\r
530 @retval EFI_SUCCESS The non data transfer executes successfully.\r
531\r
532**/\r
533EFI_STATUS\r
534AhciNonDataTransfer (\r
535 IN PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private,\r
536 IN UINT8 Port,\r
537 IN UINT8 PortMultiplier,\r
538 IN UINT8 FisIndex,\r
539 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
540 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
541 IN UINT64 Timeout\r
542 );\r
543\r
544/**\r
545 Initialize ATA host controller at AHCI mode.\r
546\r
547 The function is designed to initialize ATA host controller.\r
548\r
549 @param[in,out] Private A pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA instance.\r
550\r
551 @retval EFI_SUCCESS The ATA AHCI controller is initialized successfully.\r
552 @retval EFI_OUT_OF_RESOURCES Not enough resource to complete while initializing\r
553 the controller.\r
554 @retval Others A device error occurred while initializing the\r
555 controller.\r
556\r
557**/\r
558EFI_STATUS\r
559AhciModeInitialization (\r
560 IN OUT PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private\r
561 );\r
562\r
563/**\r
564 Trust transfer data from/to ATA device.\r
565\r
566 This function performs one ATA pass through transaction to do a trust transfer\r
567 from/to ATA device. It chooses the appropriate ATA command and protocol to invoke\r
568 PassThru interface of ATA pass through.\r
569\r
570 @param[in] DeviceData Pointer to PEI_AHCI_ATA_DEVICE_DATA structure.\r
571 @param[in,out] Buffer The pointer to the current transaction buffer.\r
572 @param[in] SecurityProtocolId\r
573 The value of the "Security Protocol" parameter\r
574 of the security protocol command to be sent.\r
575 @param[in] SecurityProtocolSpecificData\r
576 The value of the "Security Protocol Specific"\r
577 parameter of the security protocol command to\r
578 be sent.\r
579 @param[in] TransferLength The block number or sector count of the transfer.\r
580 @param[in] IsTrustSend Indicates whether it is a trust send operation\r
581 or not.\r
582 @param[in] Timeout The timeout, in 100ns units, to use for the execution\r
583 of the security protocol command. A Timeout value\r
584 of 0 means that this function will wait indefinitely\r
585 for the security protocol command to execute. If\r
586 Timeout is greater than zero, then this function\r
587 will return EFI_TIMEOUT if the time required to\r
588 execute the receive data command is greater than\r
589 Timeout.\r
590 @param[out] TransferLengthOut\r
591 A pointer to a buffer to store the size in bytes\r
592 of the data written to the buffer. Ignore it when\r
593 IsTrustSend is TRUE.\r
594\r
595 @retval EFI_SUCCESS The data transfer is complete successfully.\r
596 @return others Some error occurs when transferring data.\r
597\r
598**/\r
599EFI_STATUS\r
600TrustTransferAtaDevice (\r
601 IN PEI_AHCI_ATA_DEVICE_DATA *DeviceData,\r
602 IN OUT VOID *Buffer,\r
603 IN UINT8 SecurityProtocolId,\r
604 IN UINT16 SecurityProtocolSpecificData,\r
605 IN UINTN TransferLength,\r
606 IN BOOLEAN IsTrustSend,\r
607 IN UINT64 Timeout,\r
608 OUT UINTN *TransferLengthOut\r
609 );\r
610\r
611/**\r
612 Returns a pointer to the next node in a device path.\r
613\r
614 If Node is NULL, then ASSERT().\r
615\r
616 @param Node A pointer to a device path node data structure.\r
617\r
618 @return a pointer to the device path node that follows the device path node\r
619 specified by Node.\r
620\r
621**/\r
622EFI_DEVICE_PATH_PROTOCOL *\r
623NextDevicePathNode (\r
624 IN CONST VOID *Node\r
625 );\r
626\r
627/**\r
628 Get the size of the current device path instance.\r
629\r
630 @param[in] DevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL\r
631 structure.\r
632 @param[out] InstanceSize The size of the current device path instance.\r
633 @param[out] EntireDevicePathEnd Indicate whether the instance is the last\r
634 one in the device path strucure.\r
635\r
636 @retval EFI_SUCCESS The size of the current device path instance is fetched.\r
637 @retval Others Fails to get the size of the current device path instance.\r
638\r
639**/\r
640EFI_STATUS\r
641GetDevicePathInstanceSize (\r
642 IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
643 OUT UINTN *InstanceSize,\r
644 OUT BOOLEAN *EntireDevicePathEnd\r
645 );\r
646\r
647/**\r
648 Check the validity of the device path of a ATA AHCI host controller.\r
649\r
650 @param[in] DevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL\r
651 structure.\r
652 @param[in] DevicePathLength The length of the device path.\r
653\r
654 @retval EFI_SUCCESS The device path is valid.\r
655 @retval EFI_INVALID_PARAMETER The device path is invalid.\r
656\r
657**/\r
658EFI_STATUS\r
659AhciIsHcDevicePathValid (\r
660 IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
661 IN UINTN DevicePathLength\r
662 );\r
663\r
664/**\r
665 Build the device path for an ATA device with given port and port multiplier number.\r
666\r
667 @param[in] Private A pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA\r
668 data structure.\r
669 @param[in] Port The given port number.\r
670 @param[in] PortMultiplierPort The given port multiplier number.\r
671 @param[out] DevicePathLength The length of the device path in bytes specified\r
672 by DevicePath.\r
673 @param[out] DevicePath The device path of ATA device.\r
674\r
675 @retval EFI_SUCCESS The operation succeeds.\r
676 @retval EFI_INVALID_PARAMETER The parameters are invalid.\r
677 @retval EFI_OUT_OF_RESOURCES The operation fails due to lack of resources.\r
678\r
679**/\r
680EFI_STATUS\r
681AhciBuildDevicePath (\r
682 IN PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private,\r
683 IN UINT16 Port,\r
684 IN UINT16 PortMultiplierPort,\r
685 OUT UINTN *DevicePathLength,\r
686 OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
687 );\r
688\r
689/**\r
690 Collect the ports that need to be enumerated on a controller for S3 phase.\r
691\r
692 @param[in] HcDevicePath Device path of the controller.\r
693 @param[in] HcDevicePathLength Length of the device path specified by\r
694 HcDevicePath.\r
695 @param[out] PortBitMap Bitmap that indicates the ports that need\r
696 to be enumerated on the controller.\r
697\r
698 @retval The number of ports that need to be enumerated.\r
699\r
700**/\r
701UINT8\r
702AhciS3GetEumeratePorts (\r
703 IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,\r
704 IN UINTN HcDevicePathLength,\r
705 OUT UINT32 *PortBitMap\r
706 );\r
707\r
708#endif\r
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