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[mirror_edk2.git] / MdeModulePkg / Bus / Ata / AhciPei / AhciPei.h
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87bc3f19
HW		 1/** @file\r
2 The AhciPei driver is used to manage ATA hard disk device working under AHCI\r
3 mode at PEI phase.\r
4\r
5 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>\r
6\r
9d510e61 7 SPDX-License-Identifier: BSD-2-Clause-Patent\r
87bc3f19
HW		 8\r
9**/\r
10\r
11#ifndef _AHCI_PEI_H_\r
12#define _AHCI_PEI_H_\r
13\r
14#include <PiPei.h>\r
15\r
16#include <IndustryStandard/Atapi.h>\r
17\r
18#include <Ppi/AtaAhciController.h>\r
19#include <Ppi/IoMmu.h>\r
20#include <Ppi/EndOfPeiPhase.h>\r
21#include <Ppi/AtaPassThru.h>\r
22#include <Ppi/BlockIo2.h>\r
23#include <Ppi/StorageSecurityCommand.h>\r
24\r
25#include <Library/DebugLib.h>\r
26#include <Library/PeiServicesLib.h>\r
27#include <Library/MemoryAllocationLib.h>\r
28#include <Library/BaseMemoryLib.h>\r
29#include <Library/IoLib.h>\r
30#include <Library/TimerLib.h>\r
31\r
32//\r
33// Structure forward declarations\r
34//\r
35typedef struct _PEI_AHCI_CONTROLLER_PRIVATE_DATA PEI_AHCI_CONTROLLER_PRIVATE_DATA;\r
36\r
37#include "AhciPeiPassThru.h"\r
38#include "AhciPeiStorageSecurity.h"\r
39\r
40//\r
41// ATA AHCI driver implementation related definitions\r
42//\r
43//\r
44// Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.\r
45// The value is in millisecond units. Add a bit of margin for robustness.\r
46//\r
47#define AHCI_BUS_PHY_DETECT_TIMEOUT 15\r
48//\r
49// Refer SATA1.0a spec, the bus reset time should be less than 1s.\r
50// The value is in 100ns units.\r
51//\r
52#define AHCI_PEI_RESET_TIMEOUT 10000000\r
53//\r
54// Time out Value for ATA pass through protocol, in 100ns units.\r
55//\r
56#define ATA_TIMEOUT 30000000\r
57//\r
58// Maximal number of Physical Region Descriptor Table entries supported.\r
59//\r
60#define AHCI_MAX_PRDT_NUMBER 8\r
61\r
62#define AHCI_CAPABILITY_OFFSET 0x0000\r
63#define AHCI_CAP_SAM BIT18\r
64#define AHCI_CAP_SSS BIT27\r
65\r
66#define AHCI_GHC_OFFSET 0x0004\r
67#define AHCI_GHC_RESET BIT0\r
68#define AHCI_GHC_ENABLE BIT31\r
69\r
70#define AHCI_IS_OFFSET 0x0008\r
71#define AHCI_PI_OFFSET 0x000C\r
72\r
73#define AHCI_MAX_PORTS 32\r
74\r
75typedef struct {\r
76 UINT32 Lower32;\r
77 UINT32 Upper32;\r
78} DATA_32;\r
79\r
80typedef union {\r
81 DATA_32 Uint32;\r
82 UINT64 Uint64;\r
83} DATA_64;\r
84\r
85#define AHCI_ATAPI_SIG_MASK 0xFFFF0000\r
86#define AHCI_ATA_DEVICE_SIG 0x00000000\r
87\r
88//\r
89// Each PRDT entry can point to a memory block up to 4M byte\r
90//\r
91#define AHCI_MAX_DATA_PER_PRDT 0x400000\r
92\r
93#define AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device\r
94#define AHCI_FIS_REGISTER_H2D_LENGTH 20\r
95#define AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host\r
96#define AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host\r
97\r
98#define AHCI_D2H_FIS_OFFSET 0x40\r
99#define AHCI_PIO_FIS_OFFSET 0x20\r
100#define AHCI_FIS_TYPE_MASK 0xFF\r
101\r
102//\r
103// Port register\r
104//\r
105#define AHCI_PORT_START 0x0100\r
106#define AHCI_PORT_REG_WIDTH 0x0080\r
107#define AHCI_PORT_CLB 0x0000\r
108#define AHCI_PORT_CLBU 0x0004\r
109#define AHCI_PORT_FB 0x0008\r
110#define AHCI_PORT_FBU 0x000C\r
111#define AHCI_PORT_IS 0x0010\r
112#define AHCI_PORT_IE 0x0014\r
113#define AHCI_PORT_CMD 0x0018\r
114#define AHCI_PORT_CMD_ST BIT0\r
115#define AHCI_PORT_CMD_SUD BIT1\r
116#define AHCI_PORT_CMD_POD BIT2\r
117#define AHCI_PORT_CMD_CLO BIT3\r
118#define AHCI_PORT_CMD_FRE BIT4\r
119#define AHCI_PORT_CMD_FR BIT14\r
120#define AHCI_PORT_CMD_CR BIT15\r
121#define AHCI_PORT_CMD_CPD BIT20\r
122#define AHCI_PORT_CMD_ATAPI BIT24\r
123#define AHCI_PORT_CMD_DLAE BIT25\r
124#define AHCI_PORT_CMD_ALPE BIT26\r
125#define AHCI_PORT_CMD_ACTIVE (1 << 28)\r
126#define AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)\r
127\r
128#define AHCI_PORT_TFD 0x0020\r
129#define AHCI_PORT_TFD_ERR BIT0\r
130#define AHCI_PORT_TFD_DRQ BIT3\r
131#define AHCI_PORT_TFD_BSY BIT7\r
132#define AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)\r
133\r
134#define AHCI_PORT_SIG 0x0024\r
135#define AHCI_PORT_SSTS 0x0028\r
136#define AHCI_PORT_SSTS_DET_MASK 0x000F\r
137#define AHCI_PORT_SSTS_DET 0x0001\r
138#define AHCI_PORT_SSTS_DET_PCE 0x0003\r
139\r
140#define AHCI_PORT_SCTL 0x002C\r
141#define AHCI_PORT_SCTL_IPM_INIT 0x0300\r
142\r
143#define AHCI_PORT_SERR 0x0030\r
144#define AHCI_PORT_CI 0x0038\r
145\r
146#define IS_ALIGNED(addr, size) (((UINTN) (addr) & (size - 1)) == 0)\r
147#define TIMER_PERIOD_SECONDS(Seconds) MultU64x32((UINT64)(Seconds), 10000000)\r
148\r
149#pragma pack(1)\r
150\r
151//\r
152// Received FIS structure\r
153//\r
154typedef struct {\r
155 UINT8 AhciDmaSetupFis[0x1C]; // Dma Setup Fis: offset 0x00\r
156 UINT8 AhciDmaSetupFisRsvd[0x04];\r
157 UINT8 AhciPioSetupFis[0x14]; // Pio Setup Fis: offset 0x20\r
158 UINT8 AhciPioSetupFisRsvd[0x0C];\r
159 UINT8 AhciD2HRegisterFis[0x14]; // D2H Register Fis: offset 0x40\r
160 UINT8 AhciD2HRegisterFisRsvd[0x04];\r
161 UINT64 AhciSetDeviceBitsFis; // Set Device Bits Fix: offset 0x58\r
162 UINT8 AhciUnknownFis[0x40]; // Unkonwn Fis: offset 0x60\r
163 UINT8 AhciUnknownFisRsvd[0x60];\r
164} EFI_AHCI_RECEIVED_FIS;\r
165\r
166//\r
167// Command List structure includes total 32 entries.\r
168// The entry Data structure is listed at the following.\r
169//\r
170typedef struct {\r
171 UINT32 AhciCmdCfl:5; //Command FIS Length\r
172 UINT32 AhciCmdA:1; //ATAPI\r
173 UINT32 AhciCmdW:1; //Write\r
174 UINT32 AhciCmdP:1; //Prefetchable\r
175 UINT32 AhciCmdR:1; //Reset\r
176 UINT32 AhciCmdB:1; //BIST\r
177 UINT32 AhciCmdC:1; //Clear Busy upon R_OK\r
178 UINT32 AhciCmdRsvd:1;\r
179 UINT32 AhciCmdPmp:4; //Port Multiplier Port\r
180 UINT32 AhciCmdPrdtl:16; //Physical Region Descriptor Table Length\r
181 UINT32 AhciCmdPrdbc; //Physical Region Descriptor Byte Count\r
182 UINT32 AhciCmdCtba; //Command Table Descriptor Base Address\r
183 UINT32 AhciCmdCtbau; //Command Table Descriptor Base Address Upper 32-BITs\r
184 UINT32 AhciCmdRsvd1[4];\r
185} EFI_AHCI_COMMAND_LIST;\r
186\r
187//\r
188// This is a software constructed FIS.\r
189// For Data transfer operations, this is the H2D Register FIS format as\r
190// specified in the Serial ATA Revision 2.6 specification.\r
191//\r
192typedef struct {\r
193 UINT8 AhciCFisType;\r
194 UINT8 AhciCFisPmNum:4;\r
195 UINT8 AhciCFisRsvd:1;\r
196 UINT8 AhciCFisRsvd1:1;\r
197 UINT8 AhciCFisRsvd2:1;\r
198 UINT8 AhciCFisCmdInd:1;\r
199 UINT8 AhciCFisCmd;\r
200 UINT8 AhciCFisFeature;\r
201 UINT8 AhciCFisSecNum;\r
202 UINT8 AhciCFisClyLow;\r
203 UINT8 AhciCFisClyHigh;\r
204 UINT8 AhciCFisDevHead;\r
205 UINT8 AhciCFisSecNumExp;\r
206 UINT8 AhciCFisClyLowExp;\r
207 UINT8 AhciCFisClyHighExp;\r
208 UINT8 AhciCFisFeatureExp;\r
209 UINT8 AhciCFisSecCount;\r
210 UINT8 AhciCFisSecCountExp;\r
211 UINT8 AhciCFisRsvd3;\r
212 UINT8 AhciCFisControl;\r
213 UINT8 AhciCFisRsvd4[4];\r
214 UINT8 AhciCFisRsvd5[44];\r
215} EFI_AHCI_COMMAND_FIS;\r
216\r
217//\r
218// ACMD: ATAPI command (12 or 16 bytes)\r
219//\r
220typedef struct {\r
221 UINT8 AtapiCmd[0x10];\r
222} EFI_AHCI_ATAPI_COMMAND;\r
223\r
224//\r
225// Physical Region Descriptor Table includes up to 65535 entries\r
226// The entry data structure is listed at the following.\r
227// the actual entry number comes from the PRDTL field in the command\r
228// list entry for this command slot.\r
229//\r
230typedef struct {\r
231 UINT32 AhciPrdtDba; //Data Base Address\r
232 UINT32 AhciPrdtDbau; //Data Base Address Upper 32-BITs\r
233 UINT32 AhciPrdtRsvd;\r
234 UINT32 AhciPrdtDbc:22; //Data Byte Count\r
235 UINT32 AhciPrdtRsvd1:9;\r
236 UINT32 AhciPrdtIoc:1; //Interrupt on Completion\r
237} EFI_AHCI_COMMAND_PRDT;\r
238\r
239//\r
240// Command table Data strucute which is pointed to by the entry in the command list\r
241//\r
242typedef struct {\r
243 EFI_AHCI_COMMAND_FIS CommandFis; // A software constructed FIS.\r
244 EFI_AHCI_ATAPI_COMMAND AtapiCmd; // 12 or 16 bytes ATAPI cmd.\r
245 UINT8 Reserved[0x30];\r
246 //\r
247 // The scatter/gather list for Data transfer.\r
248 //\r
249 EFI_AHCI_COMMAND_PRDT PrdtTable[AHCI_MAX_PRDT_NUMBER];\r
250} EFI_AHCI_COMMAND_TABLE;\r
251\r
252#pragma pack()\r
253\r
254typedef struct {\r
255 EFI_AHCI_RECEIVED_FIS *AhciRFis;\r
256 EFI_AHCI_COMMAND_LIST *AhciCmdList;\r
257 EFI_AHCI_COMMAND_TABLE *AhciCmdTable;\r
258 UINTN MaxRFisSize;\r
259 UINTN MaxCmdListSize;\r
260 UINTN MaxCmdTableSize;\r
261 VOID *AhciRFisMap;\r
262 VOID *AhciCmdListMap;\r
263 VOID *AhciCmdTableMap;\r
264} EFI_AHCI_REGISTERS;\r
265\r
266//\r
267// Unique signature for AHCI ATA device information structure.\r
268//\r
269#define AHCI_PEI_ATA_DEVICE_DATA_SIGNATURE SIGNATURE_32 ('A', 'P', 'A', 'D')\r
270\r
271//\r
272// AHCI mode device information structure.\r
273//\r
274typedef struct {\r
275 UINT32 Signature;\r
276 LIST_ENTRY Link;\r
277\r
278 UINT16 Port;\r
279 UINT16 PortMultiplier;\r
280 UINT8 FisIndex;\r
281 UINTN DeviceIndex;\r
282 ATA_IDENTIFY_DATA *IdentifyData;\r
283\r
284 BOOLEAN Lba48Bit;\r
285 BOOLEAN TrustComputing;\r
286 UINTN TrustComputingDeviceIndex;\r
287 EFI_PEI_BLOCK_IO2_MEDIA Media;\r
288\r
289 PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private;\r
290} PEI_AHCI_ATA_DEVICE_DATA;\r
291\r
292#define AHCI_PEI_ATA_DEVICE_INFO_FROM_THIS(a) \\r
293 CR (a, \\r
294 PEI_AHCI_ATA_DEVICE_DATA, \\r
295 Link, \\r
296 AHCI_PEI_ATA_DEVICE_DATA_SIGNATURE \\r
297 );\r
298\r
299//\r
300// Unique signature for private data structure.\r
301//\r
302#define AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('A','P','C','P')\r
303\r
304//\r
305// ATA AHCI controller private data structure.\r
306//\r
307struct _PEI_AHCI_CONTROLLER_PRIVATE_DATA {\r
308 UINT32 Signature;\r
309 UINTN MmioBase;\r
310 UINTN DevicePathLength;\r
311 EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
312\r
313 EFI_ATA_PASS_THRU_MODE AtaPassThruMode;\r
314 EDKII_PEI_ATA_PASS_THRU_PPI AtaPassThruPpi;\r
315 EDKII_PEI_STORAGE_SECURITY_CMD_PPI StorageSecurityPpi;\r
316 EFI_PEI_PPI_DESCRIPTOR AtaPassThruPpiList;\r
317 EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;\r
318 EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList;\r
319 EFI_PEI_PPI_DESCRIPTOR StorageSecurityPpiList;\r
320 EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;\r
321\r
322 EFI_AHCI_REGISTERS AhciRegisters;\r
323\r
324 UINT32 PortBitMap;\r
325 UINT32 ActiveDevices;\r
326 UINT32 TrustComputingDevices;\r
327 LIST_ENTRY DeviceList;\r
328\r
329 UINT16 PreviousPort;\r
330 UINT16 PreviousPortMultiplier;\r
331};\r
332\r
333#define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_PASS_THRU(a) \\r
334 CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, AtaPassThruPpi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
335#define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a) \\r
336 CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, BlkIoPpi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
337#define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2(a) \\r
338 CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, BlkIo2Ppi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
339#define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_STROAGE_SECURITY(a) \\r
340 CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, StorageSecurityPpi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
341#define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a) \\r
342 CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
343\r
344//\r
345// Global variables\r
346//\r
347extern UINT32 mMaxTransferBlockNumber[2];\r
348\r
349//\r
350// Internal functions\r
351//\r
352\r
353/**\r
354 Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r
355 OperationBusMasterCommonBuffer64 mapping.\r
356\r
357 @param Pages The number of pages to allocate.\r
358 @param HostAddress A pointer to store the base system memory address of the\r
359 allocated range.\r
360 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
361 access the hosts HostAddress.\r
362 @param Mapping A resulting value to pass to Unmap().\r
363\r
364 @retval EFI_SUCCESS The requested memory pages were allocated.\r
365 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
366 MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
367 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
368 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
369\r
370**/\r
371EFI_STATUS\r
372IoMmuAllocateBuffer (\r
373 IN UINTN Pages,\r
374 OUT VOID **HostAddress,\r
375 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
376 OUT VOID **Mapping\r
377 );\r
378\r
379/**\r
380 Frees memory that was allocated with AllocateBuffer().\r
381\r
382 @param Pages The number of pages to free.\r
383 @param HostAddress The base system memory address of the allocated range.\r
384 @param Mapping The mapping value returned from Map().\r
385\r
386 @retval EFI_SUCCESS The requested memory pages were freed.\r
387 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
388 was not allocated with AllocateBuffer().\r
389\r
390**/\r
391EFI_STATUS\r
392IoMmuFreeBuffer (\r
393 IN UINTN Pages,\r
394 IN VOID *HostAddress,\r
395 IN VOID *Mapping\r
396 );\r
397\r
398/**\r
399 Provides the controller-specific addresses required to access system memory from a\r
400 DMA bus master.\r
401\r
402 @param Operation Indicates if the bus master is going to read or write to system memory.\r
403 @param HostAddress The system memory address to map to the PCI controller.\r
404 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
405 that were mapped.\r
406 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
407 access the hosts HostAddress.\r
408 @param Mapping A resulting value to pass to Unmap().\r
409\r
410 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
411 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
412 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
413 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
414 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
415\r
416**/\r
417EFI_STATUS\r
418IoMmuMap (\r
419 IN EDKII_IOMMU_OPERATION Operation,\r
420 IN VOID *HostAddress,\r
421 IN OUT UINTN *NumberOfBytes,\r
422 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
423 OUT VOID **Mapping\r
424 );\r
425\r
426/**\r
427 Completes the Map() operation and releases any corresponding resources.\r
428\r
429 @param Mapping The mapping value returned from Map().\r
430\r
431 @retval EFI_SUCCESS The range was unmapped.\r
432 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
433 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
434**/\r
435EFI_STATUS\r
436IoMmuUnmap (\r
437 IN VOID *Mapping\r
438 );\r
439\r
440/**\r
441 One notified function to cleanup the allocated DMA buffers at EndOfPei.\r
442\r
443 @param[in] PeiServices Pointer to PEI Services Table.\r
444 @param[in] NotifyDescriptor Pointer to the descriptor for the Notification\r
445 event that caused this function to execute.\r
446 @param[in] Ppi Pointer to the PPI data associated with this function.\r
447\r
448 @retval EFI_SUCCESS The function completes successfully\r
449\r
450**/\r
451EFI_STATUS\r
452EFIAPI\r
453AhciPeimEndOfPei (\r
454 IN EFI_PEI_SERVICES **PeiServices,\r
455 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
456 IN VOID *Ppi\r
457 );\r
458\r
459/**\r
460 Collect the number of bits set within a port bitmap.\r
461\r
462 @param[in] PortBitMap A 32-bit wide bit map of ATA AHCI ports.\r
463\r
464 @retval The number of bits set in the bitmap.\r
465\r
466**/\r
467UINT8\r
468AhciGetNumberOfPortsFromMap (\r
469 IN UINT32 PortBitMap\r
470 );\r
471\r
472/**\r
473 Start a PIO Data transfer on specific port.\r
474\r
475 @param[in] Private The pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA.\r
476 @param[in] Port The number of port.\r
477 @param[in] PortMultiplier The number of port multiplier.\r
478 @param[in] FisIndex The offset index of the FIS base address.\r
479 @param[in] Read The transfer direction.\r
480 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.\r
481 @param[in,out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.\r
482 @param[in,out] MemoryAddr The pointer to the data buffer.\r
483 @param[in] DataCount The data count to be transferred.\r
484 @param[in] Timeout The timeout value of PIO data transfer, uses\r
485 100ns as a unit.\r
486\r
487 @retval EFI_DEVICE_ERROR The PIO data transfer abort with error occurs.\r
488 @retval EFI_TIMEOUT The operation is time out.\r
489 @retval EFI_UNSUPPORTED The device is not ready for transfer.\r
490 @retval EFI_OUT_OF_RESOURCES The operation fails due to lack of resources.\r
491 @retval EFI_SUCCESS The PIO data transfer executes successfully.\r
492\r
493**/\r
494EFI_STATUS\r
495AhciPioTransfer (\r
496 IN PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private,\r
497 IN UINT8 Port,\r
498 IN UINT8 PortMultiplier,\r
499 IN UINT8 FisIndex,\r
500 IN BOOLEAN Read,\r
501 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
502 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
503 IN OUT VOID *MemoryAddr,\r
504 IN UINT32 DataCount,\r
505 IN UINT64 Timeout\r
506 );\r
507\r
508/**\r
509 Start a non data transfer on specific port.\r
510\r
511 @param[in] Private The pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA.\r
512 @param[in] Port The number of port.\r
513 @param[in] PortMultiplier The number of port multiplier.\r
514 @param[in] FisIndex The offset index of the FIS base address.\r
515 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.\r
516 @param[in,out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.\r
517 @param[in] Timeout The timeout value of non data transfer, uses\r
518 100ns as a unit.\r
519\r
520 @retval EFI_DEVICE_ERROR The non data transfer abort with error occurs.\r
521 @retval EFI_TIMEOUT The operation is time out.\r
522 @retval EFI_UNSUPPORTED The device is not ready for transfer.\r
523 @retval EFI_SUCCESS The non data transfer executes successfully.\r
524\r
525**/\r
526EFI_STATUS\r
527AhciNonDataTransfer (\r
528 IN PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private,\r
529 IN UINT8 Port,\r
530 IN UINT8 PortMultiplier,\r
531 IN UINT8 FisIndex,\r
532 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
533 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
534 IN UINT64 Timeout\r
535 );\r
536\r
537/**\r
538 Initialize ATA host controller at AHCI mode.\r
539\r
540 The function is designed to initialize ATA host controller.\r
541\r
542 @param[in,out] Private A pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA instance.\r
543\r
544 @retval EFI_SUCCESS The ATA AHCI controller is initialized successfully.\r
545 @retval EFI_OUT_OF_RESOURCES Not enough resource to complete while initializing\r
546 the controller.\r
547 @retval Others A device error occurred while initializing the\r
548 controller.\r
549\r
550**/\r
551EFI_STATUS\r
552AhciModeInitialization (\r
553 IN OUT PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private\r
554 );\r
555\r
556/**\r
557 Trust transfer data from/to ATA device.\r
558\r
559 This function performs one ATA pass through transaction to do a trust transfer\r
560 from/to ATA device. It chooses the appropriate ATA command and protocol to invoke\r
561 PassThru interface of ATA pass through.\r
562\r
563 @param[in] DeviceData Pointer to PEI_AHCI_ATA_DEVICE_DATA structure.\r
564 @param[in,out] Buffer The pointer to the current transaction buffer.\r
565 @param[in] SecurityProtocolId\r
566 The value of the "Security Protocol" parameter\r
567 of the security protocol command to be sent.\r
568 @param[in] SecurityProtocolSpecificData\r
569 The value of the "Security Protocol Specific"\r
570 parameter of the security protocol command to\r
571 be sent.\r
572 @param[in] TransferLength The block number or sector count of the transfer.\r
573 @param[in] IsTrustSend Indicates whether it is a trust send operation\r
574 or not.\r
575 @param[in] Timeout The timeout, in 100ns units, to use for the execution\r
576 of the security protocol command. A Timeout value\r
577 of 0 means that this function will wait indefinitely\r
578 for the security protocol command to execute. If\r
579 Timeout is greater than zero, then this function\r
580 will return EFI_TIMEOUT if the time required to\r
581 execute the receive data command is greater than\r
582 Timeout.\r
583 @param[out] TransferLengthOut\r
584 A pointer to a buffer to store the size in bytes\r
585 of the data written to the buffer. Ignore it when\r
586 IsTrustSend is TRUE.\r
587\r
588 @retval EFI_SUCCESS The data transfer is complete successfully.\r
589 @return others Some error occurs when transferring data.\r
590\r
591**/\r
592EFI_STATUS\r
593TrustTransferAtaDevice (\r
594 IN PEI_AHCI_ATA_DEVICE_DATA *DeviceData,\r
595 IN OUT VOID *Buffer,\r
596 IN UINT8 SecurityProtocolId,\r
597 IN UINT16 SecurityProtocolSpecificData,\r
598 IN UINTN TransferLength,\r
599 IN BOOLEAN IsTrustSend,\r
600 IN UINT64 Timeout,\r
601 OUT UINTN *TransferLengthOut\r
602 );\r
603\r
604/**\r
605 Returns a pointer to the next node in a device path.\r
606\r
607 If Node is NULL, then ASSERT().\r
608\r
609 @param Node A pointer to a device path node data structure.\r
610\r
611 @return a pointer to the device path node that follows the device path node\r
612 specified by Node.\r
613\r
614**/\r
615EFI_DEVICE_PATH_PROTOCOL *\r
616NextDevicePathNode (\r
617 IN CONST VOID *Node\r
618 );\r
619\r
620/**\r
621 Get the size of the current device path instance.\r
622\r
623 @param[in] DevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL\r
624 structure.\r
625 @param[out] InstanceSize The size of the current device path instance.\r
626 @param[out] EntireDevicePathEnd Indicate whether the instance is the last\r
627 one in the device path strucure.\r
628\r
629 @retval EFI_SUCCESS The size of the current device path instance is fetched.\r
630 @retval Others Fails to get the size of the current device path instance.\r
631\r
632**/\r
633EFI_STATUS\r
634GetDevicePathInstanceSize (\r
635 IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
636 OUT UINTN *InstanceSize,\r
637 OUT BOOLEAN *EntireDevicePathEnd\r
638 );\r
639\r
640/**\r
641 Check the validity of the device path of a ATA AHCI host controller.\r
642\r
643 @param[in] DevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL\r
644 structure.\r
645 @param[in] DevicePathLength The length of the device path.\r
646\r
647 @retval EFI_SUCCESS The device path is valid.\r
648 @retval EFI_INVALID_PARAMETER The device path is invalid.\r
649\r
650**/\r
651EFI_STATUS\r
652AhciIsHcDevicePathValid (\r
653 IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
654 IN UINTN DevicePathLength\r
655 );\r
656\r
657/**\r
658 Build the device path for an ATA device with given port and port multiplier number.\r
659\r
660 @param[in] Private A pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA\r
661 data structure.\r
662 @param[in] Port The given port number.\r
663 @param[in] PortMultiplierPort The given port multiplier number.\r
664 @param[out] DevicePathLength The length of the device path in bytes specified\r
665 by DevicePath.\r
666 @param[out] DevicePath The device path of ATA device.\r
667\r
668 @retval EFI_SUCCESS The operation succeeds.\r
669 @retval EFI_INVALID_PARAMETER The parameters are invalid.\r
670 @retval EFI_OUT_OF_RESOURCES The operation fails due to lack of resources.\r
671\r
672**/\r
673EFI_STATUS\r
674AhciBuildDevicePath (\r
675 IN PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private,\r
676 IN UINT16 Port,\r
677 IN UINT16 PortMultiplierPort,\r
678 OUT UINTN *DevicePathLength,\r
679 OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
680 );\r
681\r
682/**\r
683 Collect the ports that need to be enumerated on a controller for S3 phase.\r
684\r
685 @param[in] HcDevicePath Device path of the controller.\r
686 @param[in] HcDevicePathLength Length of the device path specified by\r
687 HcDevicePath.\r
688 @param[out] PortBitMap Bitmap that indicates the ports that need\r
689 to be enumerated on the controller.\r
690\r
691 @retval The number of ports that need to be enumerated.\r
692\r
693**/\r
694UINT8\r
695AhciS3GetEumeratePorts (\r
696 IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,\r
697 IN UINTN HcDevicePathLength,\r
698 OUT UINT32 *PortBitMap\r
699 );\r
700\r
701#endif\r
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