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MdeModulePkg/AhciPei: Add PEI BlockIO support
[mirror_edk2.git] / MdeModulePkg / Bus / Ata / AhciPei / AhciPei.h
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87bc3f19
HW		 1/** @file\r
2 The AhciPei driver is used to manage ATA hard disk device working under AHCI\r
3 mode at PEI phase.\r
4\r
5 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>\r
6\r
9d510e61 7 SPDX-License-Identifier: BSD-2-Clause-Patent\r
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HW		 8\r
9**/\r
10\r
11#ifndef _AHCI_PEI_H_\r
12#define _AHCI_PEI_H_\r
13\r
14#include <PiPei.h>\r
15\r
16#include <IndustryStandard/Atapi.h>\r
17\r
18#include <Ppi/AtaAhciController.h>\r
19#include <Ppi/IoMmu.h>\r
20#include <Ppi/EndOfPeiPhase.h>\r
21#include <Ppi/AtaPassThru.h>\r
b2b8e872 22#include <Ppi/BlockIo.h>\r
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HW		 23#include <Ppi/BlockIo2.h>\r
24#include <Ppi/StorageSecurityCommand.h>\r
25\r
26#include <Library/DebugLib.h>\r
27#include <Library/PeiServicesLib.h>\r
28#include <Library/MemoryAllocationLib.h>\r
29#include <Library/BaseMemoryLib.h>\r
30#include <Library/IoLib.h>\r
31#include <Library/TimerLib.h>\r
32\r
33//\r
34// Structure forward declarations\r
35//\r
36typedef struct _PEI_AHCI_CONTROLLER_PRIVATE_DATA PEI_AHCI_CONTROLLER_PRIVATE_DATA;\r
37\r
38#include "AhciPeiPassThru.h"\r
b2b8e872 39#include "AhciPeiBlockIo.h"\r
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HW		 40#include "AhciPeiStorageSecurity.h"\r
41\r
42//\r
43// ATA AHCI driver implementation related definitions\r
44//\r
45//\r
46// Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.\r
47// The value is in millisecond units. Add a bit of margin for robustness.\r
48//\r
49#define AHCI_BUS_PHY_DETECT_TIMEOUT 15\r
50//\r
51// Refer SATA1.0a spec, the bus reset time should be less than 1s.\r
52// The value is in 100ns units.\r
53//\r
54#define AHCI_PEI_RESET_TIMEOUT 10000000\r
55//\r
56// Time out Value for ATA pass through protocol, in 100ns units.\r
57//\r
58#define ATA_TIMEOUT 30000000\r
59//\r
60// Maximal number of Physical Region Descriptor Table entries supported.\r
61//\r
62#define AHCI_MAX_PRDT_NUMBER 8\r
63\r
64#define AHCI_CAPABILITY_OFFSET 0x0000\r
65#define AHCI_CAP_SAM BIT18\r
66#define AHCI_CAP_SSS BIT27\r
67\r
68#define AHCI_GHC_OFFSET 0x0004\r
69#define AHCI_GHC_RESET BIT0\r
70#define AHCI_GHC_ENABLE BIT31\r
71\r
72#define AHCI_IS_OFFSET 0x0008\r
73#define AHCI_PI_OFFSET 0x000C\r
74\r
75#define AHCI_MAX_PORTS 32\r
76\r
77typedef struct {\r
78 UINT32 Lower32;\r
79 UINT32 Upper32;\r
80} DATA_32;\r
81\r
82typedef union {\r
83 DATA_32 Uint32;\r
84 UINT64 Uint64;\r
85} DATA_64;\r
86\r
87#define AHCI_ATAPI_SIG_MASK 0xFFFF0000\r
88#define AHCI_ATA_DEVICE_SIG 0x00000000\r
89\r
90//\r
91// Each PRDT entry can point to a memory block up to 4M byte\r
92//\r
93#define AHCI_MAX_DATA_PER_PRDT 0x400000\r
94\r
95#define AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device\r
96#define AHCI_FIS_REGISTER_H2D_LENGTH 20\r
97#define AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host\r
98#define AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host\r
99\r
100#define AHCI_D2H_FIS_OFFSET 0x40\r
101#define AHCI_PIO_FIS_OFFSET 0x20\r
102#define AHCI_FIS_TYPE_MASK 0xFF\r
103\r
104//\r
105// Port register\r
106//\r
107#define AHCI_PORT_START 0x0100\r
108#define AHCI_PORT_REG_WIDTH 0x0080\r
109#define AHCI_PORT_CLB 0x0000\r
110#define AHCI_PORT_CLBU 0x0004\r
111#define AHCI_PORT_FB 0x0008\r
112#define AHCI_PORT_FBU 0x000C\r
113#define AHCI_PORT_IS 0x0010\r
114#define AHCI_PORT_IE 0x0014\r
115#define AHCI_PORT_CMD 0x0018\r
116#define AHCI_PORT_CMD_ST BIT0\r
117#define AHCI_PORT_CMD_SUD BIT1\r
118#define AHCI_PORT_CMD_POD BIT2\r
119#define AHCI_PORT_CMD_CLO BIT3\r
120#define AHCI_PORT_CMD_FRE BIT4\r
121#define AHCI_PORT_CMD_FR BIT14\r
122#define AHCI_PORT_CMD_CR BIT15\r
123#define AHCI_PORT_CMD_CPD BIT20\r
124#define AHCI_PORT_CMD_ATAPI BIT24\r
125#define AHCI_PORT_CMD_DLAE BIT25\r
126#define AHCI_PORT_CMD_ALPE BIT26\r
127#define AHCI_PORT_CMD_ACTIVE (1 << 28)\r
128#define AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)\r
129\r
130#define AHCI_PORT_TFD 0x0020\r
131#define AHCI_PORT_TFD_ERR BIT0\r
132#define AHCI_PORT_TFD_DRQ BIT3\r
133#define AHCI_PORT_TFD_BSY BIT7\r
134#define AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)\r
135\r
136#define AHCI_PORT_SIG 0x0024\r
137#define AHCI_PORT_SSTS 0x0028\r
138#define AHCI_PORT_SSTS_DET_MASK 0x000F\r
139#define AHCI_PORT_SSTS_DET 0x0001\r
140#define AHCI_PORT_SSTS_DET_PCE 0x0003\r
141\r
142#define AHCI_PORT_SCTL 0x002C\r
143#define AHCI_PORT_SCTL_IPM_INIT 0x0300\r
144\r
145#define AHCI_PORT_SERR 0x0030\r
146#define AHCI_PORT_CI 0x0038\r
147\r
148#define IS_ALIGNED(addr, size) (((UINTN) (addr) & (size - 1)) == 0)\r
149#define TIMER_PERIOD_SECONDS(Seconds) MultU64x32((UINT64)(Seconds), 10000000)\r
150\r
151#pragma pack(1)\r
152\r
153//\r
154// Received FIS structure\r
155//\r
156typedef struct {\r
157 UINT8 AhciDmaSetupFis[0x1C]; // Dma Setup Fis: offset 0x00\r
158 UINT8 AhciDmaSetupFisRsvd[0x04];\r
159 UINT8 AhciPioSetupFis[0x14]; // Pio Setup Fis: offset 0x20\r
160 UINT8 AhciPioSetupFisRsvd[0x0C];\r
161 UINT8 AhciD2HRegisterFis[0x14]; // D2H Register Fis: offset 0x40\r
162 UINT8 AhciD2HRegisterFisRsvd[0x04];\r
163 UINT64 AhciSetDeviceBitsFis; // Set Device Bits Fix: offset 0x58\r
164 UINT8 AhciUnknownFis[0x40]; // Unkonwn Fis: offset 0x60\r
165 UINT8 AhciUnknownFisRsvd[0x60];\r
166} EFI_AHCI_RECEIVED_FIS;\r
167\r
168//\r
169// Command List structure includes total 32 entries.\r
170// The entry Data structure is listed at the following.\r
171//\r
172typedef struct {\r
173 UINT32 AhciCmdCfl:5; //Command FIS Length\r
174 UINT32 AhciCmdA:1; //ATAPI\r
175 UINT32 AhciCmdW:1; //Write\r
176 UINT32 AhciCmdP:1; //Prefetchable\r
177 UINT32 AhciCmdR:1; //Reset\r
178 UINT32 AhciCmdB:1; //BIST\r
179 UINT32 AhciCmdC:1; //Clear Busy upon R_OK\r
180 UINT32 AhciCmdRsvd:1;\r
181 UINT32 AhciCmdPmp:4; //Port Multiplier Port\r
182 UINT32 AhciCmdPrdtl:16; //Physical Region Descriptor Table Length\r
183 UINT32 AhciCmdPrdbc; //Physical Region Descriptor Byte Count\r
184 UINT32 AhciCmdCtba; //Command Table Descriptor Base Address\r
185 UINT32 AhciCmdCtbau; //Command Table Descriptor Base Address Upper 32-BITs\r
186 UINT32 AhciCmdRsvd1[4];\r
187} EFI_AHCI_COMMAND_LIST;\r
188\r
189//\r
190// This is a software constructed FIS.\r
191// For Data transfer operations, this is the H2D Register FIS format as\r
192// specified in the Serial ATA Revision 2.6 specification.\r
193//\r
194typedef struct {\r
195 UINT8 AhciCFisType;\r
196 UINT8 AhciCFisPmNum:4;\r
197 UINT8 AhciCFisRsvd:1;\r
198 UINT8 AhciCFisRsvd1:1;\r
199 UINT8 AhciCFisRsvd2:1;\r
200 UINT8 AhciCFisCmdInd:1;\r
201 UINT8 AhciCFisCmd;\r
202 UINT8 AhciCFisFeature;\r
203 UINT8 AhciCFisSecNum;\r
204 UINT8 AhciCFisClyLow;\r
205 UINT8 AhciCFisClyHigh;\r
206 UINT8 AhciCFisDevHead;\r
207 UINT8 AhciCFisSecNumExp;\r
208 UINT8 AhciCFisClyLowExp;\r
209 UINT8 AhciCFisClyHighExp;\r
210 UINT8 AhciCFisFeatureExp;\r
211 UINT8 AhciCFisSecCount;\r
212 UINT8 AhciCFisSecCountExp;\r
213 UINT8 AhciCFisRsvd3;\r
214 UINT8 AhciCFisControl;\r
215 UINT8 AhciCFisRsvd4[4];\r
216 UINT8 AhciCFisRsvd5[44];\r
217} EFI_AHCI_COMMAND_FIS;\r
218\r
219//\r
220// ACMD: ATAPI command (12 or 16 bytes)\r
221//\r
222typedef struct {\r
223 UINT8 AtapiCmd[0x10];\r
224} EFI_AHCI_ATAPI_COMMAND;\r
225\r
226//\r
227// Physical Region Descriptor Table includes up to 65535 entries\r
228// The entry data structure is listed at the following.\r
229// the actual entry number comes from the PRDTL field in the command\r
230// list entry for this command slot.\r
231//\r
232typedef struct {\r
233 UINT32 AhciPrdtDba; //Data Base Address\r
234 UINT32 AhciPrdtDbau; //Data Base Address Upper 32-BITs\r
235 UINT32 AhciPrdtRsvd;\r
236 UINT32 AhciPrdtDbc:22; //Data Byte Count\r
237 UINT32 AhciPrdtRsvd1:9;\r
238 UINT32 AhciPrdtIoc:1; //Interrupt on Completion\r
239} EFI_AHCI_COMMAND_PRDT;\r
240\r
241//\r
242// Command table Data strucute which is pointed to by the entry in the command list\r
243//\r
244typedef struct {\r
245 EFI_AHCI_COMMAND_FIS CommandFis; // A software constructed FIS.\r
246 EFI_AHCI_ATAPI_COMMAND AtapiCmd; // 12 or 16 bytes ATAPI cmd.\r
247 UINT8 Reserved[0x30];\r
248 //\r
249 // The scatter/gather list for Data transfer.\r
250 //\r
251 EFI_AHCI_COMMAND_PRDT PrdtTable[AHCI_MAX_PRDT_NUMBER];\r
252} EFI_AHCI_COMMAND_TABLE;\r
253\r
254#pragma pack()\r
255\r
256typedef struct {\r
257 EFI_AHCI_RECEIVED_FIS *AhciRFis;\r
258 EFI_AHCI_COMMAND_LIST *AhciCmdList;\r
259 EFI_AHCI_COMMAND_TABLE *AhciCmdTable;\r
260 UINTN MaxRFisSize;\r
261 UINTN MaxCmdListSize;\r
262 UINTN MaxCmdTableSize;\r
263 VOID *AhciRFisMap;\r
264 VOID *AhciCmdListMap;\r
265 VOID *AhciCmdTableMap;\r
266} EFI_AHCI_REGISTERS;\r
267\r
268//\r
269// Unique signature for AHCI ATA device information structure.\r
270//\r
271#define AHCI_PEI_ATA_DEVICE_DATA_SIGNATURE SIGNATURE_32 ('A', 'P', 'A', 'D')\r
272\r
273//\r
274// AHCI mode device information structure.\r
275//\r
276typedef struct {\r
277 UINT32 Signature;\r
278 LIST_ENTRY Link;\r
279\r
280 UINT16 Port;\r
281 UINT16 PortMultiplier;\r
282 UINT8 FisIndex;\r
283 UINTN DeviceIndex;\r
284 ATA_IDENTIFY_DATA *IdentifyData;\r
285\r
286 BOOLEAN Lba48Bit;\r
287 BOOLEAN TrustComputing;\r
288 UINTN TrustComputingDeviceIndex;\r
289 EFI_PEI_BLOCK_IO2_MEDIA Media;\r
290\r
291 PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private;\r
292} PEI_AHCI_ATA_DEVICE_DATA;\r
293\r
294#define AHCI_PEI_ATA_DEVICE_INFO_FROM_THIS(a) \\r
295 CR (a, \\r
296 PEI_AHCI_ATA_DEVICE_DATA, \\r
297 Link, \\r
298 AHCI_PEI_ATA_DEVICE_DATA_SIGNATURE \\r
299 );\r
300\r
301//\r
302// Unique signature for private data structure.\r
303//\r
304#define AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('A','P','C','P')\r
305\r
306//\r
307// ATA AHCI controller private data structure.\r
308//\r
309struct _PEI_AHCI_CONTROLLER_PRIVATE_DATA {\r
310 UINT32 Signature;\r
311 UINTN MmioBase;\r
312 UINTN DevicePathLength;\r
313 EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
314\r
315 EFI_ATA_PASS_THRU_MODE AtaPassThruMode;\r
316 EDKII_PEI_ATA_PASS_THRU_PPI AtaPassThruPpi;\r
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HW		 317 EFI_PEI_RECOVERY_BLOCK_IO_PPI BlkIoPpi;\r
318 EFI_PEI_RECOVERY_BLOCK_IO2_PPI BlkIo2Ppi;\r
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HW		 319 EDKII_PEI_STORAGE_SECURITY_CMD_PPI StorageSecurityPpi;\r
320 EFI_PEI_PPI_DESCRIPTOR AtaPassThruPpiList;\r
321 EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;\r
322 EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList;\r
323 EFI_PEI_PPI_DESCRIPTOR StorageSecurityPpiList;\r
324 EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;\r
325\r
326 EFI_AHCI_REGISTERS AhciRegisters;\r
327\r
328 UINT32 PortBitMap;\r
329 UINT32 ActiveDevices;\r
330 UINT32 TrustComputingDevices;\r
331 LIST_ENTRY DeviceList;\r
332\r
333 UINT16 PreviousPort;\r
334 UINT16 PreviousPortMultiplier;\r
335};\r
336\r
337#define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_PASS_THRU(a) \\r
338 CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, AtaPassThruPpi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
339#define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a) \\r
340 CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, BlkIoPpi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
341#define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2(a) \\r
342 CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, BlkIo2Ppi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
343#define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_STROAGE_SECURITY(a) \\r
344 CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, StorageSecurityPpi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
345#define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a) \\r
346 CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
347\r
348//\r
349// Global variables\r
350//\r
351extern UINT32 mMaxTransferBlockNumber[2];\r
352\r
353//\r
354// Internal functions\r
355//\r
356\r
357/**\r
358 Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r
359 OperationBusMasterCommonBuffer64 mapping.\r
360\r
361 @param Pages The number of pages to allocate.\r
362 @param HostAddress A pointer to store the base system memory address of the\r
363 allocated range.\r
364 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
365 access the hosts HostAddress.\r
366 @param Mapping A resulting value to pass to Unmap().\r
367\r
368 @retval EFI_SUCCESS The requested memory pages were allocated.\r
369 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
370 MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
371 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
372 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
373\r
374**/\r
375EFI_STATUS\r
376IoMmuAllocateBuffer (\r
377 IN UINTN Pages,\r
378 OUT VOID **HostAddress,\r
379 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
380 OUT VOID **Mapping\r
381 );\r
382\r
383/**\r
384 Frees memory that was allocated with AllocateBuffer().\r
385\r
386 @param Pages The number of pages to free.\r
387 @param HostAddress The base system memory address of the allocated range.\r
388 @param Mapping The mapping value returned from Map().\r
389\r
390 @retval EFI_SUCCESS The requested memory pages were freed.\r
391 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
392 was not allocated with AllocateBuffer().\r
393\r
394**/\r
395EFI_STATUS\r
396IoMmuFreeBuffer (\r
397 IN UINTN Pages,\r
398 IN VOID *HostAddress,\r
399 IN VOID *Mapping\r
400 );\r
401\r
402/**\r
403 Provides the controller-specific addresses required to access system memory from a\r
404 DMA bus master.\r
405\r
406 @param Operation Indicates if the bus master is going to read or write to system memory.\r
407 @param HostAddress The system memory address to map to the PCI controller.\r
408 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
409 that were mapped.\r
410 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
411 access the hosts HostAddress.\r
412 @param Mapping A resulting value to pass to Unmap().\r
413\r
414 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
415 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
416 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
417 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
418 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
419\r
420**/\r
421EFI_STATUS\r
422IoMmuMap (\r
423 IN EDKII_IOMMU_OPERATION Operation,\r
424 IN VOID *HostAddress,\r
425 IN OUT UINTN *NumberOfBytes,\r
426 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
427 OUT VOID **Mapping\r
428 );\r
429\r
430/**\r
431 Completes the Map() operation and releases any corresponding resources.\r
432\r
433 @param Mapping The mapping value returned from Map().\r
434\r
435 @retval EFI_SUCCESS The range was unmapped.\r
436 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
437 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
438**/\r
439EFI_STATUS\r
440IoMmuUnmap (\r
441 IN VOID *Mapping\r
442 );\r
443\r
444/**\r
445 One notified function to cleanup the allocated DMA buffers at EndOfPei.\r
446\r
447 @param[in] PeiServices Pointer to PEI Services Table.\r
448 @param[in] NotifyDescriptor Pointer to the descriptor for the Notification\r
449 event that caused this function to execute.\r
450 @param[in] Ppi Pointer to the PPI data associated with this function.\r
451\r
452 @retval EFI_SUCCESS The function completes successfully\r
453\r
454**/\r
455EFI_STATUS\r
456EFIAPI\r
457AhciPeimEndOfPei (\r
458 IN EFI_PEI_SERVICES **PeiServices,\r
459 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
460 IN VOID *Ppi\r
461 );\r
462\r
463/**\r
464 Collect the number of bits set within a port bitmap.\r
465\r
466 @param[in] PortBitMap A 32-bit wide bit map of ATA AHCI ports.\r
467\r
468 @retval The number of bits set in the bitmap.\r
469\r
470**/\r
471UINT8\r
472AhciGetNumberOfPortsFromMap (\r
473 IN UINT32 PortBitMap\r
474 );\r
475\r
476/**\r
477 Start a PIO Data transfer on specific port.\r
478\r
479 @param[in] Private The pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA.\r
480 @param[in] Port The number of port.\r
481 @param[in] PortMultiplier The number of port multiplier.\r
482 @param[in] FisIndex The offset index of the FIS base address.\r
483 @param[in] Read The transfer direction.\r
484 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.\r
485 @param[in,out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.\r
486 @param[in,out] MemoryAddr The pointer to the data buffer.\r
487 @param[in] DataCount The data count to be transferred.\r
488 @param[in] Timeout The timeout value of PIO data transfer, uses\r
489 100ns as a unit.\r
490\r
491 @retval EFI_DEVICE_ERROR The PIO data transfer abort with error occurs.\r
492 @retval EFI_TIMEOUT The operation is time out.\r
493 @retval EFI_UNSUPPORTED The device is not ready for transfer.\r
494 @retval EFI_OUT_OF_RESOURCES The operation fails due to lack of resources.\r
495 @retval EFI_SUCCESS The PIO data transfer executes successfully.\r
496\r
497**/\r
498EFI_STATUS\r
499AhciPioTransfer (\r
500 IN PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private,\r
501 IN UINT8 Port,\r
502 IN UINT8 PortMultiplier,\r
503 IN UINT8 FisIndex,\r
504 IN BOOLEAN Read,\r
505 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
506 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
507 IN OUT VOID *MemoryAddr,\r
508 IN UINT32 DataCount,\r
509 IN UINT64 Timeout\r
510 );\r
511\r
512/**\r
513 Start a non data transfer on specific port.\r
514\r
515 @param[in] Private The pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA.\r
516 @param[in] Port The number of port.\r
517 @param[in] PortMultiplier The number of port multiplier.\r
518 @param[in] FisIndex The offset index of the FIS base address.\r
519 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.\r
520 @param[in,out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.\r
521 @param[in] Timeout The timeout value of non data transfer, uses\r
522 100ns as a unit.\r
523\r
524 @retval EFI_DEVICE_ERROR The non data transfer abort with error occurs.\r
525 @retval EFI_TIMEOUT The operation is time out.\r
526 @retval EFI_UNSUPPORTED The device is not ready for transfer.\r
527 @retval EFI_SUCCESS The non data transfer executes successfully.\r
528\r
529**/\r
530EFI_STATUS\r
531AhciNonDataTransfer (\r
532 IN PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private,\r
533 IN UINT8 Port,\r
534 IN UINT8 PortMultiplier,\r
535 IN UINT8 FisIndex,\r
536 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
537 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
538 IN UINT64 Timeout\r
539 );\r
540\r
541/**\r
542 Initialize ATA host controller at AHCI mode.\r
543\r
544 The function is designed to initialize ATA host controller.\r
545\r
546 @param[in,out] Private A pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA instance.\r
547\r
548 @retval EFI_SUCCESS The ATA AHCI controller is initialized successfully.\r
549 @retval EFI_OUT_OF_RESOURCES Not enough resource to complete while initializing\r
550 the controller.\r
551 @retval Others A device error occurred while initializing the\r
552 controller.\r
553\r
554**/\r
555EFI_STATUS\r
556AhciModeInitialization (\r
557 IN OUT PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private\r
558 );\r
559\r
b2b8e872
HW		 560/**\r
561 Transfer data from ATA device.\r
562\r
563 This function performs one ATA pass through transaction to transfer data from/to\r
564 ATA device. It chooses the appropriate ATA command and protocol to invoke PassThru\r
565 interface of ATA pass through.\r
566\r
567 @param[in] DeviceData A pointer to PEI_AHCI_ATA_DEVICE_DATA structure.\r
568 @param[in,out] Buffer The pointer to the current transaction buffer.\r
569 @param[in] StartLba The starting logical block address to be accessed.\r
570 @param[in] TransferLength The block number or sector count of the transfer.\r
571 @param[in] IsWrite Indicates whether it is a write operation.\r
572\r
573 @retval EFI_SUCCESS The data transfer is complete successfully.\r
574 @return others Some error occurs when transferring data.\r
575\r
576**/\r
577EFI_STATUS\r
578TransferAtaDevice (\r
579 IN PEI_AHCI_ATA_DEVICE_DATA *DeviceData,\r
580 IN OUT VOID *Buffer,\r
581 IN EFI_LBA StartLba,\r
582 IN UINT32 TransferLength,\r
583 IN BOOLEAN IsWrite\r
584 );\r
585\r
87bc3f19
HW		 586/**\r
587 Trust transfer data from/to ATA device.\r
588\r
589 This function performs one ATA pass through transaction to do a trust transfer\r
590 from/to ATA device. It chooses the appropriate ATA command and protocol to invoke\r
591 PassThru interface of ATA pass through.\r
592\r
593 @param[in] DeviceData Pointer to PEI_AHCI_ATA_DEVICE_DATA structure.\r
594 @param[in,out] Buffer The pointer to the current transaction buffer.\r
595 @param[in] SecurityProtocolId\r
596 The value of the "Security Protocol" parameter\r
597 of the security protocol command to be sent.\r
598 @param[in] SecurityProtocolSpecificData\r
599 The value of the "Security Protocol Specific"\r
600 parameter of the security protocol command to\r
601 be sent.\r
602 @param[in] TransferLength The block number or sector count of the transfer.\r
603 @param[in] IsTrustSend Indicates whether it is a trust send operation\r
604 or not.\r
605 @param[in] Timeout The timeout, in 100ns units, to use for the execution\r
606 of the security protocol command. A Timeout value\r
607 of 0 means that this function will wait indefinitely\r
608 for the security protocol command to execute. If\r
609 Timeout is greater than zero, then this function\r
610 will return EFI_TIMEOUT if the time required to\r
611 execute the receive data command is greater than\r
612 Timeout.\r
613 @param[out] TransferLengthOut\r
614 A pointer to a buffer to store the size in bytes\r
615 of the data written to the buffer. Ignore it when\r
616 IsTrustSend is TRUE.\r
617\r
618 @retval EFI_SUCCESS The data transfer is complete successfully.\r
619 @return others Some error occurs when transferring data.\r
620\r
621**/\r
622EFI_STATUS\r
623TrustTransferAtaDevice (\r
624 IN PEI_AHCI_ATA_DEVICE_DATA *DeviceData,\r
625 IN OUT VOID *Buffer,\r
626 IN UINT8 SecurityProtocolId,\r
627 IN UINT16 SecurityProtocolSpecificData,\r
628 IN UINTN TransferLength,\r
629 IN BOOLEAN IsTrustSend,\r
630 IN UINT64 Timeout,\r
631 OUT UINTN *TransferLengthOut\r
632 );\r
633\r
634/**\r
635 Returns a pointer to the next node in a device path.\r
636\r
637 If Node is NULL, then ASSERT().\r
638\r
639 @param Node A pointer to a device path node data structure.\r
640\r
641 @return a pointer to the device path node that follows the device path node\r
642 specified by Node.\r
643\r
644**/\r
645EFI_DEVICE_PATH_PROTOCOL *\r
646NextDevicePathNode (\r
647 IN CONST VOID *Node\r
648 );\r
649\r
650/**\r
651 Get the size of the current device path instance.\r
652\r
653 @param[in] DevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL\r
654 structure.\r
655 @param[out] InstanceSize The size of the current device path instance.\r
656 @param[out] EntireDevicePathEnd Indicate whether the instance is the last\r
657 one in the device path strucure.\r
658\r
659 @retval EFI_SUCCESS The size of the current device path instance is fetched.\r
660 @retval Others Fails to get the size of the current device path instance.\r
661\r
662**/\r
663EFI_STATUS\r
664GetDevicePathInstanceSize (\r
665 IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
666 OUT UINTN *InstanceSize,\r
667 OUT BOOLEAN *EntireDevicePathEnd\r
668 );\r
669\r
670/**\r
671 Check the validity of the device path of a ATA AHCI host controller.\r
672\r
673 @param[in] DevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL\r
674 structure.\r
675 @param[in] DevicePathLength The length of the device path.\r
676\r
677 @retval EFI_SUCCESS The device path is valid.\r
678 @retval EFI_INVALID_PARAMETER The device path is invalid.\r
679\r
680**/\r
681EFI_STATUS\r
682AhciIsHcDevicePathValid (\r
683 IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
684 IN UINTN DevicePathLength\r
685 );\r
686\r
687/**\r
688 Build the device path for an ATA device with given port and port multiplier number.\r
689\r
690 @param[in] Private A pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA\r
691 data structure.\r
692 @param[in] Port The given port number.\r
693 @param[in] PortMultiplierPort The given port multiplier number.\r
694 @param[out] DevicePathLength The length of the device path in bytes specified\r
695 by DevicePath.\r
696 @param[out] DevicePath The device path of ATA device.\r
697\r
698 @retval EFI_SUCCESS The operation succeeds.\r
699 @retval EFI_INVALID_PARAMETER The parameters are invalid.\r
700 @retval EFI_OUT_OF_RESOURCES The operation fails due to lack of resources.\r
701\r
702**/\r
703EFI_STATUS\r
704AhciBuildDevicePath (\r
705 IN PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private,\r
706 IN UINT16 Port,\r
707 IN UINT16 PortMultiplierPort,\r
708 OUT UINTN *DevicePathLength,\r
709 OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
710 );\r
711\r
712/**\r
713 Collect the ports that need to be enumerated on a controller for S3 phase.\r
714\r
715 @param[in] HcDevicePath Device path of the controller.\r
716 @param[in] HcDevicePathLength Length of the device path specified by\r
717 HcDevicePath.\r
718 @param[out] PortBitMap Bitmap that indicates the ports that need\r
719 to be enumerated on the controller.\r
720\r
721 @retval The number of ports that need to be enumerated.\r
722\r
723**/\r
724UINT8\r
725AhciS3GetEumeratePorts (\r
726 IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,\r
727 IN UINTN HcDevicePathLength,\r
728 OUT UINT32 *PortBitMap\r
729 );\r
730\r
731#endif\r
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