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1 | /** @file\r |
| 2 | Header file for AHCI mode of ATA host controller.\r |
| 3 | \r |
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4 | Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r |
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5 | This program and the accompanying materials \r |
| 6 | are licensed and made available under the terms and conditions of the BSD License \r |
| 7 | which accompanies this distribution. The full text of the license may be found at \r |
| 8 | http://opensource.org/licenses/bsd-license.php \r |
| 9 | \r |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 12 | \r |
| 13 | **/\r |
| 14 | #ifndef __ATA_HC_AHCI_MODE_H__\r |
| 15 | #define __ATA_HC_AHCI_MODE_H__\r |
| 16 | \r |
| 17 | #define EFI_AHCI_BAR_INDEX 0x05\r |
| 18 | \r |
| 19 | #define EFI_AHCI_CAPABILITY_OFFSET 0x0000\r |
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20 | #define EFI_AHCI_CAP_SSS BIT27\r |
| 21 | #define EFI_AHCI_CAP_S64A BIT31\r |
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22 | #define EFI_AHCI_GHC_OFFSET 0x0004\r |
| 23 | #define EFI_AHCI_GHC_RESET BIT0\r |
| 24 | #define EFI_AHCI_GHC_IE BIT1\r |
| 25 | #define EFI_AHCI_GHC_ENABLE BIT31\r |
| 26 | #define EFI_AHCI_IS_OFFSET 0x0008\r |
| 27 | #define EFI_AHCI_PI_OFFSET 0x000C\r |
| 28 | \r |
| 29 | typedef struct {\r |
| 30 | UINT32 Lower32;\r |
| 31 | UINT32 Upper32;\r |
| 32 | } DATA_32;\r |
| 33 | \r |
| 34 | typedef union {\r |
| 35 | DATA_32 Uint32;\r |
| 36 | UINT64 Uint64;\r |
| 37 | } DATA_64;\r |
| 38 | \r |
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39 | //\r |
| 40 | // Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.\r |
| 41 | //\r |
| 42 | #define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 10\r |
| 43 | //\r |
| 44 | // Refer SATA1.0a spec, the FIS enable time should be less than 500ms.\r |
| 45 | //\r |
| 46 | #define EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT EFI_TIMER_PERIOD_MILLISECONDS(500)\r |
| 47 | //\r |
| 48 | // Refer SATA1.0a spec, the bus reset time should be less than 1s.\r |
| 49 | //\r |
| 50 | #define EFI_AHCI_BUS_RESET_TIMEOUT EFI_TIMER_PERIOD_SECONDS(1)\r |
| 51 | \r |
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52 | #define EFI_AHCI_ATAPI_DEVICE_SIG 0xEB140000\r |
| 53 | #define EFI_AHCI_ATA_DEVICE_SIG 0x00000000\r |
| 54 | #define EFI_AHCI_PORT_MULTIPLIER_SIG 0x96690000\r |
| 55 | #define EFI_AHCI_ATAPI_SIG_MASK 0xFFFF0000\r |
| 56 | \r |
| 57 | //\r |
| 58 | // Each PRDT entry can point to a memory block up to 4M byte\r |
| 59 | //\r |
| 60 | #define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000\r |
| 61 | \r |
| 62 | #define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device\r |
| 63 | #define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20 \r |
| 64 | #define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host\r |
| 65 | #define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20\r |
| 66 | #define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host\r |
| 67 | #define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4\r |
| 68 | #define EFI_AHCI_FIS_DMA_SETUP 0x41 //DMA Setup FIS - Bi-directional\r |
| 69 | #define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28\r |
| 70 | #define EFI_AHCI_FIS_DATA 0x46 //Data FIS - Bi-directional\r |
| 71 | #define EFI_AHCI_FIS_BIST 0x58 //BIST Activate FIS - Bi-directional\r |
| 72 | #define EFI_AHCI_FIS_BIST_LENGTH 12\r |
| 73 | #define EFI_AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host\r |
| 74 | #define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20\r |
| 75 | #define EFI_AHCI_FIS_SET_DEVICE 0xA1 //Set Device Bits FIS - Device to Host\r |
| 76 | #define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8\r |
| 77 | \r |
| 78 | #define EFI_AHCI_D2H_FIS_OFFSET 0x40\r |
| 79 | #define EFI_AHCI_DMA_FIS_OFFSET 0x00\r |
| 80 | #define EFI_AHCI_PIO_FIS_OFFSET 0x20\r |
| 81 | #define EFI_AHCI_SDB_FIS_OFFSET 0x58\r |
| 82 | #define EFI_AHCI_FIS_TYPE_MASK 0xFF\r |
| 83 | #define EFI_AHCI_U_FIS_OFFSET 0x60\r |
| 84 | \r |
| 85 | //\r |
| 86 | // Port register\r |
| 87 | //\r |
| 88 | #define EFI_AHCI_PORT_START 0x0100\r |
| 89 | #define EFI_AHCI_PORT_REG_WIDTH 0x0080\r |
| 90 | #define EFI_AHCI_PORT_CLB 0x0000\r |
| 91 | #define EFI_AHCI_PORT_CLBU 0x0004\r |
| 92 | #define EFI_AHCI_PORT_FB 0x0008\r |
| 93 | #define EFI_AHCI_PORT_FBU 0x000C\r |
| 94 | #define EFI_AHCI_PORT_IS 0x0010\r |
| 95 | #define EFI_AHCI_PORT_IS_DHRS BIT0\r |
| 96 | #define EFI_AHCI_PORT_IS_PSS BIT1\r |
| 97 | #define EFI_AHCI_PORT_IS_SSS BIT2\r |
| 98 | #define EFI_AHCI_PORT_IS_SDBS BIT3\r |
| 99 | #define EFI_AHCI_PORT_IS_UFS BIT4\r |
| 100 | #define EFI_AHCI_PORT_IS_DPS BIT5\r |
| 101 | #define EFI_AHCI_PORT_IS_PCS BIT6\r |
| 102 | #define EFI_AHCI_PORT_IS_DIS BIT7\r |
| 103 | #define EFI_AHCI_PORT_IS_PRCS BIT22\r |
| 104 | #define EFI_AHCI_PORT_IS_IPMS BIT23\r |
| 105 | #define EFI_AHCI_PORT_IS_OFS BIT24\r |
| 106 | #define EFI_AHCI_PORT_IS_INFS BIT26\r |
| 107 | #define EFI_AHCI_PORT_IS_IFS BIT27\r |
| 108 | #define EFI_AHCI_PORT_IS_HBDS BIT28\r |
| 109 | #define EFI_AHCI_PORT_IS_HBFS BIT29\r |
| 110 | #define EFI_AHCI_PORT_IS_TFES BIT30\r |
| 111 | #define EFI_AHCI_PORT_IS_CPDS BIT31\r |
| 112 | #define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF\r |
| 113 | #define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F\r |
| 114 | \r |
| 115 | #define EFI_AHCI_PORT_IE 0x0014\r |
| 116 | #define EFI_AHCI_PORT_CMD 0x0018\r |
| 117 | #define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE\r |
| 118 | #define EFI_AHCI_PORT_CMD_ST BIT0\r |
| 119 | #define EFI_AHCI_PORT_CMD_SUD BIT1\r |
| 120 | #define EFI_AHCI_PORT_CMD_POD BIT2\r |
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121 | #define EFI_AHCI_PORT_CMD_CLO BIT3\r |
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122 | #define EFI_AHCI_PORT_CMD_CR BIT15\r |
| 123 | #define EFI_AHCI_PORT_CMD_FRE BIT4\r |
| 124 | #define EFI_AHCI_PORT_CMD_FR BIT14\r |
| 125 | #define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)\r |
| 126 | #define EFI_AHCI_PORT_CMD_PMA BIT17\r |
| 127 | #define EFI_AHCI_PORT_CMD_HPCP BIT18\r |
| 128 | #define EFI_AHCI_PORT_CMD_MPSP BIT19\r |
| 129 | #define EFI_AHCI_PORT_CMD_CPD BIT20\r |
| 130 | #define EFI_AHCI_PORT_CMD_ESP BIT21\r |
| 131 | #define EFI_AHCI_PORT_CMD_ATAPI BIT24\r |
| 132 | #define EFI_AHCI_PORT_CMD_DLAE BIT25\r |
| 133 | #define EFI_AHCI_PORT_CMD_ALPE BIT26\r |
| 134 | #define EFI_AHCI_PORT_CMD_ASP BIT27\r |
| 135 | #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)\r |
| 136 | #define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 )\r |
| 137 | #define EFI_AHCI_PORT_TFD 0x0020\r |
| 138 | #define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)\r |
| 139 | #define EFI_AHCI_PORT_TFD_BSY BIT7\r |
| 140 | #define EFI_AHCI_PORT_TFD_DRQ BIT3\r |
| 141 | #define EFI_AHCI_PORT_TFD_ERR BIT0\r |
| 142 | #define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00\r |
| 143 | #define EFI_AHCI_PORT_SIG 0x0024\r |
| 144 | #define EFI_AHCI_PORT_SSTS 0x0028\r |
| 145 | #define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F\r |
| 146 | #define EFI_AHCI_PORT_SSTS_DET 0x0001\r |
| 147 | #define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003\r |
| 148 | #define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0\r |
| 149 | #define EFI_AHCI_PORT_SCTL 0x002C\r |
| 150 | #define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F\r |
| 151 | #define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK)\r |
| 152 | #define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001\r |
| 153 | #define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003\r |
| 154 | #define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0\r |
| 155 | #define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00\r |
| 156 | #define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300\r |
| 157 | #define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100\r |
| 158 | #define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200\r |
| 159 | #define EFI_AHCI_PORT_SERR 0x0030\r |
| 160 | #define EFI_AHCI_PORT_SERR_RDIE BIT0\r |
| 161 | #define EFI_AHCI_PORT_SERR_RCE BIT1\r |
| 162 | #define EFI_AHCI_PORT_SERR_TDIE BIT8\r |
| 163 | #define EFI_AHCI_PORT_SERR_PCDIE BIT9\r |
| 164 | #define EFI_AHCI_PORT_SERR_PE BIT10\r |
| 165 | #define EFI_AHCI_PORT_SERR_IE BIT11\r |
| 166 | #define EFI_AHCI_PORT_SERR_PRC BIT16\r |
| 167 | #define EFI_AHCI_PORT_SERR_PIE BIT17\r |
| 168 | #define EFI_AHCI_PORT_SERR_CW BIT18\r |
| 169 | #define EFI_AHCI_PORT_SERR_BDE BIT19\r |
| 170 | #define EFI_AHCI_PORT_SERR_DE BIT20\r |
| 171 | #define EFI_AHCI_PORT_SERR_CRCE BIT21\r |
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172 | #define EFI_AHCI_PORT_SERR_HE BIT22\r |
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173 | #define EFI_AHCI_PORT_SERR_LSE BIT23\r |
| 174 | #define EFI_AHCI_PORT_SERR_TSTE BIT24\r |
| 175 | #define EFI_AHCI_PORT_SERR_UFT BIT25\r |
| 176 | #define EFI_AHCI_PORT_SERR_EX BIT26\r |
| 177 | #define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF\r |
| 178 | #define EFI_AHCI_PORT_SACT 0x0034\r |
| 179 | #define EFI_AHCI_PORT_CI 0x0038\r |
| 180 | #define EFI_AHCI_PORT_SNTF 0x003C\r |
| 181 | \r |
| 182 | \r |
| 183 | #pragma pack(1)\r |
| 184 | //\r |
| 185 | // Command List structure includes total 32 entries.\r |
| 186 | // The entry data structure is listed at the following.\r |
| 187 | //\r |
| 188 | typedef struct {\r |
| 189 | UINT32 AhciCmdCfl:5; //Command FIS Length\r |
| 190 | UINT32 AhciCmdA:1; //ATAPI\r |
| 191 | UINT32 AhciCmdW:1; //Write\r |
| 192 | UINT32 AhciCmdP:1; //Prefetchable\r |
| 193 | UINT32 AhciCmdR:1; //Reset\r |
| 194 | UINT32 AhciCmdB:1; //BIST\r |
| 195 | UINT32 AhciCmdC:1; //Clear Busy upon R_OK\r |
| 196 | UINT32 AhciCmdRsvd:1;\r |
| 197 | UINT32 AhciCmdPmp:4; //Port Multiplier Port\r |
| 198 | UINT32 AhciCmdPrdtl:16; //Physical Region Descriptor Table Length\r |
| 199 | UINT32 AhciCmdPrdbc; //Physical Region Descriptor Byte Count\r |
| 200 | UINT32 AhciCmdCtba; //Command Table Descriptor Base Address\r |
| 201 | UINT32 AhciCmdCtbau; //Command Table Descriptor Base Address Upper 32-BITs\r |
| 202 | UINT32 AhciCmdRsvd1[4]; \r |
| 203 | } EFI_AHCI_COMMAND_LIST;\r |
| 204 | \r |
| 205 | //\r |
| 206 | // This is a software constructed FIS.\r |
| 207 | // For data transfer operations, this is the H2D Register FIS format as \r |
| 208 | // specified in the Serial ATA Revision 2.6 specification.\r |
| 209 | //\r |
| 210 | typedef struct {\r |
| 211 | UINT8 AhciCFisType;\r |
| 212 | UINT8 AhciCFisPmNum:4;\r |
| 213 | UINT8 AhciCFisRsvd:1;\r |
| 214 | UINT8 AhciCFisRsvd1:1;\r |
| 215 | UINT8 AhciCFisRsvd2:1;\r |
| 216 | UINT8 AhciCFisCmdInd:1;\r |
| 217 | UINT8 AhciCFisCmd;\r |
| 218 | UINT8 AhciCFisFeature;\r |
| 219 | UINT8 AhciCFisSecNum;\r |
| 220 | UINT8 AhciCFisClyLow;\r |
| 221 | UINT8 AhciCFisClyHigh;\r |
| 222 | UINT8 AhciCFisDevHead;\r |
| 223 | UINT8 AhciCFisSecNumExp;\r |
| 224 | UINT8 AhciCFisClyLowExp;\r |
| 225 | UINT8 AhciCFisClyHighExp;\r |
| 226 | UINT8 AhciCFisFeatureExp;\r |
| 227 | UINT8 AhciCFisSecCount;\r |
| 228 | UINT8 AhciCFisSecCountExp;\r |
| 229 | UINT8 AhciCFisRsvd3;\r |
| 230 | UINT8 AhciCFisControl;\r |
| 231 | UINT8 AhciCFisRsvd4[4];\r |
| 232 | UINT8 AhciCFisRsvd5[44];\r |
| 233 | } EFI_AHCI_COMMAND_FIS;\r |
| 234 | \r |
| 235 | //\r |
| 236 | // ACMD: ATAPI command (12 or 16 bytes)\r |
| 237 | //\r |
| 238 | typedef struct {\r |
| 239 | UINT8 AtapiCmd[0x10];\r |
| 240 | } EFI_AHCI_ATAPI_COMMAND;\r |
| 241 | \r |
| 242 | //\r |
| 243 | // Physical Region Descriptor Table includes up to 65535 entries\r |
| 244 | // The entry data structure is listed at the following.\r |
| 245 | // the actual entry number comes from the PRDTL field in the command\r |
| 246 | // list entry for this command slot. \r |
| 247 | //\r |
| 248 | typedef struct {\r |
| 249 | UINT32 AhciPrdtDba; //Data Base Address\r |
| 250 | UINT32 AhciPrdtDbau; //Data Base Address Upper 32-BITs\r |
| 251 | UINT32 AhciPrdtRsvd;\r |
| 252 | UINT32 AhciPrdtDbc:22; //Data Byte Count\r |
| 253 | UINT32 AhciPrdtRsvd1:9;\r |
| 254 | UINT32 AhciPrdtIoc:1; //Interrupt on Completion\r |
| 255 | } EFI_AHCI_COMMAND_PRDT;\r |
| 256 | \r |
| 257 | //\r |
| 258 | // Command table data strucute which is pointed to by the entry in the command list\r |
| 259 | //\r |
| 260 | typedef struct {\r |
| 261 | EFI_AHCI_COMMAND_FIS CommandFis; // A software constructed FIS.\r |
| 262 | EFI_AHCI_ATAPI_COMMAND AtapiCmd; // 12 or 16 bytes ATAPI cmd.\r |
| 263 | UINT8 Reserved[0x30];\r |
| 264 | EFI_AHCI_COMMAND_PRDT PrdtTable[65535]; // The scatter/gather list for data transfer\r |
| 265 | } EFI_AHCI_COMMAND_TABLE;\r |
| 266 | \r |
| 267 | //\r |
| 268 | // Received FIS structure\r |
| 269 | //\r |
| 270 | typedef struct {\r |
| 271 | UINT8 AhciDmaSetupFis[0x1C]; // Dma Setup Fis: offset 0x00\r |
| 272 | UINT8 AhciDmaSetupFisRsvd[0x04];\r |
| 273 | UINT8 AhciPioSetupFis[0x14]; // Pio Setup Fis: offset 0x20\r |
| 274 | UINT8 AhciPioSetupFisRsvd[0x0C]; \r |
| 275 | UINT8 AhciD2HRegisterFis[0x14]; // D2H Register Fis: offset 0x40\r |
| 276 | UINT8 AhciD2HRegisterFisRsvd[0x04];\r |
| 277 | UINT64 AhciSetDeviceBitsFis; // Set Device Bits Fix: offset 0x58\r |
| 278 | UINT8 AhciUnknownFis[0x40]; // Unkonwn Fis: offset 0x60\r |
| 279 | UINT8 AhciUnknownFisRsvd[0x60]; \r |
| 280 | } EFI_AHCI_RECEIVED_FIS; \r |
| 281 | \r |
| 282 | #pragma pack()\r |
| 283 | \r |
| 284 | typedef struct {\r |
| 285 | EFI_AHCI_RECEIVED_FIS *AhciRFis;\r |
| 286 | EFI_AHCI_COMMAND_LIST *AhciCmdList;\r |
| 287 | EFI_AHCI_COMMAND_TABLE *AhciCommandTable;\r |
| 288 | EFI_AHCI_RECEIVED_FIS *AhciRFisPciAddr;\r |
| 289 | EFI_AHCI_COMMAND_LIST *AhciCmdListPciAddr;\r |
| 290 | EFI_AHCI_COMMAND_TABLE *AhciCommandTablePciAddr;\r |
| 291 | UINT64 MaxCommandListSize;\r |
| 292 | UINT64 MaxCommandTableSize;\r |
| 293 | UINT64 MaxReceiveFisSize;\r |
| 294 | VOID *MapRFis;\r |
| 295 | VOID *MapCmdList;\r |
| 296 | VOID *MapCommandTable;\r |
| 297 | } EFI_AHCI_REGISTERS;\r |
| 298 | \r |
| 299 | /**\r |
| 300 | This function is used to send out ATAPI commands conforms to the Packet Command \r |
| 301 | with PIO Protocol.\r |
| 302 | \r |
| 303 | @param PciIo The PCI IO protocol instance.\r |
| 304 | @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r |
| 305 | @param Port The number of port. \r |
| 306 | @param PortMultiplier The number of port multiplier.\r |
| 307 | @param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.\r |
| 308 | \r |
| 309 | @retval EFI_SUCCESS send out the ATAPI packet command successfully\r |
| 310 | and device sends data successfully.\r |
| 311 | @retval EFI_DEVICE_ERROR the device failed to send data.\r |
| 312 | \r |
| 313 | **/\r |
| 314 | EFI_STATUS\r |
| 315 | EFIAPI\r |
| 316 | AhciPacketCommandExecute (\r |
| 317 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
| 318 | IN EFI_AHCI_REGISTERS *AhciRegisters,\r |
| 319 | IN UINT8 Port,\r |
| 320 | IN UINT8 PortMultiplier,\r |
| 321 | IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet\r |
| 322 | );\r |
| 323 | \r |
| 324 | /**\r |
| 325 | Start command for give slot on specific port.\r |
| 326 | \r |
| 327 | @param PciIo The PCI IO protocol instance.\r |
| 328 | @param Port The number of port.\r |
| 329 | @param CommandSlot The number of CommandSlot.\r |
| 8536cc4b |
330 | @param Timeout The timeout value of start, uses 100ns as a unit.\r |
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331 | \r |
| 332 | @retval EFI_DEVICE_ERROR The command start unsuccessfully.\r |
| 333 | @retval EFI_TIMEOUT The operation is time out.\r |
| 334 | @retval EFI_SUCCESS The command start successfully.\r |
| 335 | \r |
| 336 | **/\r |
| 337 | EFI_STATUS\r |
| 338 | EFIAPI\r |
| 339 | AhciStartCommand (\r |
| 340 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
| 341 | IN UINT8 Port,\r |
| 342 | IN UINT8 CommandSlot,\r |
| 343 | IN UINT64 Timeout\r |
| 344 | );\r |
| 345 | \r |
| 346 | /**\r |
| 347 | Stop command running for giving port\r |
| 348 | \r |
| 349 | @param PciIo The PCI IO protocol instance.\r |
| 350 | @param Port The number of port.\r |
| 8536cc4b |
351 | @param Timeout The timeout value of stop, uses 100ns as a unit.\r |
| a41b5272 |
352 | \r |
| 353 | @retval EFI_DEVICE_ERROR The command stop unsuccessfully.\r |
| 354 | @retval EFI_TIMEOUT The operation is time out.\r |
| 355 | @retval EFI_SUCCESS The command stop successfully.\r |
| 356 | \r |
| 357 | **/\r |
| 358 | EFI_STATUS\r |
| 359 | EFIAPI\r |
| 360 | AhciStopCommand (\r |
| 361 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
| 362 | IN UINT8 Port,\r |
| 363 | IN UINT64 Timeout\r |
| 364 | );\r |
| 365 | \r |
| a41b5272 |
366 | #endif\r |
| 367 | \r |
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