projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| a41b5272 | 1 | /** @file\r |
| 2 | Header file for AHCI mode of ATA host controller.\r | |
| d1102dba | 3 | \r |
| f3100a1a | 4 | Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r |
| 9d510e61 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| a41b5272 | 6 | \r |
| 7 | **/\r | |
| 8 | #ifndef __ATA_HC_AHCI_MODE_H__\r | |
| 9 | #define __ATA_HC_AHCI_MODE_H__\r | |
| 10 | \r | |
| 11 | #define EFI_AHCI_BAR_INDEX 0x05\r | |
| 12 | \r | |
| 13 | #define EFI_AHCI_CAPABILITY_OFFSET 0x0000\r | |
| 1ff1dd0f | 14 | #define EFI_AHCI_CAP_SAM BIT18\r |
| cbd2a4b3 | 15 | #define EFI_AHCI_CAP_SSS BIT27\r |
| 16 | #define EFI_AHCI_CAP_S64A BIT31\r | |
| a41b5272 | 17 | #define EFI_AHCI_GHC_OFFSET 0x0004\r |
| 18 | #define EFI_AHCI_GHC_RESET BIT0\r | |
| 19 | #define EFI_AHCI_GHC_IE BIT1\r | |
| 20 | #define EFI_AHCI_GHC_ENABLE BIT31\r | |
| 21 | #define EFI_AHCI_IS_OFFSET 0x0008\r | |
| 22 | #define EFI_AHCI_PI_OFFSET 0x000C\r | |
| 23 | \r | |
| 6b13aa60 | 24 | #define EFI_AHCI_MAX_PORTS 32\r |
| 25 | \r | |
| f3100a1a RN |
26 | #define AHCI_CAPABILITY2_OFFSET 0x0024\r |
| 27 | #define AHCI_CAP2_SDS BIT3\r | |
| 28 | #define AHCI_CAP2_SADM BIT4\r | |
| 29 | \r | |
| a41b5272 | 30 | typedef struct {\r |
| 31 | UINT32 Lower32;\r | |
| 32 | UINT32 Upper32;\r | |
| 33 | } DATA_32;\r | |
| 34 | \r | |
| 35 | typedef union {\r | |
| 36 | DATA_32 Uint32;\r | |
| 37 | UINT64 Uint64;\r | |
| 38 | } DATA_64;\r | |
| 39 | \r | |
| cbd2a4b3 | 40 | //\r |
| 41 | // Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.\r | |
| 1fb805b1 | 42 | // Add a bit of margin for robustness.\r |
| cbd2a4b3 | 43 | //\r |
| 1fb805b1 | 44 | #define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 15\r |
| cbd2a4b3 | 45 | //\r |
| 46 | // Refer SATA1.0a spec, the FIS enable time should be less than 500ms.\r | |
| 47 | //\r | |
| 48 | #define EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT EFI_TIMER_PERIOD_MILLISECONDS(500)\r | |
| 49 | //\r | |
| 50 | // Refer SATA1.0a spec, the bus reset time should be less than 1s.\r | |
| 51 | //\r | |
| 52 | #define EFI_AHCI_BUS_RESET_TIMEOUT EFI_TIMER_PERIOD_SECONDS(1)\r | |
| 53 | \r | |
| a41b5272 | 54 | #define EFI_AHCI_ATAPI_DEVICE_SIG 0xEB140000\r |
| 55 | #define EFI_AHCI_ATA_DEVICE_SIG 0x00000000\r | |
| 56 | #define EFI_AHCI_PORT_MULTIPLIER_SIG 0x96690000\r | |
| 57 | #define EFI_AHCI_ATAPI_SIG_MASK 0xFFFF0000\r | |
| 58 | \r | |
| 59 | //\r | |
| 60 | // Each PRDT entry can point to a memory block up to 4M byte\r | |
| 61 | //\r | |
| 62 | #define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000\r | |
| 63 | \r | |
| 64 | #define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device\r | |
| d1102dba | 65 | #define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20\r |
| a41b5272 | 66 | #define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host\r |
| 67 | #define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20\r | |
| 68 | #define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host\r | |
| 69 | #define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4\r | |
| 70 | #define EFI_AHCI_FIS_DMA_SETUP 0x41 //DMA Setup FIS - Bi-directional\r | |
| 71 | #define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28\r | |
| 72 | #define EFI_AHCI_FIS_DATA 0x46 //Data FIS - Bi-directional\r | |
| 73 | #define EFI_AHCI_FIS_BIST 0x58 //BIST Activate FIS - Bi-directional\r | |
| 74 | #define EFI_AHCI_FIS_BIST_LENGTH 12\r | |
| 75 | #define EFI_AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host\r | |
| 76 | #define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20\r | |
| 77 | #define EFI_AHCI_FIS_SET_DEVICE 0xA1 //Set Device Bits FIS - Device to Host\r | |
| 78 | #define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8\r | |
| 79 | \r | |
| 80 | #define EFI_AHCI_D2H_FIS_OFFSET 0x40\r | |
| 81 | #define EFI_AHCI_DMA_FIS_OFFSET 0x00\r | |
| 82 | #define EFI_AHCI_PIO_FIS_OFFSET 0x20\r | |
| 83 | #define EFI_AHCI_SDB_FIS_OFFSET 0x58\r | |
| 84 | #define EFI_AHCI_FIS_TYPE_MASK 0xFF\r | |
| 85 | #define EFI_AHCI_U_FIS_OFFSET 0x60\r | |
| 86 | \r | |
| 87 | //\r | |
| 88 | // Port register\r | |
| 89 | //\r | |
| 90 | #define EFI_AHCI_PORT_START 0x0100\r | |
| 91 | #define EFI_AHCI_PORT_REG_WIDTH 0x0080\r | |
| 92 | #define EFI_AHCI_PORT_CLB 0x0000\r | |
| 93 | #define EFI_AHCI_PORT_CLBU 0x0004\r | |
| 94 | #define EFI_AHCI_PORT_FB 0x0008\r | |
| 95 | #define EFI_AHCI_PORT_FBU 0x000C\r | |
| 96 | #define EFI_AHCI_PORT_IS 0x0010\r | |
| 97 | #define EFI_AHCI_PORT_IS_DHRS BIT0\r | |
| 98 | #define EFI_AHCI_PORT_IS_PSS BIT1\r | |
| 99 | #define EFI_AHCI_PORT_IS_SSS BIT2\r | |
| 100 | #define EFI_AHCI_PORT_IS_SDBS BIT3\r | |
| 101 | #define EFI_AHCI_PORT_IS_UFS BIT4\r | |
| 102 | #define EFI_AHCI_PORT_IS_DPS BIT5\r | |
| 103 | #define EFI_AHCI_PORT_IS_PCS BIT6\r | |
| 104 | #define EFI_AHCI_PORT_IS_DIS BIT7\r | |
| 105 | #define EFI_AHCI_PORT_IS_PRCS BIT22\r | |
| 106 | #define EFI_AHCI_PORT_IS_IPMS BIT23\r | |
| 107 | #define EFI_AHCI_PORT_IS_OFS BIT24\r | |
| 108 | #define EFI_AHCI_PORT_IS_INFS BIT26\r | |
| 109 | #define EFI_AHCI_PORT_IS_IFS BIT27\r | |
| 110 | #define EFI_AHCI_PORT_IS_HBDS BIT28\r | |
| 111 | #define EFI_AHCI_PORT_IS_HBFS BIT29\r | |
| 112 | #define EFI_AHCI_PORT_IS_TFES BIT30\r | |
| 113 | #define EFI_AHCI_PORT_IS_CPDS BIT31\r | |
| 114 | #define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF\r | |
| 115 | #define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F\r | |
| 116 | \r | |
| 117 | #define EFI_AHCI_PORT_IE 0x0014\r | |
| 118 | #define EFI_AHCI_PORT_CMD 0x0018\r | |
| 119 | #define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE\r | |
| 120 | #define EFI_AHCI_PORT_CMD_ST BIT0\r | |
| 121 | #define EFI_AHCI_PORT_CMD_SUD BIT1\r | |
| 122 | #define EFI_AHCI_PORT_CMD_POD BIT2\r | |
| cbd2a4b3 | 123 | #define EFI_AHCI_PORT_CMD_CLO BIT3\r |
| a41b5272 | 124 | #define EFI_AHCI_PORT_CMD_CR BIT15\r |
| 125 | #define EFI_AHCI_PORT_CMD_FRE BIT4\r | |
| 126 | #define EFI_AHCI_PORT_CMD_FR BIT14\r | |
| 127 | #define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)\r | |
| 128 | #define EFI_AHCI_PORT_CMD_PMA BIT17\r | |
| 129 | #define EFI_AHCI_PORT_CMD_HPCP BIT18\r | |
| 130 | #define EFI_AHCI_PORT_CMD_MPSP BIT19\r | |
| 131 | #define EFI_AHCI_PORT_CMD_CPD BIT20\r | |
| 132 | #define EFI_AHCI_PORT_CMD_ESP BIT21\r | |
| 133 | #define EFI_AHCI_PORT_CMD_ATAPI BIT24\r | |
| 134 | #define EFI_AHCI_PORT_CMD_DLAE BIT25\r | |
| 135 | #define EFI_AHCI_PORT_CMD_ALPE BIT26\r | |
| 136 | #define EFI_AHCI_PORT_CMD_ASP BIT27\r | |
| 137 | #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)\r | |
| 138 | #define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 )\r | |
| 139 | #define EFI_AHCI_PORT_TFD 0x0020\r | |
| 140 | #define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)\r | |
| 141 | #define EFI_AHCI_PORT_TFD_BSY BIT7\r | |
| 142 | #define EFI_AHCI_PORT_TFD_DRQ BIT3\r | |
| 143 | #define EFI_AHCI_PORT_TFD_ERR BIT0\r | |
| 144 | #define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00\r | |
| 145 | #define EFI_AHCI_PORT_SIG 0x0024\r | |
| 146 | #define EFI_AHCI_PORT_SSTS 0x0028\r | |
| 147 | #define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F\r | |
| 148 | #define EFI_AHCI_PORT_SSTS_DET 0x0001\r | |
| 149 | #define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003\r | |
| 150 | #define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0\r | |
| 151 | #define EFI_AHCI_PORT_SCTL 0x002C\r | |
| 152 | #define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F\r | |
| 153 | #define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK)\r | |
| 154 | #define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001\r | |
| 155 | #define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003\r | |
| 156 | #define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0\r | |
| 157 | #define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00\r | |
| 158 | #define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300\r | |
| 159 | #define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100\r | |
| 160 | #define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200\r | |
| 161 | #define EFI_AHCI_PORT_SERR 0x0030\r | |
| 162 | #define EFI_AHCI_PORT_SERR_RDIE BIT0\r | |
| 163 | #define EFI_AHCI_PORT_SERR_RCE BIT1\r | |
| 164 | #define EFI_AHCI_PORT_SERR_TDIE BIT8\r | |
| 165 | #define EFI_AHCI_PORT_SERR_PCDIE BIT9\r | |
| 166 | #define EFI_AHCI_PORT_SERR_PE BIT10\r | |
| 167 | #define EFI_AHCI_PORT_SERR_IE BIT11\r | |
| 168 | #define EFI_AHCI_PORT_SERR_PRC BIT16\r | |
| 169 | #define EFI_AHCI_PORT_SERR_PIE BIT17\r | |
| 170 | #define EFI_AHCI_PORT_SERR_CW BIT18\r | |
| 171 | #define EFI_AHCI_PORT_SERR_BDE BIT19\r | |
| 172 | #define EFI_AHCI_PORT_SERR_DE BIT20\r | |
| 173 | #define EFI_AHCI_PORT_SERR_CRCE BIT21\r | |
| 490b5ea1 | 174 | #define EFI_AHCI_PORT_SERR_HE BIT22\r |
| a41b5272 | 175 | #define EFI_AHCI_PORT_SERR_LSE BIT23\r |
| 176 | #define EFI_AHCI_PORT_SERR_TSTE BIT24\r | |
| 177 | #define EFI_AHCI_PORT_SERR_UFT BIT25\r | |
| 178 | #define EFI_AHCI_PORT_SERR_EX BIT26\r | |
| 179 | #define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF\r | |
| 180 | #define EFI_AHCI_PORT_SACT 0x0034\r | |
| 181 | #define EFI_AHCI_PORT_CI 0x0038\r | |
| 182 | #define EFI_AHCI_PORT_SNTF 0x003C\r | |
| f3100a1a RN |
183 | #define AHCI_PORT_DEVSLP 0x0044\r |
| 184 | #define AHCI_PORT_DEVSLP_ADSE BIT0\r | |
| 185 | #define AHCI_PORT_DEVSLP_DSP BIT1\r | |
| 186 | #define AHCI_PORT_DEVSLP_DETO_MASK 0x000003FC\r | |
| 187 | #define AHCI_PORT_DEVSLP_MDAT_MASK 0x00007C00\r | |
| 188 | #define AHCI_PORT_DEVSLP_DITO_MASK 0x01FF8000\r | |
| 189 | #define AHCI_PORT_DEVSLP_DM_MASK 0x1E000000\r | |
| a41b5272 | 190 | \r |
| 191 | #pragma pack(1)\r | |
| 192 | //\r | |
| 193 | // Command List structure includes total 32 entries.\r | |
| 194 | // The entry data structure is listed at the following.\r | |
| 195 | //\r | |
| 196 | typedef struct {\r | |
| 197 | UINT32 AhciCmdCfl:5; //Command FIS Length\r | |
| 198 | UINT32 AhciCmdA:1; //ATAPI\r | |
| 199 | UINT32 AhciCmdW:1; //Write\r | |
| 200 | UINT32 AhciCmdP:1; //Prefetchable\r | |
| 201 | UINT32 AhciCmdR:1; //Reset\r | |
| 202 | UINT32 AhciCmdB:1; //BIST\r | |
| 203 | UINT32 AhciCmdC:1; //Clear Busy upon R_OK\r | |
| 204 | UINT32 AhciCmdRsvd:1;\r | |
| 205 | UINT32 AhciCmdPmp:4; //Port Multiplier Port\r | |
| 206 | UINT32 AhciCmdPrdtl:16; //Physical Region Descriptor Table Length\r | |
| 207 | UINT32 AhciCmdPrdbc; //Physical Region Descriptor Byte Count\r | |
| 208 | UINT32 AhciCmdCtba; //Command Table Descriptor Base Address\r | |
| 209 | UINT32 AhciCmdCtbau; //Command Table Descriptor Base Address Upper 32-BITs\r | |
| d1102dba | 210 | UINT32 AhciCmdRsvd1[4];\r |
| a41b5272 | 211 | } EFI_AHCI_COMMAND_LIST;\r |
| 212 | \r | |
| 213 | //\r | |
| 214 | // This is a software constructed FIS.\r | |
| d1102dba | 215 | // For data transfer operations, this is the H2D Register FIS format as\r |
| a41b5272 | 216 | // specified in the Serial ATA Revision 2.6 specification.\r |
| 217 | //\r | |
| 218 | typedef struct {\r | |
| 219 | UINT8 AhciCFisType;\r | |
| 220 | UINT8 AhciCFisPmNum:4;\r | |
| 221 | UINT8 AhciCFisRsvd:1;\r | |
| 222 | UINT8 AhciCFisRsvd1:1;\r | |
| 223 | UINT8 AhciCFisRsvd2:1;\r | |
| 224 | UINT8 AhciCFisCmdInd:1;\r | |
| 225 | UINT8 AhciCFisCmd;\r | |
| 226 | UINT8 AhciCFisFeature;\r | |
| 227 | UINT8 AhciCFisSecNum;\r | |
| 228 | UINT8 AhciCFisClyLow;\r | |
| 229 | UINT8 AhciCFisClyHigh;\r | |
| 230 | UINT8 AhciCFisDevHead;\r | |
| 231 | UINT8 AhciCFisSecNumExp;\r | |
| 232 | UINT8 AhciCFisClyLowExp;\r | |
| 233 | UINT8 AhciCFisClyHighExp;\r | |
| 234 | UINT8 AhciCFisFeatureExp;\r | |
| 235 | UINT8 AhciCFisSecCount;\r | |
| 236 | UINT8 AhciCFisSecCountExp;\r | |
| 237 | UINT8 AhciCFisRsvd3;\r | |
| 238 | UINT8 AhciCFisControl;\r | |
| 239 | UINT8 AhciCFisRsvd4[4];\r | |
| 240 | UINT8 AhciCFisRsvd5[44];\r | |
| 241 | } EFI_AHCI_COMMAND_FIS;\r | |
| 242 | \r | |
| 243 | //\r | |
| 244 | // ACMD: ATAPI command (12 or 16 bytes)\r | |
| 245 | //\r | |
| 246 | typedef struct {\r | |
| 247 | UINT8 AtapiCmd[0x10];\r | |
| 248 | } EFI_AHCI_ATAPI_COMMAND;\r | |
| 249 | \r | |
| 250 | //\r | |
| 251 | // Physical Region Descriptor Table includes up to 65535 entries\r | |
| 252 | // The entry data structure is listed at the following.\r | |
| 253 | // the actual entry number comes from the PRDTL field in the command\r | |
| d1102dba | 254 | // list entry for this command slot.\r |
| a41b5272 | 255 | //\r |
| 256 | typedef struct {\r | |
| 257 | UINT32 AhciPrdtDba; //Data Base Address\r | |
| 258 | UINT32 AhciPrdtDbau; //Data Base Address Upper 32-BITs\r | |
| 259 | UINT32 AhciPrdtRsvd;\r | |
| 260 | UINT32 AhciPrdtDbc:22; //Data Byte Count\r | |
| 261 | UINT32 AhciPrdtRsvd1:9;\r | |
| 262 | UINT32 AhciPrdtIoc:1; //Interrupt on Completion\r | |
| 263 | } EFI_AHCI_COMMAND_PRDT;\r | |
| 264 | \r | |
| 265 | //\r | |
| 266 | // Command table data strucute which is pointed to by the entry in the command list\r | |
| 267 | //\r | |
| 268 | typedef struct {\r | |
| 269 | EFI_AHCI_COMMAND_FIS CommandFis; // A software constructed FIS.\r | |
| 270 | EFI_AHCI_ATAPI_COMMAND AtapiCmd; // 12 or 16 bytes ATAPI cmd.\r | |
| 271 | UINT8 Reserved[0x30];\r | |
| 272 | EFI_AHCI_COMMAND_PRDT PrdtTable[65535]; // The scatter/gather list for data transfer\r | |
| 273 | } EFI_AHCI_COMMAND_TABLE;\r | |
| 274 | \r | |
| 275 | //\r | |
| 276 | // Received FIS structure\r | |
| 277 | //\r | |
| 278 | typedef struct {\r | |
| 279 | UINT8 AhciDmaSetupFis[0x1C]; // Dma Setup Fis: offset 0x00\r | |
| 280 | UINT8 AhciDmaSetupFisRsvd[0x04];\r | |
| 281 | UINT8 AhciPioSetupFis[0x14]; // Pio Setup Fis: offset 0x20\r | |
| d1102dba | 282 | UINT8 AhciPioSetupFisRsvd[0x0C];\r |
| a41b5272 | 283 | UINT8 AhciD2HRegisterFis[0x14]; // D2H Register Fis: offset 0x40\r |
| 284 | UINT8 AhciD2HRegisterFisRsvd[0x04];\r | |
| 285 | UINT64 AhciSetDeviceBitsFis; // Set Device Bits Fix: offset 0x58\r | |
| 286 | UINT8 AhciUnknownFis[0x40]; // Unkonwn Fis: offset 0x60\r | |
| d1102dba LG |
287 | UINT8 AhciUnknownFisRsvd[0x60];\r |
| 288 | } EFI_AHCI_RECEIVED_FIS;\r | |
| a41b5272 | 289 | \r |
| f3100a1a RN |
290 | typedef struct {\r |
| 291 | UINT8 Madt : 5;\r | |
| 292 | UINT8 Reserved_5 : 3;\r | |
| 293 | UINT8 Deto;\r | |
| 294 | UINT16 Reserved_16;\r | |
| 295 | UINT32 Reserved_32 : 31;\r | |
| 296 | UINT32 Supported : 1;\r | |
| 297 | } DEVSLP_TIMING_VARIABLES;\r | |
| 298 | \r | |
| a41b5272 | 299 | #pragma pack()\r |
| 300 | \r | |
| 301 | typedef struct {\r | |
| 302 | EFI_AHCI_RECEIVED_FIS *AhciRFis;\r | |
| 303 | EFI_AHCI_COMMAND_LIST *AhciCmdList;\r | |
| 304 | EFI_AHCI_COMMAND_TABLE *AhciCommandTable;\r | |
| 305 | EFI_AHCI_RECEIVED_FIS *AhciRFisPciAddr;\r | |
| 306 | EFI_AHCI_COMMAND_LIST *AhciCmdListPciAddr;\r | |
| 307 | EFI_AHCI_COMMAND_TABLE *AhciCommandTablePciAddr;\r | |
| 308 | UINT64 MaxCommandListSize;\r | |
| 309 | UINT64 MaxCommandTableSize;\r | |
| 310 | UINT64 MaxReceiveFisSize;\r | |
| 311 | VOID *MapRFis;\r | |
| 312 | VOID *MapCmdList;\r | |
| 313 | VOID *MapCommandTable;\r | |
| 314 | } EFI_AHCI_REGISTERS;\r | |
| 315 | \r | |
| 316 | /**\r | |
| d1102dba | 317 | This function is used to send out ATAPI commands conforms to the Packet Command\r |
| a41b5272 | 318 | with PIO Protocol.\r |
| 319 | \r | |
| 320 | @param PciIo The PCI IO protocol instance.\r | |
| 321 | @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r | |
| d1102dba | 322 | @param Port The number of port.\r |
| a41b5272 | 323 | @param PortMultiplier The number of port multiplier.\r |
| 324 | @param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.\r | |
| 325 | \r | |
| 326 | @retval EFI_SUCCESS send out the ATAPI packet command successfully\r | |
| 327 | and device sends data successfully.\r | |
| 328 | @retval EFI_DEVICE_ERROR the device failed to send data.\r | |
| 329 | \r | |
| 330 | **/\r | |
| 331 | EFI_STATUS\r | |
| 332 | EFIAPI\r | |
| 333 | AhciPacketCommandExecute (\r | |
| 334 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 335 | IN EFI_AHCI_REGISTERS *AhciRegisters,\r | |
| 336 | IN UINT8 Port,\r | |
| 337 | IN UINT8 PortMultiplier,\r | |
| 338 | IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet\r | |
| 339 | );\r | |
| 340 | \r | |
| 341 | /**\r | |
| 342 | Start command for give slot on specific port.\r | |
| d1102dba | 343 | \r |
| a41b5272 | 344 | @param PciIo The PCI IO protocol instance.\r |
| 345 | @param Port The number of port.\r | |
| 346 | @param CommandSlot The number of CommandSlot.\r | |
| 8536cc4b | 347 | @param Timeout The timeout value of start, uses 100ns as a unit.\r |
| d1102dba | 348 | \r |
| a41b5272 | 349 | @retval EFI_DEVICE_ERROR The command start unsuccessfully.\r |
| 350 | @retval EFI_TIMEOUT The operation is time out.\r | |
| 351 | @retval EFI_SUCCESS The command start successfully.\r | |
| 352 | \r | |
| 353 | **/\r | |
| 354 | EFI_STATUS\r | |
| 355 | EFIAPI\r | |
| 356 | AhciStartCommand (\r | |
| 357 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 358 | IN UINT8 Port,\r | |
| 359 | IN UINT8 CommandSlot,\r | |
| 360 | IN UINT64 Timeout\r | |
| 361 | );\r | |
| 362 | \r | |
| 363 | /**\r | |
| 364 | Stop command running for giving port\r | |
| d1102dba | 365 | \r |
| a41b5272 | 366 | @param PciIo The PCI IO protocol instance.\r |
| 367 | @param Port The number of port.\r | |
| 8536cc4b | 368 | @param Timeout The timeout value of stop, uses 100ns as a unit.\r |
| d1102dba | 369 | \r |
| a41b5272 | 370 | @retval EFI_DEVICE_ERROR The command stop unsuccessfully.\r |
| 371 | @retval EFI_TIMEOUT The operation is time out.\r | |
| 372 | @retval EFI_SUCCESS The command stop successfully.\r | |
| 373 | \r | |
| 374 | **/\r | |
| 375 | EFI_STATUS\r | |
| 376 | EFIAPI\r | |
| 377 | AhciStopCommand (\r | |
| 378 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 379 | IN UINT8 Port,\r | |
| 380 | IN UINT64 Timeout\r | |
| 381 | );\r | |
| 382 | \r | |
| a41b5272 | 383 | #endif\r |
| 384 | \r |