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1 | /** @file\r |
2 | Header file for IDE mode of ATA host controller.\r |
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3 | \r |
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4 | Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r |
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5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
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6 | \r |
7 | **/\r |
8 | #ifndef __ATA_HC_IDE_MODE_H__\r |
9 | #define __ATA_HC_IDE_MODE_H__\r |
10 | \r |
11 | typedef enum {\r |
12 | EfiIdePrimary = 0,\r |
13 | EfiIdeSecondary = 1,\r |
14 | EfiIdeMaxChannel = 2\r |
15 | } EFI_IDE_CHANNEL;\r |
16 | \r |
17 | typedef enum {\r |
18 | EfiIdeMaster = 0,\r |
19 | EfiIdeSlave = 1,\r |
20 | EfiIdeMaxDevice = 2\r |
21 | } EFI_IDE_DEVICE;\r |
22 | \r |
23 | ///\r |
24 | /// PIO mode definition\r |
25 | ///\r |
26 | typedef enum {\r |
27 | EfiAtaPioModeBelow2,\r |
28 | EfiAtaPioMode2,\r |
29 | EfiAtaPioMode3,\r |
30 | EfiAtaPioMode4\r |
31 | } EFI_ATA_PIO_MODE;\r |
32 | \r |
33 | //\r |
34 | // Multi word DMA definition\r |
35 | //\r |
36 | typedef enum {\r |
37 | EfiAtaMdmaMode0,\r |
38 | EfiAtaMdmaMode1,\r |
39 | EfiAtaMdmaMode2\r |
40 | } EFI_ATA_MDMA_MODE;\r |
41 | \r |
42 | //\r |
43 | // UDMA mode definition\r |
44 | //\r |
45 | typedef enum {\r |
46 | EfiAtaUdmaMode0,\r |
47 | EfiAtaUdmaMode1,\r |
48 | EfiAtaUdmaMode2,\r |
49 | EfiAtaUdmaMode3,\r |
50 | EfiAtaUdmaMode4,\r |
51 | EfiAtaUdmaMode5\r |
52 | } EFI_ATA_UDMA_MODE;\r |
53 | \r |
54 | //\r |
55 | // Bus Master Reg\r |
56 | //\r |
57 | #define BMIC_NREAD BIT3\r |
58 | #define BMIC_START BIT0\r |
59 | #define BMIS_INTERRUPT BIT2\r |
60 | #define BMIS_ERROR BIT1\r |
61 | \r |
62 | #define BMIC_OFFSET 0x00\r |
63 | #define BMIS_OFFSET 0x02\r |
64 | #define BMID_OFFSET 0x04\r |
65 | \r |
66 | //\r |
67 | // IDE transfer mode\r |
68 | //\r |
69 | #define EFI_ATA_MODE_DEFAULT_PIO 0x00\r |
70 | #define EFI_ATA_MODE_FLOW_PIO 0x01\r |
71 | #define EFI_ATA_MODE_MDMA 0x04\r |
72 | #define EFI_ATA_MODE_UDMA 0x08\r |
73 | \r |
74 | typedef struct {\r |
75 | UINT32 RegionBaseAddr;\r |
76 | UINT16 ByteCount;\r |
77 | UINT16 EndOfTable;\r |
78 | } EFI_ATA_DMA_PRD;\r |
79 | \r |
80 | typedef struct {\r |
81 | UINT8 ModeNumber : 3;\r |
82 | UINT8 ModeCategory : 5;\r |
83 | } EFI_ATA_TRANSFER_MODE;\r |
84 | \r |
85 | typedef struct {\r |
86 | UINT8 Sector;\r |
87 | UINT8 Heads;\r |
88 | UINT8 MultipleSector;\r |
89 | } EFI_ATA_DRIVE_PARMS;\r |
90 | \r |
91 | //\r |
92 | // IDE registers set\r |
93 | //\r |
94 | typedef struct {\r |
95 | UINT16 Data;\r |
96 | UINT16 ErrOrFeature;\r |
97 | UINT16 SectorCount;\r |
98 | UINT16 SectorNumber;\r |
99 | UINT16 CylinderLsb;\r |
100 | UINT16 CylinderMsb;\r |
101 | UINT16 Head;\r |
102 | UINT16 CmdOrStatus;\r |
103 | UINT16 AltOrDev;\r |
104 | \r |
105 | UINT16 BusMasterBaseAddr;\r |
106 | } EFI_IDE_REGISTERS;\r |
107 | \r |
108 | //\r |
109 | // Bit definitions in Programming Interface byte of the Class Code field\r |
110 | // in PCI IDE controller's Configuration Space\r |
111 | //\r |
112 | #define IDE_PRIMARY_OPERATING_MODE BIT0\r |
113 | #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1\r |
114 | #define IDE_SECONDARY_OPERATING_MODE BIT2\r |
115 | #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR BIT3\r |
116 | \r |
117 | /**\r |
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118 | Get IDE i/o port registers' base addresses by mode.\r |
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119 | \r |
120 | In 'Compatibility' mode, use fixed addresses.\r |
121 | In Native-PCI mode, get base addresses from BARs in the PCI IDE controller's\r |
122 | Configuration Space.\r |
123 | \r |
124 | The steps to get IDE i/o port registers' base addresses for each channel\r |
125 | as follows:\r |
126 | \r |
127 | 1. Examine the Programming Interface byte of the Class Code fields in PCI IDE\r |
128 | controller's Configuration Space to determine the operating mode.\r |
129 | \r |
130 | 2. a) In 'Compatibility' mode, use fixed addresses shown in the Table 1 below.\r |
131 | ___________________________________________\r |
132 | | | Command Block | Control Block |\r |
133 | | Channel | Registers | Registers |\r |
134 | |___________|_______________|_______________|\r |
135 | | Primary | 1F0h - 1F7h | 3F6h - 3F7h |\r |
136 | |___________|_______________|_______________|\r |
137 | | Secondary | 170h - 177h | 376h - 377h |\r |
138 | |___________|_______________|_______________|\r |
139 | \r |
140 | Table 1. Compatibility resource mappings\r |
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141 | \r |
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142 | b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs\r |
143 | in IDE controller's PCI Configuration Space, shown in the Table 2 below.\r |
144 | ___________________________________________________\r |
145 | | | Command Block | Control Block |\r |
146 | | Channel | Registers | Registers |\r |
147 | |___________|___________________|___________________|\r |
148 | | Primary | BAR at offset 0x10| BAR at offset 0x14|\r |
149 | |___________|___________________|___________________|\r |
150 | | Secondary | BAR at offset 0x18| BAR at offset 0x1C|\r |
151 | |___________|___________________|___________________|\r |
152 | \r |
153 | Table 2. BARs for Register Mapping\r |
154 | \r |
155 | @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance\r |
156 | @param[in, out] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to\r |
157 | store the IDE i/o port registers' base addresses\r |
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158 | \r |
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159 | @retval EFI_UNSUPPORTED Return this value when the BARs is not IO type\r |
160 | @retval EFI_SUCCESS Get the Base address successfully\r |
161 | @retval Other Read the pci configureation data error\r |
162 | \r |
163 | **/\r |
164 | EFI_STATUS\r |
165 | EFIAPI\r |
166 | GetIdeRegisterIoAddr (\r |
167 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
168 | IN OUT EFI_IDE_REGISTERS *IdeRegisters\r |
169 | );\r |
170 | \r |
171 | /**\r |
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172 | This function is used to send out ATAPI commands conforms to the Packet Command\r |
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173 | with PIO Data In Protocol.\r |
174 | \r |
175 | @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance\r |
176 | @param[in] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to\r |
177 | store the IDE i/o port registers' base addresses\r |
178 | @param[in] Channel The channel number of device.\r |
179 | @param[in] Device The device number of device.\r |
180 | @param[in] Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET data structure.\r |
181 | \r |
182 | @retval EFI_SUCCESS send out the ATAPI packet command successfully\r |
183 | and device sends data successfully.\r |
184 | @retval EFI_DEVICE_ERROR the device failed to send data.\r |
185 | \r |
186 | **/\r |
187 | EFI_STATUS\r |
188 | EFIAPI\r |
189 | AtaPacketCommandExecute (\r |
190 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
191 | IN EFI_IDE_REGISTERS *IdeRegisters,\r |
192 | IN UINT8 Channel,\r |
193 | IN UINT8 Device,\r |
194 | IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet\r |
195 | );\r |
196 | \r |
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197 | #endif\r |
198 | \r |