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913cb9dc 1/** @file\r
2\r
78c2ffb5 3 Provides some data struct used by EHCI controller driver.\r
4\r
d1102dba 5Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
e33d3e7f 6Copyright (c) Microsoft Corporation.<BR>\r
9d510e61 7SPDX-License-Identifier: BSD-2-Clause-Patent\r
913cb9dc 8\r
913cb9dc 9**/\r
10\r
11#ifndef _EFI_EHCI_H_\r
12#define _EFI_EHCI_H_\r
13\r
60c93673 14#include <Uefi.h>\r
ed7748fe 15\r
913cb9dc 16#include <Protocol/Usb2HostController.h>\r
17#include <Protocol/PciIo.h>\r
ed7748fe 18\r
0428a6cb 19#include <Guid/EventGroup.h>\r
20\r
913cb9dc 21#include <Library/DebugLib.h>\r
22#include <Library/BaseMemoryLib.h>\r
23#include <Library/UefiDriverEntryPoint.h>\r
24#include <Library/UefiBootServicesTableLib.h>\r
25#include <Library/UefiLib.h>\r
26#include <Library/BaseLib.h>\r
27#include <Library/MemoryAllocationLib.h>\r
dd4047a5 28#include <Library/PcdLib.h>\r
37623a5c 29#include <Library/ReportStatusCodeLib.h>\r
913cb9dc 30\r
a261044c 31#include <IndustryStandard/Pci.h>\r
913cb9dc 32\r
1436aea4 33typedef struct _USB2_HC_DEV USB2_HC_DEV;\r
913cb9dc 34\r
35#include "UsbHcMem.h"\r
36#include "EhciReg.h"\r
37#include "EhciUrb.h"\r
38#include "EhciSched.h"\r
39#include "EhciDebug.h"\r
aa79b0b3 40#include "ComponentName.h"\r
913cb9dc 41\r
1ccdbf2a 42//\r
43// EHC timeout experience values\r
44//\r
45\r
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46#define EHC_1_MICROSECOND 1\r
47#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)\r
48#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)\r
1ccdbf2a 49\r
50//\r
51// EHCI register operation timeout, set by experience\r
52//\r
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53#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)\r
54#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)\r
78c2ffb5 55\r
1ccdbf2a 56//\r
57// Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]\r
58//\r
1436aea4 59#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)\r
1ccdbf2a 60\r
61//\r
62// Sync and Async transfer polling interval, set by experience,\r
d525ec10 63// and the unit of Async is 100us, means 1ms as interval.\r
1ccdbf2a 64//\r
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65#define EHC_SYNC_POLL_INTERVAL (1 * EHC_1_MILLISECOND)\r
66#define EHC_ASYNC_POLL_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)\r
41e8ff27 67\r
09943f5e 68//\r
69// EHCI debug port control status register bit definition\r
70//\r
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71#define USB_DEBUG_PORT_IN_USE BIT10\r
72#define USB_DEBUG_PORT_ENABLE BIT28\r
73#define USB_DEBUG_PORT_OWNER BIT30\r
74#define USB_DEBUG_PORT_IN_USE_MASK (USB_DEBUG_PORT_IN_USE | \\r
b48ec0e8 75 USB_DEBUG_PORT_OWNER)\r
09943f5e 76\r
597f4ee2 77//\r
78// EHC raises TPL to TPL_NOTIFY to serialize all its operations\r
79// to protect shared data structures.\r
80//\r
1436aea4 81#define EHC_TPL TPL_NOTIFY\r
913cb9dc 82\r
1436aea4 83#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)\r
913cb9dc 84\r
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85#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r
86#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r
87#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
913cb9dc 88\r
89#define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \\r
90 (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))\r
91\r
597f4ee2 92#define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i')\r
1436aea4 93#define EHC_FROM_THIS(a) CR(a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)\r
913cb9dc 94\r
c52fa98c 95struct _USB2_HC_DEV {\r
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96 UINTN Signature;\r
97 EFI_USB2_HC_PROTOCOL Usb2Hc;\r
913cb9dc 98\r
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99 EFI_PCI_IO_PROTOCOL *PciIo;\r
100 EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
101 UINT64 OriginalPciAttributes;\r
102 USBHC_MEM_POOL *MemPool;\r
913cb9dc 103\r
104 //\r
105 // Schedule data shared between asynchronous and periodic\r
106 // transfers:\r
107 // ShortReadStop, as its name indicates, is used to terminate\r
108 // the short read except the control transfer. EHCI follows\r
109 // the alternative next QTD point when a short read happens.\r
110 // For control transfer, even the short read happens, try the\r
111 // status stage.\r
112 //\r
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113 EHC_QTD *ShortReadStop;\r
114 EFI_EVENT PollTimer;\r
913cb9dc 115\r
0428a6cb 116 //\r
d1102dba 117 // ExitBootServicesEvent is used to stop the EHC DMA operation\r
0428a6cb 118 // after exit boot service.\r
119 //\r
1436aea4 120 EFI_EVENT ExitBootServiceEvent;\r
0428a6cb 121\r
913cb9dc 122 //\r
123 // Asynchronous(bulk and control) transfer schedule data:\r
124 // ReclaimHead is used as the head of the asynchronous transfer\r
125 // list. It acts as the reclamation header.\r
126 //\r
1436aea4 127 EHC_QH *ReclaimHead;\r
913cb9dc 128\r
129 //\r
ed356b9e 130 // Periodic (interrupt) transfer schedule data:\r
913cb9dc 131 //\r
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132 VOID *PeriodFrame; // the buffer pointed by this pointer is used to store pci bus address of the QH descriptor.\r
133 VOID *PeriodFrameHost; // the buffer pointed by this pointer is used to store host memory address of the QH descriptor.\r
134 VOID *PeriodFrameMap;\r
913cb9dc 135\r
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136 EHC_QH *PeriodOne;\r
137 LIST_ENTRY AsyncIntTransfers;\r
913cb9dc 138\r
139 //\r
140 // EHCI configuration data\r
141 //\r
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142 UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET\r
143 UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS\r
144 UINT32 CapLen; // Capability length\r
913cb9dc 145\r
146 //\r
147 // Misc\r
148 //\r
1436aea4 149 EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r
09943f5e 150\r
151 //\r
152 // EHCI debug port info\r
153 //\r
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154 UINT16 DebugPortOffset; // The offset of debug port mmio register\r
155 UINT8 DebugPortBarNum; // The bar number of debug port mmio register\r
156 UINT8 DebugPortNum; // The port number of usb debug port\r
167c3fb4 157\r
1436aea4 158 BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device\r
c52fa98c 159};\r
913cb9dc 160\r
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161extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;\r
162extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;\r
163extern EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2;\r
913cb9dc 164\r
aa79b0b3 165/**\r
166 Test to see if this driver supports ControllerHandle. Any\r
167 ControllerHandle that has Usb2HcProtocol installed will\r
168 be supported.\r
169\r
170 @param This Protocol instance pointer.\r
171 @param Controller Handle of device to test.\r
172 @param RemainingDevicePath Not used.\r
173\r
174 @return EFI_SUCCESS This driver supports this device.\r
175 @return EFI_UNSUPPORTED This driver does not support this device.\r
176\r
177**/\r
178EFI_STATUS\r
179EFIAPI\r
180EhcDriverBindingSupported (\r
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181 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
182 IN EFI_HANDLE Controller,\r
183 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
aa79b0b3 184 );\r
185\r
186/**\r
187 Starting the Usb EHCI Driver.\r
188\r
189 @param This Protocol instance pointer.\r
190 @param Controller Handle of device to test.\r
191 @param RemainingDevicePath Not used.\r
192\r
193 @return EFI_SUCCESS supports this device.\r
194 @return EFI_UNSUPPORTED do not support this device.\r
195 @return EFI_DEVICE_ERROR cannot be started due to device Error.\r
196 @return EFI_OUT_OF_RESOURCES cannot allocate resources.\r
197\r
198**/\r
199EFI_STATUS\r
200EFIAPI\r
201EhcDriverBindingStart (\r
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202 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
203 IN EFI_HANDLE Controller,\r
204 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
aa79b0b3 205 );\r
206\r
207/**\r
ed356b9e 208 Stop this driver on ControllerHandle. Support stopping any child handles\r
aa79b0b3 209 created by this driver.\r
210\r
211 @param This Protocol instance pointer.\r
212 @param Controller Handle of device to stop driver on.\r
213 @param NumberOfChildren Number of Children in the ChildHandleBuffer.\r
214 @param ChildHandleBuffer List of handles for the children we need to stop.\r
215\r
216 @return EFI_SUCCESS Success.\r
217 @return EFI_DEVICE_ERROR Fail.\r
218\r
219**/\r
220EFI_STATUS\r
221EFIAPI\r
222EhcDriverBindingStop (\r
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223 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
224 IN EFI_HANDLE Controller,\r
225 IN UINTN NumberOfChildren,\r
226 IN EFI_HANDLE *ChildHandleBuffer\r
aa79b0b3 227 );\r
228\r
913cb9dc 229#endif\r