[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / EhciReg.h

/** @file\r
\r
  This file contains the definination for host controller register operation routines.\r
\r
Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _EFI_EHCI_REG_H_\r
#define _EFI_EHCI_REG_H_\r
\r
//\r
// EHCI register offset\r
//\r
\r
\r
//\r
// Capability register offset\r
//\r
#define EHC_CAPLENGTH_OFFSET    0    // Capability register length offset\r
#define EHC_HCSPARAMS_OFFSET    0x04 // Structural Parameters 04-07h\r
#define EHC_HCCPARAMS_OFFSET    0x08 // Capability parameters offset\r
\r
//\r
// Capability register bit definition\r
//\r
#define HCSP_NPORTS             0x0F // Number of root hub port\r
#define HCCP_64BIT              0x01 // 64-bit addressing capability\r
\r
//\r
// Operational register offset\r
//\r
#define EHC_USBCMD_OFFSET       0x0  // USB command register offset\r
#define EHC_USBSTS_OFFSET       0x04 // Statue register offset\r
#define EHC_USBINTR_OFFSET      0x08 // USB interrutp offset\r
#define EHC_FRINDEX_OFFSET      0x0C // Frame index offset\r
#define EHC_CTRLDSSEG_OFFSET    0x10 // Control data structure segment offset\r
#define EHC_FRAME_BASE_OFFSET   0x14 // Frame list base address offset\r
#define EHC_ASYNC_HEAD_OFFSET   0x18 // Next asynchronous list address offset\r
#define EHC_CONFIG_FLAG_OFFSET  0x40 // Configure flag register offset\r
#define EHC_PORT_STAT_OFFSET    0x44 // Port status/control offset\r
\r
#define EHC_FRAME_LEN           1024\r
\r
//\r
// Register bit definition\r
//\r
#define CONFIGFLAG_ROUTE_EHC    0x01 // Route port to EHC\r
\r
#define USBCMD_RUN              0x01   // Run/stop\r
#define USBCMD_RESET            0x02   // Start the host controller reset\r
#define USBCMD_ENABLE_PERIOD    0x10   // Enable periodic schedule\r
#define USBCMD_ENABLE_ASYNC     0x20   // Enable asynchronous schedule\r
#define USBCMD_IAAD             0x40   // Interrupt on async advance doorbell\r
\r
#define USBSTS_IAA              0x20   // Interrupt on async advance\r
#define USBSTS_PERIOD_ENABLED   0x4000 // Periodic schedule status\r
#define USBSTS_ASYNC_ENABLED    0x8000 // Asynchronous schedule status\r
#define USBSTS_HALT             0x1000 // Host controller halted\r
#define USBSTS_SYS_ERROR        0x10   // Host system error\r
#define USBSTS_INTACK_MASK      0x003F // Mask for the interrupt ACK, the WC\r
                                       // (write clean) bits in USBSTS register\r
\r
#define PORTSC_CONN             0x01   // Current Connect Status\r
#define PORTSC_CONN_CHANGE      0x02   // Connect Status Change\r
#define PORTSC_ENABLED          0x04   // Port Enable / Disable\r
#define PORTSC_ENABLE_CHANGE    0x08   // Port Enable / Disable Change\r
#define PORTSC_OVERCUR          0x10   // Over current Active\r
#define PORTSC_OVERCUR_CHANGE   0x20   // Over current Change\r
#define PORSTSC_RESUME          0x40   // Force Port Resume\r
#define PORTSC_SUSPEND          0x80   // Port Suspend State\r
#define PORTSC_RESET            0x100  // Port Reset\r
#define PORTSC_LINESTATE_K      0x400  // Line Status K-state\r
#define PORTSC_LINESTATE_J      0x800  // Line Status J-state\r
#define PORTSC_POWER            0x1000 // Port Power\r
#define PORTSC_OWNER            0x2000 // Port Owner\r
#define PORTSC_CHANGE_MASK      0x2A   // Mask of the port change bits,\r
                                       // they are WC (write clean)\r
//\r
// PCI Configuration Registers\r
//\r
#define EHC_BAR_INDEX           0      // how many bytes away from USB_BASE to 0x10\r
\r
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
\r
#define EHC_ADDR(High, QhHw32)   \\r
        ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))\r
\r
#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
//\r
typedef struct {\r
  UINT16                  HwState;\r
  UINT16                  UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
//\r
// Ehci Data and Ctrl Structures\r
//\r
#pragma pack(1)\r
typedef struct {\r
  UINT8                   ProgInterface;\r
  UINT8                   SubClassCode;\r
  UINT8                   BaseCode;\r
} USB_CLASSC;\r
#pragma pack()\r
\r
/**\r
  Read EHCI capability register.\r
\r
  @param  Ehc     The EHCI device.\r
  @param  Offset  Capability register address.\r
\r
  @return The register content.\r
\r
**/\r
UINT32\r
EhcReadCapRegister (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32              Offset\r
  );\r
\r
\r
/**\r
  Read EHCI Operation register.\r
\r
  @param  Ehc      The EHCI device.\r
  @param  Offset   The operation register offset.\r
\r
  @return The register content.\r
\r
**/\r
UINT32\r
EhcReadOpReg (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32              Offset\r
  );\r
\r
\r
/**\r
  Write  the data to the EHCI operation register.\r
\r
  @param  Ehc      The EHCI device.\r
  @param  Offset   EHCI operation register offset.\r
  @param  Data     The data to write.\r
\r
**/\r
VOID\r
EhcWriteOpReg (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
EhcSetOpRegBit (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to clear.\r
\r
**/\r
VOID\r
EhcClearOpRegBit (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Add support for UEFI Over Legacy (UoL) feature, stop\r
  the legacy USB SMI support.\r
\r
  @param  Ehc      The EHCI device.\r
\r
**/\r
VOID\r
EhcClearLegacySupport (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
\r
/**\r
  Set door bell and wait it to be ACKed by host controller.\r
  This function is used to synchronize with the hardware.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  Synchronized with the hardware.\r
  @retval EFI_TIMEOUT  Time out happened while waiting door bell to set.\r
\r
**/\r
EFI_STATUS\r
EhcSetAndWaitDoorBell (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32               Timeout\r
  );\r
\r
\r
/**\r
  Clear all the interrutp status bits, these bits are Write-Clean.\r
\r
  @param  Ehc      The EHCI device.\r
\r
**/\r
VOID\r
EhcAckAllInterrupt (\r
  IN  USB2_HC_DEV         *Ehc\r
  );\r
\r
\r
\r
/**\r
  Whether Ehc is halted.\r
\r
  @param  Ehc     The EHCI device.\r
\r
  @retval TRUE    The controller is halted.\r
  @retval FALSE   It isn't halted.\r
\r
**/\r
BOOLEAN\r
EhcIsHalt (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
/**\r
  Whether system error occurred.\r
\r
  @param  Ehc      The EHCI device.\r
\r
  @retval TRUE     System error happened.\r
  @retval FALSE    No system error.\r
\r
**/\r
BOOLEAN\r
EhcIsSysError (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
/**\r
  Reset the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The host controller is reset.\r
  @return Others       Failed to reset the host.\r
\r
**/\r
EFI_STATUS\r
EhcResetHC (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  );\r
\r
\r
/**\r
  Halt the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @return EFI_SUCCESS  The EHCI is halt.\r
  @return EFI_TIMEOUT  Failed to halt the controller before Timeout.\r
\r
**/\r
EFI_STATUS\r
EhcHaltHC (\r
  IN USB2_HC_DEV         *Ehc,\r
  IN UINT32              Timeout\r
  );\r
\r
\r
/**\r
  Set the EHCI to run.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @return EFI_SUCCESS  The EHCI is running.\r
  @return Others       Failed to set the EHCI to run.\r
\r
**/\r
EFI_STATUS\r
EhcRunHC (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  );\r
\r
\r
\r
/**\r
  Initialize the HC hardware.\r
  EHCI spec lists the five things to do to initialize the hardware:\r
  1. Program CTRLDSSEGMENT\r
  2. Set USBINTR to enable interrupts\r
  3. Set periodic list base\r
  4. Set USBCMD, interrupt threshold, frame list size etc\r
  5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
\r
  @param  Ehc          The EHCI device.\r
\r
  @return EFI_SUCCESS  The EHCI has come out of halt state.\r
  @return EFI_TIMEOUT  Time out happened.\r
\r
**/\r
EFI_STATUS\r
EhcInitHC (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
#endif\r
Commit	Line	Data
913cb9dc	1	/** @file\r
913cb9dc	2	\r
78c2ffb5	3	This file contains the definination for host controller register operation routines.\r
78c2ffb5	4	\r
1ccdbf2a	5	Copyright (c) 2007 - 2010, Intel Corporation\r
913cb9dc	6	All rights reserved. This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
913cb9dc	14	**/\r
	15	\r
	16	#ifndef _EFI_EHCI_REG_H_\r
	17	#define _EFI_EHCI_REG_H_\r
	18	\r
1ccdbf2a	19	//\r
	20	// EHCI register offset\r
	21	//\r
	22	\r
	23	\r
	24	//\r
	25	// Capability register offset\r
	26	//\r
	27	#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset\r
	28	#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h\r
	29	#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset\r
	30	\r
	31	//\r
	32	// Capability register bit definition\r
	33	//\r
	34	#define HCSP_NPORTS 0x0F // Number of root hub port\r
	35	#define HCCP_64BIT 0x01 // 64-bit addressing capability\r
	36	\r
	37	//\r
	38	// Operational register offset\r
	39	//\r
	40	#define EHC_USBCMD_OFFSET 0x0 // USB command register offset\r
	41	#define EHC_USBSTS_OFFSET 0x04 // Statue register offset\r
	42	#define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset\r
	43	#define EHC_FRINDEX_OFFSET 0x0C // Frame index offset\r
	44	#define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset\r
	45	#define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset\r
	46	#define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset\r
	47	#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset\r
	48	#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset\r
	49	\r
	50	#define EHC_FRAME_LEN 1024\r
913cb9dc	51	\r
1ccdbf2a	52	//\r
	53	// Register bit definition\r
	54	//\r
	55	#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC\r
	56	\r
	57	#define USBCMD_RUN 0x01 // Run/stop\r
	58	#define USBCMD_RESET 0x02 // Start the host controller reset\r
	59	#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule\r
	60	#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule\r
	61	#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell\r
	62	\r
	63	#define USBSTS_IAA 0x20 // Interrupt on async advance\r
	64	#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status\r
	65	#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status\r
	66	#define USBSTS_HALT 0x1000 // Host controller halted\r
	67	#define USBSTS_SYS_ERROR 0x10 // Host system error\r
	68	#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC\r
	69	// (write clean) bits in USBSTS register\r
	70	\r
	71	#define PORTSC_CONN 0x01 // Current Connect Status\r
	72	#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change\r
	73	#define PORTSC_ENABLED 0x04 // Port Enable / Disable\r
	74	#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change\r
	75	#define PORTSC_OVERCUR 0x10 // Over current Active\r
	76	#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change\r
	77	#define PORSTSC_RESUME 0x40 // Force Port Resume\r
	78	#define PORTSC_SUSPEND 0x80 // Port Suspend State\r
	79	#define PORTSC_RESET 0x100 // Port Reset\r
	80	#define PORTSC_LINESTATE_K 0x400 // Line Status K-state\r
	81	#define PORTSC_LINESTATE_J 0x800 // Line Status J-state\r
	82	#define PORTSC_POWER 0x1000 // Port Power\r
	83	#define PORTSC_OWNER 0x2000 // Port Owner\r
	84	#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,\r
	85	// they are WC (write clean)\r
	86	//\r
	87	// PCI Configuration Registers\r
	88	//\r
	89	#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10\r
913cb9dc	90	\r
	91	#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
	92	\r
	93	#define EHC_ADDR(High, QhHw32) \\r
	94	((VOID *) (UINTN) (LShiftU64 ((High), 32) \| ((QhHw32) & 0xFFFFFFF0)))\r
	95	\r
	96	#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
	97	\r
	98	//\r
	99	// Structure to map the hardware port states to the\r
	100	// UEFI's port states.\r
	101	//\r
	102	typedef struct {\r
	103	UINT16 HwState;\r
	104	UINT16 UefiState;\r
	105	} USB_PORT_STATE_MAP;\r
	106	\r
	107	//\r
	108	// Ehci Data and Ctrl Structures\r
	109	//\r
	110	#pragma pack(1)\r
	111	typedef struct {\r
1ccdbf2a	112	UINT8 ProgInterface;\r
913cb9dc	113	UINT8 SubClassCode;\r
	114	UINT8 BaseCode;\r
	115	} USB_CLASSC;\r
	116	#pragma pack()\r
	117	\r
78c2ffb5	118	/**\r
	119	Read EHCI capability register.\r
	120	\r
	121	@param Ehc The EHCI device.\r
	122	@param Offset Capability register address.\r
	123	\r
	124	@return The register content.\r
913cb9dc	125	\r
78c2ffb5	126	**/\r
913cb9dc	127	UINT32\r
	128	EhcReadCapRegister (\r
	129	IN USB2_HC_DEV *Ehc,\r
	130	IN UINT32 Offset\r
ed66e1bc	131	);\r
913cb9dc	132	\r
	133	\r
	134	/**\r
78c2ffb5	135	Read EHCI Operation register.\r
913cb9dc	136	\r
78c2ffb5	137	@param Ehc The EHCI device.\r
78c2ffb5	138	@param Offset The operation register offset.\r
913cb9dc	139	\r
78c2ffb5	140	@return The register content.\r
913cb9dc	141	\r
	142	**/\r
	143	UINT32\r
	144	EhcReadOpReg (\r
	145	IN USB2_HC_DEV *Ehc,\r
	146	IN UINT32 Offset\r
ed66e1bc	147	);\r
913cb9dc	148	\r
	149	\r
	150	/**\r
78c2ffb5	151	Write the data to the EHCI operation register.\r
913cb9dc	152	\r
78c2ffb5	153	@param Ehc The EHCI device.\r
	154	@param Offset EHCI operation register offset.\r
	155	@param Data The data to write.\r
913cb9dc	156	\r
913cb9dc	157	**/\r
	158	VOID\r
	159	EhcWriteOpReg (\r
	160	IN USB2_HC_DEV *Ehc,\r
	161	IN UINT32 Offset,\r
	162	IN UINT32 Data\r
ed66e1bc	163	);\r
913cb9dc	164	\r
efe9186f	165	/**\r
	166	Set one bit of the operational register while keeping other bits.\r
	167	\r
	168	@param Ehc The EHCI device.\r
	169	@param Offset The offset of the operational register.\r
	170	@param Bit The bit mask of the register to set.\r
	171	\r
	172	**/\r
	173	VOID\r
	174	EhcSetOpRegBit (\r
	175	IN USB2_HC_DEV *Ehc,\r
	176	IN UINT32 Offset,\r
	177	IN UINT32 Bit\r
	178	);\r
	179	\r
	180	/**\r
	181	Clear one bit of the operational register while keeping other bits.\r
	182	\r
	183	@param Ehc The EHCI device.\r
	184	@param Offset The offset of the operational register.\r
	185	@param Bit The bit mask of the register to clear.\r
	186	\r
	187	**/\r
	188	VOID\r
	189	EhcClearOpRegBit (\r
	190	IN USB2_HC_DEV *Ehc,\r
	191	IN UINT32 Offset,\r
	192	IN UINT32 Bit\r
	193	);\r
913cb9dc	194	\r
	195	/**\r
	196	Add support for UEFI Over Legacy (UoL) feature, stop\r
78c2ffb5	197	the legacy USB SMI support.\r
913cb9dc	198	\r
	199	@param Ehc The EHCI device.\r
	200	\r
913cb9dc	201	**/\r
	202	VOID\r
	203	EhcClearLegacySupport (\r
	204	IN USB2_HC_DEV *Ehc\r
ed66e1bc	205	);\r
913cb9dc	206	\r
	207	\r
	208	\r
	209	/**\r
	210	Set door bell and wait it to be ACKed by host controller.\r
	211	This function is used to synchronize with the hardware.\r
	212	\r
78c2ffb5	213	@param Ehc The EHCI device.\r
78c2ffb5	214	@param Timeout The time to wait before abort (in millisecond, ms).\r
913cb9dc	215	\r
78c2ffb5	216	@retval EFI_SUCCESS Synchronized with the hardware.\r
78c2ffb5	217	@retval EFI_TIMEOUT Time out happened while waiting door bell to set.\r
913cb9dc	218	\r
	219	**/\r
	220	EFI_STATUS\r
	221	EhcSetAndWaitDoorBell (\r
	222	IN USB2_HC_DEV *Ehc,\r
	223	IN UINT32 Timeout\r
ed66e1bc	224	);\r
913cb9dc	225	\r
	226	\r
	227	/**\r
78c2ffb5	228	Clear all the interrutp status bits, these bits are Write-Clean.\r
913cb9dc	229	\r
78c2ffb5	230	@param Ehc The EHCI device.\r
913cb9dc	231	\r
913cb9dc	232	**/\r
	233	VOID\r
	234	EhcAckAllInterrupt (\r
	235	IN USB2_HC_DEV *Ehc\r
ed66e1bc	236	);\r
913cb9dc	237	\r
	238	\r
	239	\r
	240	/**\r
78c2ffb5	241	Whether Ehc is halted.\r
913cb9dc	242	\r
78c2ffb5	243	@param Ehc The EHCI device.\r
913cb9dc	244	\r
78c2ffb5	245	@retval TRUE The controller is halted.\r
78c2ffb5	246	@retval FALSE It isn't halted.\r
913cb9dc	247	\r
	248	**/\r
	249	BOOLEAN\r
	250	EhcIsHalt (\r
	251	IN USB2_HC_DEV *Ehc\r
ed66e1bc	252	);\r
913cb9dc	253	\r
	254	\r
	255	/**\r
78c2ffb5	256	Whether system error occurred.\r
913cb9dc	257	\r
78c2ffb5	258	@param Ehc The EHCI device.\r
913cb9dc	259	\r
78c2ffb5	260	@retval TRUE System error happened.\r
78c2ffb5	261	@retval FALSE No system error.\r
913cb9dc	262	\r
	263	**/\r
	264	BOOLEAN\r
	265	EhcIsSysError (\r
	266	IN USB2_HC_DEV *Ehc\r
ed66e1bc	267	);\r
913cb9dc	268	\r
913cb9dc	269	\r
913cb9dc	270	/**\r
78c2ffb5	271	Reset the host controller.\r
913cb9dc	272	\r
78c2ffb5	273	@param Ehc The EHCI device.\r
78c2ffb5	274	@param Timeout Time to wait before abort (in millisecond, ms).\r
913cb9dc	275	\r
78c2ffb5	276	@retval EFI_SUCCESS The host controller is reset.\r
78c2ffb5	277	@return Others Failed to reset the host.\r
913cb9dc	278	\r
	279	**/\r
	280	EFI_STATUS\r
	281	EhcResetHC (\r
	282	IN USB2_HC_DEV *Ehc,\r
	283	IN UINT32 Timeout\r
ed66e1bc	284	);\r
913cb9dc	285	\r
913cb9dc	286	\r
913cb9dc	287	/**\r
78c2ffb5	288	Halt the host controller.\r
913cb9dc	289	\r
78c2ffb5	290	@param Ehc The EHCI device.\r
78c2ffb5	291	@param Timeout Time to wait before abort.\r
913cb9dc	292	\r
78c2ffb5	293	@return EFI_SUCCESS The EHCI is halt.\r
78c2ffb5	294	@return EFI_TIMEOUT Failed to halt the controller before Timeout.\r
913cb9dc	295	\r
	296	**/\r
	297	EFI_STATUS\r
	298	EhcHaltHC (\r
	299	IN USB2_HC_DEV *Ehc,\r
	300	IN UINT32 Timeout\r
ed66e1bc	301	);\r
913cb9dc	302	\r
913cb9dc	303	\r
913cb9dc	304	/**\r
78c2ffb5	305	Set the EHCI to run.\r
913cb9dc	306	\r
78c2ffb5	307	@param Ehc The EHCI device.\r
78c2ffb5	308	@param Timeout Time to wait before abort.\r
913cb9dc	309	\r
78c2ffb5	310	@return EFI_SUCCESS The EHCI is running.\r
78c2ffb5	311	@return Others Failed to set the EHCI to run.\r
913cb9dc	312	\r
	313	**/\r
	314	EFI_STATUS\r
	315	EhcRunHC (\r
	316	IN USB2_HC_DEV *Ehc,\r
	317	IN UINT32 Timeout\r
ed66e1bc	318	);\r
913cb9dc	319	\r
	320	\r
	321	\r
	322	/**\r
	323	Initialize the HC hardware.\r
78c2ffb5	324	EHCI spec lists the five things to do to initialize the hardware:\r
913cb9dc	325	1. Program CTRLDSSEGMENT\r
	326	2. Set USBINTR to enable interrupts\r
	327	3. Set periodic list base\r
	328	4. Set USBCMD, interrupt threshold, frame list size etc\r
	329	5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
	330	\r
78c2ffb5	331	@param Ehc The EHCI device.\r
913cb9dc	332	\r
78c2ffb5	333	@return EFI_SUCCESS The EHCI has come out of halt state.\r
78c2ffb5	334	@return EFI_TIMEOUT Time out happened.\r
913cb9dc	335	\r
	336	**/\r
	337	EFI_STATUS\r
	338	EhcInitHC (\r
	339	IN USB2_HC_DEV *Ehc\r
ed66e1bc	340	);\r
913cb9dc	341	\r
913cb9dc	342	#endif\r