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913cb9dc | 1 | /** @file\r |
2 | \r | |
78c2ffb5 | 3 | This file contains the definination for host controller register operation routines.\r |
4 | \r | |
f01219e8 | 5 | Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>\r |
cd5ebaa0 | 6 | This program and the accompanying materials\r |
913cb9dc | 7 | are licensed and made available under the terms and conditions of the BSD License\r |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
913cb9dc | 14 | **/\r |
15 | \r | |
16 | #ifndef _EFI_EHCI_REG_H_\r | |
17 | #define _EFI_EHCI_REG_H_\r | |
18 | \r | |
1ccdbf2a | 19 | //\r |
20 | // EHCI register offset\r | |
21 | //\r | |
22 | \r | |
23 | \r | |
24 | //\r | |
25 | // Capability register offset\r | |
26 | //\r | |
27 | #define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset\r | |
28 | #define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h\r | |
29 | #define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset\r | |
30 | \r | |
31 | //\r | |
32 | // Capability register bit definition\r | |
33 | //\r | |
34 | #define HCSP_NPORTS 0x0F // Number of root hub port\r | |
f01219e8 | 35 | #define HCSP_PPC 0x10 // Port Power Control\r |
1ccdbf2a | 36 | #define HCCP_64BIT 0x01 // 64-bit addressing capability\r |
37 | \r | |
38 | //\r | |
39 | // Operational register offset\r | |
40 | //\r | |
41 | #define EHC_USBCMD_OFFSET 0x0 // USB command register offset\r | |
42 | #define EHC_USBSTS_OFFSET 0x04 // Statue register offset\r | |
43 | #define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset\r | |
44 | #define EHC_FRINDEX_OFFSET 0x0C // Frame index offset\r | |
45 | #define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset\r | |
46 | #define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset\r | |
47 | #define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset\r | |
48 | #define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset\r | |
49 | #define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset\r | |
50 | \r | |
51 | #define EHC_FRAME_LEN 1024\r | |
913cb9dc | 52 | \r |
1ccdbf2a | 53 | //\r |
54 | // Register bit definition\r | |
55 | //\r | |
56 | #define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC\r | |
57 | \r | |
58 | #define USBCMD_RUN 0x01 // Run/stop\r | |
59 | #define USBCMD_RESET 0x02 // Start the host controller reset\r | |
60 | #define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule\r | |
61 | #define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule\r | |
62 | #define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell\r | |
63 | \r | |
64 | #define USBSTS_IAA 0x20 // Interrupt on async advance\r | |
65 | #define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status\r | |
66 | #define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status\r | |
67 | #define USBSTS_HALT 0x1000 // Host controller halted\r | |
68 | #define USBSTS_SYS_ERROR 0x10 // Host system error\r | |
69 | #define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC\r | |
70 | // (write clean) bits in USBSTS register\r | |
71 | \r | |
72 | #define PORTSC_CONN 0x01 // Current Connect Status\r | |
73 | #define PORTSC_CONN_CHANGE 0x02 // Connect Status Change\r | |
74 | #define PORTSC_ENABLED 0x04 // Port Enable / Disable\r | |
75 | #define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change\r | |
76 | #define PORTSC_OVERCUR 0x10 // Over current Active\r | |
77 | #define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change\r | |
78 | #define PORSTSC_RESUME 0x40 // Force Port Resume\r | |
79 | #define PORTSC_SUSPEND 0x80 // Port Suspend State\r | |
80 | #define PORTSC_RESET 0x100 // Port Reset\r | |
81 | #define PORTSC_LINESTATE_K 0x400 // Line Status K-state\r | |
82 | #define PORTSC_LINESTATE_J 0x800 // Line Status J-state\r | |
83 | #define PORTSC_POWER 0x1000 // Port Power\r | |
84 | #define PORTSC_OWNER 0x2000 // Port Owner\r | |
85 | #define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,\r | |
86 | // they are WC (write clean)\r | |
87 | //\r | |
88 | // PCI Configuration Registers\r | |
89 | //\r | |
90 | #define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10\r | |
913cb9dc | 91 | \r |
92 | #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r | |
93 | \r | |
94 | #define EHC_ADDR(High, QhHw32) \\r | |
95 | ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))\r | |
96 | \r | |
97 | #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r | |
98 | \r | |
99 | //\r | |
100 | // Structure to map the hardware port states to the\r | |
101 | // UEFI's port states.\r | |
102 | //\r | |
103 | typedef struct {\r | |
104 | UINT16 HwState;\r | |
105 | UINT16 UefiState;\r | |
106 | } USB_PORT_STATE_MAP;\r | |
107 | \r | |
108 | //\r | |
109 | // Ehci Data and Ctrl Structures\r | |
110 | //\r | |
111 | #pragma pack(1)\r | |
112 | typedef struct {\r | |
1ccdbf2a | 113 | UINT8 ProgInterface;\r |
913cb9dc | 114 | UINT8 SubClassCode;\r |
115 | UINT8 BaseCode;\r | |
116 | } USB_CLASSC;\r | |
117 | #pragma pack()\r | |
118 | \r | |
78c2ffb5 | 119 | /**\r |
120 | Read EHCI capability register.\r | |
121 | \r | |
122 | @param Ehc The EHCI device.\r | |
123 | @param Offset Capability register address.\r | |
124 | \r | |
125 | @return The register content.\r | |
913cb9dc | 126 | \r |
78c2ffb5 | 127 | **/\r |
913cb9dc | 128 | UINT32\r |
129 | EhcReadCapRegister (\r | |
130 | IN USB2_HC_DEV *Ehc,\r | |
131 | IN UINT32 Offset\r | |
ed66e1bc | 132 | );\r |
913cb9dc | 133 | \r |
134 | \r | |
135 | /**\r | |
78c2ffb5 | 136 | Read EHCI Operation register.\r |
913cb9dc | 137 | \r |
78c2ffb5 | 138 | @param Ehc The EHCI device.\r |
139 | @param Offset The operation register offset.\r | |
913cb9dc | 140 | \r |
78c2ffb5 | 141 | @return The register content.\r |
913cb9dc | 142 | \r |
143 | **/\r | |
144 | UINT32\r | |
145 | EhcReadOpReg (\r | |
146 | IN USB2_HC_DEV *Ehc,\r | |
147 | IN UINT32 Offset\r | |
ed66e1bc | 148 | );\r |
913cb9dc | 149 | \r |
150 | \r | |
151 | /**\r | |
78c2ffb5 | 152 | Write the data to the EHCI operation register.\r |
913cb9dc | 153 | \r |
78c2ffb5 | 154 | @param Ehc The EHCI device.\r |
155 | @param Offset EHCI operation register offset.\r | |
156 | @param Data The data to write.\r | |
913cb9dc | 157 | \r |
913cb9dc | 158 | **/\r |
159 | VOID\r | |
160 | EhcWriteOpReg (\r | |
161 | IN USB2_HC_DEV *Ehc,\r | |
162 | IN UINT32 Offset,\r | |
163 | IN UINT32 Data\r | |
ed66e1bc | 164 | );\r |
913cb9dc | 165 | \r |
efe9186f | 166 | /**\r |
167 | Set one bit of the operational register while keeping other bits.\r | |
168 | \r | |
169 | @param Ehc The EHCI device.\r | |
170 | @param Offset The offset of the operational register.\r | |
171 | @param Bit The bit mask of the register to set.\r | |
172 | \r | |
173 | **/\r | |
174 | VOID\r | |
175 | EhcSetOpRegBit (\r | |
176 | IN USB2_HC_DEV *Ehc,\r | |
177 | IN UINT32 Offset,\r | |
178 | IN UINT32 Bit\r | |
179 | );\r | |
180 | \r | |
181 | /**\r | |
182 | Clear one bit of the operational register while keeping other bits.\r | |
183 | \r | |
184 | @param Ehc The EHCI device.\r | |
185 | @param Offset The offset of the operational register.\r | |
186 | @param Bit The bit mask of the register to clear.\r | |
187 | \r | |
188 | **/\r | |
189 | VOID\r | |
190 | EhcClearOpRegBit (\r | |
191 | IN USB2_HC_DEV *Ehc,\r | |
192 | IN UINT32 Offset,\r | |
193 | IN UINT32 Bit\r | |
194 | );\r | |
913cb9dc | 195 | \r |
196 | /**\r | |
197 | Add support for UEFI Over Legacy (UoL) feature, stop\r | |
78c2ffb5 | 198 | the legacy USB SMI support.\r |
913cb9dc | 199 | \r |
200 | @param Ehc The EHCI device.\r | |
201 | \r | |
913cb9dc | 202 | **/\r |
203 | VOID\r | |
204 | EhcClearLegacySupport (\r | |
205 | IN USB2_HC_DEV *Ehc\r | |
ed66e1bc | 206 | );\r |
913cb9dc | 207 | \r |
208 | \r | |
209 | \r | |
210 | /**\r | |
211 | Set door bell and wait it to be ACKed by host controller.\r | |
212 | This function is used to synchronize with the hardware.\r | |
213 | \r | |
78c2ffb5 | 214 | @param Ehc The EHCI device.\r |
215 | @param Timeout The time to wait before abort (in millisecond, ms).\r | |
913cb9dc | 216 | \r |
78c2ffb5 | 217 | @retval EFI_SUCCESS Synchronized with the hardware.\r |
218 | @retval EFI_TIMEOUT Time out happened while waiting door bell to set.\r | |
913cb9dc | 219 | \r |
220 | **/\r | |
221 | EFI_STATUS\r | |
222 | EhcSetAndWaitDoorBell (\r | |
223 | IN USB2_HC_DEV *Ehc,\r | |
224 | IN UINT32 Timeout\r | |
ed66e1bc | 225 | );\r |
913cb9dc | 226 | \r |
227 | \r | |
228 | /**\r | |
78c2ffb5 | 229 | Clear all the interrutp status bits, these bits are Write-Clean.\r |
913cb9dc | 230 | \r |
78c2ffb5 | 231 | @param Ehc The EHCI device.\r |
913cb9dc | 232 | \r |
913cb9dc | 233 | **/\r |
234 | VOID\r | |
235 | EhcAckAllInterrupt (\r | |
236 | IN USB2_HC_DEV *Ehc\r | |
ed66e1bc | 237 | );\r |
913cb9dc | 238 | \r |
239 | \r | |
240 | \r | |
241 | /**\r | |
78c2ffb5 | 242 | Whether Ehc is halted.\r |
913cb9dc | 243 | \r |
78c2ffb5 | 244 | @param Ehc The EHCI device.\r |
913cb9dc | 245 | \r |
78c2ffb5 | 246 | @retval TRUE The controller is halted.\r |
247 | @retval FALSE It isn't halted.\r | |
913cb9dc | 248 | \r |
249 | **/\r | |
250 | BOOLEAN\r | |
251 | EhcIsHalt (\r | |
252 | IN USB2_HC_DEV *Ehc\r | |
ed66e1bc | 253 | );\r |
913cb9dc | 254 | \r |
255 | \r | |
256 | /**\r | |
78c2ffb5 | 257 | Whether system error occurred.\r |
913cb9dc | 258 | \r |
78c2ffb5 | 259 | @param Ehc The EHCI device.\r |
913cb9dc | 260 | \r |
78c2ffb5 | 261 | @retval TRUE System error happened.\r |
262 | @retval FALSE No system error.\r | |
913cb9dc | 263 | \r |
264 | **/\r | |
265 | BOOLEAN\r | |
266 | EhcIsSysError (\r | |
267 | IN USB2_HC_DEV *Ehc\r | |
ed66e1bc | 268 | );\r |
913cb9dc | 269 | \r |
270 | \r | |
913cb9dc | 271 | /**\r |
78c2ffb5 | 272 | Reset the host controller.\r |
913cb9dc | 273 | \r |
78c2ffb5 | 274 | @param Ehc The EHCI device.\r |
275 | @param Timeout Time to wait before abort (in millisecond, ms).\r | |
913cb9dc | 276 | \r |
78c2ffb5 | 277 | @retval EFI_SUCCESS The host controller is reset.\r |
278 | @return Others Failed to reset the host.\r | |
913cb9dc | 279 | \r |
280 | **/\r | |
281 | EFI_STATUS\r | |
282 | EhcResetHC (\r | |
283 | IN USB2_HC_DEV *Ehc,\r | |
284 | IN UINT32 Timeout\r | |
ed66e1bc | 285 | );\r |
913cb9dc | 286 | \r |
287 | \r | |
913cb9dc | 288 | /**\r |
78c2ffb5 | 289 | Halt the host controller.\r |
913cb9dc | 290 | \r |
78c2ffb5 | 291 | @param Ehc The EHCI device.\r |
292 | @param Timeout Time to wait before abort.\r | |
913cb9dc | 293 | \r |
78c2ffb5 | 294 | @return EFI_SUCCESS The EHCI is halt.\r |
295 | @return EFI_TIMEOUT Failed to halt the controller before Timeout.\r | |
913cb9dc | 296 | \r |
297 | **/\r | |
298 | EFI_STATUS\r | |
299 | EhcHaltHC (\r | |
300 | IN USB2_HC_DEV *Ehc,\r | |
301 | IN UINT32 Timeout\r | |
ed66e1bc | 302 | );\r |
913cb9dc | 303 | \r |
304 | \r | |
913cb9dc | 305 | /**\r |
78c2ffb5 | 306 | Set the EHCI to run.\r |
913cb9dc | 307 | \r |
78c2ffb5 | 308 | @param Ehc The EHCI device.\r |
309 | @param Timeout Time to wait before abort.\r | |
913cb9dc | 310 | \r |
78c2ffb5 | 311 | @return EFI_SUCCESS The EHCI is running.\r |
312 | @return Others Failed to set the EHCI to run.\r | |
913cb9dc | 313 | \r |
314 | **/\r | |
315 | EFI_STATUS\r | |
316 | EhcRunHC (\r | |
317 | IN USB2_HC_DEV *Ehc,\r | |
318 | IN UINT32 Timeout\r | |
ed66e1bc | 319 | );\r |
913cb9dc | 320 | \r |
321 | \r | |
322 | \r | |
323 | /**\r | |
324 | Initialize the HC hardware.\r | |
78c2ffb5 | 325 | EHCI spec lists the five things to do to initialize the hardware:\r |
913cb9dc | 326 | 1. Program CTRLDSSEGMENT\r |
327 | 2. Set USBINTR to enable interrupts\r | |
328 | 3. Set periodic list base\r | |
329 | 4. Set USBCMD, interrupt threshold, frame list size etc\r | |
330 | 5. Write 1 to CONFIGFLAG to route all ports to EHCI\r | |
331 | \r | |
78c2ffb5 | 332 | @param Ehc The EHCI device.\r |
913cb9dc | 333 | \r |
78c2ffb5 | 334 | @return EFI_SUCCESS The EHCI has come out of halt state.\r |
335 | @return EFI_TIMEOUT Time out happened.\r | |
913cb9dc | 336 | \r |
337 | **/\r | |
338 | EFI_STATUS\r | |
339 | EhcInitHC (\r | |
340 | IN USB2_HC_DEV *Ehc\r | |
ed66e1bc | 341 | );\r |
913cb9dc | 342 | \r |
343 | #endif\r |