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when timeout is 0, infinite loop on the timeout request to follow UEFI spec
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913cb9dc 1/** @file\r
2\r
78c2ffb5 3 EHCI transfer scheduling routines.\r
4\r
17a6c337 5Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>\r
cd5ebaa0 6This program and the accompanying materials\r
913cb9dc 7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
913cb9dc 14**/\r
15\r
16#include "Ehci.h"\r
17\r
18\r
19/**\r
78c2ffb5 20 Create helper QTD/QH for the EHCI device.\r
913cb9dc 21\r
78c2ffb5 22 @param Ehc The EHCI device.\r
913cb9dc 23\r
78c2ffb5 24 @retval EFI_OUT_OF_RESOURCES Failed to allocate resource for helper QTD/QH.\r
25 @retval EFI_SUCCESS Helper QH/QTD are created.\r
913cb9dc 26\r
27**/\r
913cb9dc 28EFI_STATUS\r
29EhcCreateHelpQ (\r
30 IN USB2_HC_DEV *Ehc\r
31 )\r
32{\r
33 USB_ENDPOINT Ep;\r
34 EHC_QH *Qh;\r
35 QH_HW *QhHw;\r
36 EHC_QTD *Qtd;\r
739802e4 37 EFI_PHYSICAL_ADDRESS PciAddr;\r
913cb9dc 38\r
39 //\r
40 // Create an inactive Qtd to terminate the short packet read.\r
41 //\r
739802e4 42 Qtd = EhcCreateQtd (Ehc, NULL, NULL, 0, QTD_PID_INPUT, 0, 64);\r
913cb9dc 43\r
44 if (Qtd == NULL) {\r
45 return EFI_OUT_OF_RESOURCES;\r
46 }\r
47\r
48 Qtd->QtdHw.Status = QTD_STAT_HALTED;\r
49 Ehc->ShortReadStop = Qtd;\r
50\r
51 //\r
52 // Create a QH to act as the EHC reclamation header.\r
53 // Set the header to loopback to itself.\r
54 //\r
55 Ep.DevAddr = 0;\r
56 Ep.EpAddr = 1;\r
57 Ep.Direction = EfiUsbDataIn;\r
58 Ep.DevSpeed = EFI_USB_SPEED_HIGH;\r
59 Ep.MaxPacket = 64;\r
60 Ep.HubAddr = 0;\r
61 Ep.HubPort = 0;\r
62 Ep.Toggle = 0;\r
63 Ep.Type = EHC_BULK_TRANSFER;\r
64 Ep.PollRate = 1;\r
65\r
66 Qh = EhcCreateQh (Ehc, &Ep);\r
67\r
68 if (Qh == NULL) {\r
69 return EFI_OUT_OF_RESOURCES;\r
70 }\r
71\r
739802e4 72 PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));\r
913cb9dc 73 QhHw = &Qh->QhHw;\r
739802e4 74 QhHw->HorizonLink = QH_LINK (PciAddr + OFFSET_OF(EHC_QH, QhHw), EHC_TYPE_QH, FALSE);\r
913cb9dc 75 QhHw->Status = QTD_STAT_HALTED;\r
76 QhHw->ReclaimHead = 1;\r
3a2f9cce 77 Qh->NextQh = Qh;\r
913cb9dc 78 Ehc->ReclaimHead = Qh;\r
79\r
80 //\r
81 // Create a dummy QH to act as the terminator for periodical schedule\r
82 //\r
83 Ep.EpAddr = 2;\r
84 Ep.Type = EHC_INT_TRANSFER_SYNC;\r
85\r
86 Qh = EhcCreateQh (Ehc, &Ep);\r
87\r
88 if (Qh == NULL) {\r
89 return EFI_OUT_OF_RESOURCES;\r
90 }\r
91\r
92 Qh->QhHw.Status = QTD_STAT_HALTED;\r
93 Ehc->PeriodOne = Qh;\r
94\r
95 return EFI_SUCCESS;\r
96}\r
97\r
98\r
913cb9dc 99/**\r
78c2ffb5 100 Initialize the schedule data structure such as frame list.\r
913cb9dc 101\r
78c2ffb5 102 @param Ehc The EHCI device to init schedule data.\r
913cb9dc 103\r
78c2ffb5 104 @retval EFI_OUT_OF_RESOURCES Failed to allocate resource to init schedule data.\r
105 @retval EFI_SUCCESS The schedule data is initialized.\r
913cb9dc 106\r
107**/\r
108EFI_STATUS\r
109EhcInitSched (\r
110 IN USB2_HC_DEV *Ehc\r
111 )\r
112{\r
113 EFI_PCI_IO_PROTOCOL *PciIo;\r
114 VOID *Buf;\r
115 EFI_PHYSICAL_ADDRESS PhyAddr;\r
116 VOID *Map;\r
117 UINTN Pages;\r
118 UINTN Bytes;\r
119 UINTN Index;\r
913cb9dc 120 EFI_STATUS Status;\r
739802e4 121 EFI_PHYSICAL_ADDRESS PciAddr;\r
913cb9dc 122\r
123 //\r
124 // First initialize the periodical schedule data:\r
125 // 1. Allocate and map the memory for the frame list\r
126 // 2. Create the help QTD/QH\r
127 // 3. Initialize the frame entries\r
128 // 4. Set the frame list register\r
129 //\r
130 PciIo = Ehc->PciIo;\r
131\r
132 Bytes = 4096;\r
133 Pages = EFI_SIZE_TO_PAGES (Bytes);\r
134\r
135 Status = PciIo->AllocateBuffer (\r
136 PciIo,\r
137 AllocateAnyPages,\r
138 EfiBootServicesData,\r
139 Pages,\r
140 &Buf,\r
141 0\r
142 );\r
143\r
144 if (EFI_ERROR (Status)) {\r
145 return EFI_OUT_OF_RESOURCES;\r
146 }\r
147\r
148 Status = PciIo->Map (\r
149 PciIo,\r
150 EfiPciIoOperationBusMasterCommonBuffer,\r
151 Buf,\r
152 &Bytes,\r
153 &PhyAddr,\r
154 &Map\r
155 );\r
156\r
157 if (EFI_ERROR (Status) || (Bytes != 4096)) {\r
158 PciIo->FreeBuffer (PciIo, Pages, Buf);\r
159 return EFI_OUT_OF_RESOURCES;\r
160 }\r
161\r
592b87a4 162 Ehc->PeriodFrame = Buf;\r
913cb9dc 163 Ehc->PeriodFrameMap = Map;\r
592b87a4 164\r
165 //\r
166 // Program the FRAMELISTBASE register with the low 32 bit addr\r
167 //\r
168 EhcWriteOpReg (Ehc, EHC_FRAME_BASE_OFFSET, EHC_LOW_32BIT (PhyAddr));\r
169 //\r
170 // Program the CTRLDSSEGMENT register with the high 32 bit addr\r
171 //\r
172 EhcWriteOpReg (Ehc, EHC_CTRLDSSEG_OFFSET, EHC_HIGH_32BIT (PhyAddr));\r
913cb9dc 173\r
174 //\r
175 // Init memory pool management then create the helper\r
176 // QTD/QH. If failed, previously allocated resources\r
177 // will be freed by EhcFreeSched\r
178 //\r
179 Ehc->MemPool = UsbHcInitMemPool (\r
180 PciIo,\r
181 EHC_BIT_IS_SET (Ehc->HcCapParams, HCCP_64BIT),\r
592b87a4 182 EHC_HIGH_32BIT (PhyAddr)\r
913cb9dc 183 );\r
184\r
185 if (Ehc->MemPool == NULL) {\r
60cf9cfc 186 Status = EFI_OUT_OF_RESOURCES;\r
187 goto ErrorExit1;\r
913cb9dc 188 }\r
189\r
190 Status = EhcCreateHelpQ (Ehc);\r
191\r
192 if (EFI_ERROR (Status)) {\r
592b87a4 193 goto ErrorExit;\r
913cb9dc 194 }\r
195\r
196 //\r
197 // Initialize the frame list entries then set the registers\r
198 //\r
592b87a4 199 Ehc->PeriodFrameHost = AllocateZeroPool (EHC_FRAME_LEN * sizeof (UINTN));\r
200 if (Ehc->PeriodFrameHost == NULL) {\r
201 Status = EFI_OUT_OF_RESOURCES;\r
202 goto ErrorExit;\r
203 }\r
204\r
205 PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (EHC_QH));\r
913cb9dc 206\r
207 for (Index = 0; Index < EHC_FRAME_LEN; Index++) {\r
592b87a4 208 //\r
209 // Store the pci bus address of the QH in period frame list which will be accessed by pci bus master.\r
210 //\r
211 ((UINT32 *)(Ehc->PeriodFrame))[Index] = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
212 //\r
213 // Store the host address of the QH in period frame list which will be accessed by host.\r
214 //\r
215 ((UINTN *)(Ehc->PeriodFrameHost))[Index] = (UINTN)Ehc->PeriodOne;\r
913cb9dc 216 }\r
217\r
913cb9dc 218 //\r
219 // Second initialize the asynchronous schedule:\r
220 // Only need to set the AsynListAddr register to\r
221 // the reclamation header\r
222 //\r
739802e4 223 PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ReclaimHead, sizeof (EHC_QH));\r
224 EhcWriteOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET, EHC_LOW_32BIT (PciAddr));\r
913cb9dc 225 return EFI_SUCCESS;\r
592b87a4 226\r
227ErrorExit:\r
592b87a4 228 if (Ehc->PeriodOne != NULL) {\r
229 UsbHcFreeMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (EHC_QH));\r
230 Ehc->PeriodOne = NULL;\r
231 }\r
232\r
233 if (Ehc->ReclaimHead != NULL) {\r
234 UsbHcFreeMem (Ehc->MemPool, Ehc->ReclaimHead, sizeof (EHC_QH));\r
235 Ehc->ReclaimHead = NULL;\r
236 }\r
237\r
238 if (Ehc->ShortReadStop != NULL) {\r
239 UsbHcFreeMem (Ehc->MemPool, Ehc->ShortReadStop, sizeof (EHC_QTD));\r
240 Ehc->ShortReadStop = NULL;\r
241 }\r
60cf9cfc 242\r
243ErrorExit1:\r
244 PciIo->FreeBuffer (PciIo, Pages, Buf);\r
245 PciIo->Unmap (PciIo, Map);\r
246\r
592b87a4 247 return Status;\r
913cb9dc 248}\r
249\r
250\r
913cb9dc 251/**\r
252 Free the schedule data. It may be partially initialized.\r
253\r
78c2ffb5 254 @param Ehc The EHCI device.\r
913cb9dc 255\r
913cb9dc 256**/\r
257VOID\r
258EhcFreeSched (\r
259 IN USB2_HC_DEV *Ehc\r
260 )\r
261{\r
262 EFI_PCI_IO_PROTOCOL *PciIo;\r
263\r
264 EhcWriteOpReg (Ehc, EHC_FRAME_BASE_OFFSET, 0);\r
265 EhcWriteOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET, 0);\r
266\r
267 if (Ehc->PeriodOne != NULL) {\r
268 UsbHcFreeMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (EHC_QH));\r
269 Ehc->PeriodOne = NULL;\r
270 }\r
271\r
272 if (Ehc->ReclaimHead != NULL) {\r
273 UsbHcFreeMem (Ehc->MemPool, Ehc->ReclaimHead, sizeof (EHC_QH));\r
274 Ehc->ReclaimHead = NULL;\r
275 }\r
276\r
277 if (Ehc->ShortReadStop != NULL) {\r
278 UsbHcFreeMem (Ehc->MemPool, Ehc->ShortReadStop, sizeof (EHC_QTD));\r
279 Ehc->ShortReadStop = NULL;\r
280 }\r
281\r
282 if (Ehc->MemPool != NULL) {\r
283 UsbHcFreeMemPool (Ehc->MemPool);\r
284 Ehc->MemPool = NULL;\r
285 }\r
286\r
592b87a4 287 if (Ehc->PeriodFrame != NULL) {\r
913cb9dc 288 PciIo = Ehc->PciIo;\r
289 ASSERT (PciIo != NULL);\r
290\r
291 PciIo->Unmap (PciIo, Ehc->PeriodFrameMap);\r
292\r
293 PciIo->FreeBuffer (\r
294 PciIo,\r
295 EFI_SIZE_TO_PAGES (EFI_PAGE_SIZE),\r
592b87a4 296 Ehc->PeriodFrame\r
913cb9dc 297 );\r
298\r
592b87a4 299 Ehc->PeriodFrame = NULL;\r
300 }\r
301\r
302 if (Ehc->PeriodFrameHost != NULL) {\r
303 FreePool (Ehc->PeriodFrameHost);\r
739802e4 304 Ehc->PeriodFrameHost = NULL;\r
913cb9dc 305 }\r
306}\r
307\r
308\r
913cb9dc 309/**\r
310 Link the queue head to the asynchronous schedule list.\r
311 UEFI only supports one CTRL/BULK transfer at a time\r
312 due to its interfaces. This simplifies the AsynList\r
313 management: A reclamation header is always linked to\r
314 the AsyncListAddr, the only active QH is appended to it.\r
315\r
78c2ffb5 316 @param Ehc The EHCI device.\r
317 @param Qh The queue head to link.\r
913cb9dc 318\r
913cb9dc 319**/\r
320VOID\r
321EhcLinkQhToAsync (\r
322 IN USB2_HC_DEV *Ehc,\r
323 IN EHC_QH *Qh\r
324 )\r
325{\r
326 EHC_QH *Head;\r
739802e4 327 EFI_PHYSICAL_ADDRESS PciAddr;\r
913cb9dc 328\r
329 //\r
330 // Append the queue head after the reclaim header, then\r
331 // fix the hardware visiable parts (EHCI R1.0 page 72).\r
332 // ReclaimHead is always linked to the EHCI's AsynListAddr.\r
333 //\r
334 Head = Ehc->ReclaimHead;\r
335\r
336 Qh->NextQh = Head->NextQh;\r
337 Head->NextQh = Qh;\r
338\r
3a2f9cce 339 PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh->NextQh, sizeof (EHC_QH));\r
592b87a4 340 Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
3a2f9cce 341 PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));\r
739802e4 342 Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
913cb9dc 343}\r
344\r
345\r
346/**\r
347 Unlink a queue head from the asynchronous schedule list.\r
78c2ffb5 348 Need to synchronize with hardware.\r
913cb9dc 349\r
78c2ffb5 350 @param Ehc The EHCI device.\r
351 @param Qh The queue head to unlink.\r
913cb9dc 352\r
913cb9dc 353**/\r
354VOID\r
355EhcUnlinkQhFromAsync (\r
356 IN USB2_HC_DEV *Ehc,\r
357 IN EHC_QH *Qh\r
358 )\r
359{\r
360 EHC_QH *Head;\r
361 EFI_STATUS Status;\r
739802e4 362 EFI_PHYSICAL_ADDRESS PciAddr;\r
913cb9dc 363\r
364 ASSERT (Ehc->ReclaimHead->NextQh == Qh);\r
365\r
366 //\r
367 // Remove the QH from reclamation head, then update the hardware\r
368 // visiable part: Only need to loopback the ReclaimHead. The Qh\r
369 // is pointing to ReclaimHead (which is staill in the list).\r
370 //\r
371 Head = Ehc->ReclaimHead;\r
372\r
373 Head->NextQh = Qh->NextQh;\r
374 Qh->NextQh = NULL;\r
375\r
3a2f9cce 376 PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));\r
739802e4 377 Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
913cb9dc 378\r
379 //\r
380 // Set and wait the door bell to synchronize with the hardware\r
381 //\r
41e8ff27 382 Status = EhcSetAndWaitDoorBell (Ehc, EHC_GENERIC_TIMEOUT);\r
913cb9dc 383\r
384 if (EFI_ERROR (Status)) {\r
1c619535 385 DEBUG ((EFI_D_ERROR, "EhcUnlinkQhFromAsync: Failed to synchronize with doorbell\n"));\r
913cb9dc 386 }\r
387}\r
388\r
389\r
390/**\r
391 Link a queue head for interrupt transfer to the periodic\r
392 schedule frame list. This code is very much the same as\r
393 that in UHCI.\r
394\r
78c2ffb5 395 @param Ehc The EHCI device.\r
396 @param Qh The queue head to link.\r
913cb9dc 397\r
913cb9dc 398**/\r
399VOID\r
400EhcLinkQhToPeriod (\r
401 IN USB2_HC_DEV *Ehc,\r
402 IN EHC_QH *Qh\r
403 )\r
404{\r
913cb9dc 405 UINTN Index;\r
406 EHC_QH *Prev;\r
407 EHC_QH *Next;\r
739802e4 408 EFI_PHYSICAL_ADDRESS PciAddr;\r
913cb9dc 409\r
913cb9dc 410 for (Index = 0; Index < EHC_FRAME_LEN; Index += Qh->Interval) {\r
411 //\r
412 // First QH can't be NULL because we always keep PeriodOne\r
413 // heads on the frame list\r
414 //\r
592b87a4 415 ASSERT (!EHC_LINK_TERMINATED (((UINT32*)Ehc->PeriodFrame)[Index]));\r
416 Next = (EHC_QH*)((UINTN*)Ehc->PeriodFrameHost)[Index];\r
913cb9dc 417 Prev = NULL;\r
418\r
419 //\r
420 // Now, insert the queue head (Qh) into this frame:\r
421 // 1. Find a queue head with the same poll interval, just insert\r
422 // Qh after this queue head, then we are done.\r
423 //\r
424 // 2. Find the position to insert the queue head into:\r
425 // Previous head's interval is bigger than Qh's\r
426 // Next head's interval is less than Qh's\r
427 // Then, insert the Qh between then\r
428 //\r
429 while (Next->Interval > Qh->Interval) {\r
430 Prev = Next;\r
431 Next = Next->NextQh;\r
432 }\r
433\r
434 ASSERT (Next != NULL);\r
435\r
436 //\r
437 // The entry may have been linked into the frame by early insertation.\r
438 // For example: if insert a Qh with Qh.Interval == 4, and there is a Qh\r
439 // with Qh.Interval == 8 on the frame. If so, we are done with this frame.\r
440 // It isn't necessary to compare all the QH with the same interval to\r
441 // Qh. This is because if there is other QH with the same interval, Qh\r
442 // should has been inserted after that at Frames[0] and at Frames[0] it is\r
443 // impossible for (Next == Qh)\r
444 //\r
445 if (Next == Qh) {\r
446 continue;\r
447 }\r
448\r
449 if (Next->Interval == Qh->Interval) {\r
450 //\r
451 // If there is a QH with the same interval, it locates at\r
452 // Frames[0], and we can simply insert it after this QH. We\r
453 // are all done.\r
454 //\r
455 ASSERT ((Index == 0) && (Qh->NextQh == NULL));\r
456\r
457 Prev = Next;\r
458 Next = Next->NextQh;\r
459\r
460 Qh->NextQh = Next;\r
461 Prev->NextQh = Qh;\r
462\r
463 Qh->QhHw.HorizonLink = Prev->QhHw.HorizonLink;\r
739802e4 464 PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));\r
465 Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
913cb9dc 466 break;\r
467 }\r
468\r
469 //\r
470 // OK, find the right position, insert it in. If Qh's next\r
471 // link has already been set, it is in position. This is\r
472 // guarranted by 2^n polling interval.\r
473 //\r
474 if (Qh->NextQh == NULL) {\r
475 Qh->NextQh = Next;\r
739802e4 476 PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Next, sizeof (EHC_QH));\r
477 Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
913cb9dc 478 }\r
479\r
739802e4 480 PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));\r
481\r
913cb9dc 482 if (Prev == NULL) {\r
592b87a4 483 ((UINT32*)Ehc->PeriodFrame)[Index] = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
484 ((UINTN*)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh;\r
913cb9dc 485 } else {\r
486 Prev->NextQh = Qh;\r
739802e4 487 Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
913cb9dc 488 }\r
489 }\r
490}\r
491\r
492\r
493/**\r
494 Unlink an interrupt queue head from the periodic\r
78c2ffb5 495 schedule frame list.\r
913cb9dc 496\r
78c2ffb5 497 @param Ehc The EHCI device.\r
498 @param Qh The queue head to unlink.\r
913cb9dc 499\r
913cb9dc 500**/\r
501VOID\r
502EhcUnlinkQhFromPeriod (\r
503 IN USB2_HC_DEV *Ehc,\r
504 IN EHC_QH *Qh\r
505 )\r
506{\r
913cb9dc 507 UINTN Index;\r
508 EHC_QH *Prev;\r
509 EHC_QH *This;\r
510\r
913cb9dc 511 for (Index = 0; Index < EHC_FRAME_LEN; Index += Qh->Interval) {\r
512 //\r
513 // Frame link can't be NULL because we always keep PeroidOne\r
514 // on the frame list\r
515 //\r
592b87a4 516 ASSERT (!EHC_LINK_TERMINATED (((UINT32*)Ehc->PeriodFrame)[Index]));\r
517 This = (EHC_QH*)((UINTN*)Ehc->PeriodFrameHost)[Index];\r
913cb9dc 518 Prev = NULL;\r
519\r
520 //\r
521 // Walk through the frame's QH list to find the\r
522 // queue head to remove\r
523 //\r
524 while ((This != NULL) && (This != Qh)) {\r
525 Prev = This;\r
526 This = This->NextQh;\r
527 }\r
528\r
529 //\r
530 // Qh may have already been unlinked from this frame\r
531 // by early action. See the comments in EhcLinkQhToPeriod.\r
532 //\r
533 if (This == NULL) {\r
534 continue;\r
535 }\r
536\r
537 if (Prev == NULL) {\r
538 //\r
539 // Qh is the first entry in the frame\r
540 //\r
592b87a4 541 ((UINT32*)Ehc->PeriodFrame)[Index] = Qh->QhHw.HorizonLink;\r
542 ((UINTN*)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh->NextQh;\r
913cb9dc 543 } else {\r
544 Prev->NextQh = Qh->NextQh;\r
545 Prev->QhHw.HorizonLink = Qh->QhHw.HorizonLink;\r
546 }\r
547 }\r
548}\r
549\r
550\r
913cb9dc 551/**\r
552 Check the URB's execution result and update the URB's\r
553 result accordingly.\r
554\r
78c2ffb5 555 @param Ehc The EHCI device.\r
556 @param Urb The URB to check result.\r
913cb9dc 557\r
558 @return Whether the result of URB transfer is finialized.\r
559\r
560**/\r
913cb9dc 561BOOLEAN\r
562EhcCheckUrbResult (\r
563 IN USB2_HC_DEV *Ehc,\r
564 IN URB *Urb\r
565 )\r
566{\r
567 LIST_ENTRY *Entry;\r
568 EHC_QTD *Qtd;\r
569 QTD_HW *QtdHw;\r
570 UINT8 State;\r
571 BOOLEAN Finished;\r
739802e4 572 EFI_PHYSICAL_ADDRESS PciAddr;\r
913cb9dc 573\r
574 ASSERT ((Ehc != NULL) && (Urb != NULL) && (Urb->Qh != NULL));\r
575\r
576 Finished = TRUE;\r
577 Urb->Completed = 0;\r
578\r
579 Urb->Result = EFI_USB_NOERROR;\r
580\r
581 if (EhcIsHalt (Ehc) || EhcIsSysError (Ehc)) {\r
582 Urb->Result |= EFI_USB_ERR_SYSTEM;\r
583 goto ON_EXIT;\r
584 }\r
585\r
586 EFI_LIST_FOR_EACH (Entry, &Urb->Qh->Qtds) {\r
587 Qtd = EFI_LIST_CONTAINER (Entry, EHC_QTD, QtdList);\r
588 QtdHw = &Qtd->QtdHw;\r
589 State = (UINT8) QtdHw->Status;\r
590\r
591 if (EHC_BIT_IS_SET (State, QTD_STAT_HALTED)) {\r
592 //\r
593 // EHCI will halt the queue head when met some error.\r
594 // If it is halted, the result of URB is finialized.\r
595 //\r
596 if ((State & QTD_STAT_ERR_MASK) == 0) {\r
597 Urb->Result |= EFI_USB_ERR_STALL;\r
598 }\r
599\r
600 if (EHC_BIT_IS_SET (State, QTD_STAT_BABBLE_ERR)) {\r
601 Urb->Result |= EFI_USB_ERR_BABBLE;\r
602 }\r
603\r
604 if (EHC_BIT_IS_SET (State, QTD_STAT_BUFF_ERR)) {\r
605 Urb->Result |= EFI_USB_ERR_BUFFER;\r
606 }\r
607\r
608 if (EHC_BIT_IS_SET (State, QTD_STAT_TRANS_ERR) && (QtdHw->ErrCnt == 0)) {\r
609 Urb->Result |= EFI_USB_ERR_TIMEOUT;\r
610 }\r
611\r
612 Finished = TRUE;\r
613 goto ON_EXIT;\r
614\r
615 } else if (EHC_BIT_IS_SET (State, QTD_STAT_ACTIVE)) {\r
616 //\r
617 // The QTD is still active, no need to check furthur.\r
618 //\r
619 Urb->Result |= EFI_USB_ERR_NOTEXECUTE;\r
620\r
621 Finished = FALSE;\r
622 goto ON_EXIT;\r
623\r
624 } else {\r
625 //\r
626 // This QTD is finished OK or met short packet read. Update the\r
627 // transfer length if it isn't a setup.\r
628 //\r
629 if (QtdHw->Pid != QTD_PID_SETUP) {\r
630 Urb->Completed += Qtd->DataLen - QtdHw->TotalBytes;\r
631 }\r
632\r
633 if ((QtdHw->TotalBytes != 0) && (QtdHw->Pid == QTD_PID_INPUT)) {\r
1c619535 634 EhcDumpQh (Urb->Qh, "Short packet read", FALSE);\r
913cb9dc 635\r
636 //\r
637 // Short packet read condition. If it isn't a setup transfer,\r
638 // no need to check furthur: the queue head will halt at the\r
639 // ShortReadStop. If it is a setup transfer, need to check the\r
640 // Status Stage of the setup transfer to get the finial result\r
641 //\r
739802e4 642 PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ShortReadStop, sizeof (EHC_QTD));\r
643 if (QtdHw->AltNext == QTD_LINK (PciAddr, FALSE)) {\r
1c619535 644 DEBUG ((EFI_D_INFO, "EhcCheckUrbResult: Short packet read, break\n"));\r
913cb9dc 645\r
646 Finished = TRUE;\r
647 goto ON_EXIT;\r
648 }\r
649\r
1c619535 650 DEBUG ((EFI_D_INFO, "EhcCheckUrbResult: Short packet read, continue\n"));\r
913cb9dc 651 }\r
652 }\r
653 }\r
654\r
655ON_EXIT:\r
656 //\r
657 // Return the data toggle set by EHCI hardware, bulk and interrupt\r
658 // transfer will use this to initialize the next transaction. For\r
659 // Control transfer, it always start a new data toggle sequence for\r
660 // new transfer.\r
661 //\r
662 // NOTICE: don't move DT update before the loop, otherwise there is\r
663 // a race condition that DT is wrong.\r
664 //\r
665 Urb->DataToggle = (UINT8) Urb->Qh->QhHw.DataToggle;\r
666\r
667 return Finished;\r
668}\r
669\r
670\r
671/**\r
672 Execute the transfer by polling the URB. This is a synchronous operation.\r
673\r
78c2ffb5 674 @param Ehc The EHCI device.\r
675 @param Urb The URB to execute.\r
676 @param TimeOut The time to wait before abort, in millisecond.\r
913cb9dc 677\r
78c2ffb5 678 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r
679 @return EFI_TIMEOUT The transfer failed due to time out.\r
680 @return EFI_SUCCESS The transfer finished OK.\r
913cb9dc 681\r
682**/\r
683EFI_STATUS\r
684EhcExecTransfer (\r
685 IN USB2_HC_DEV *Ehc,\r
686 IN URB *Urb,\r
687 IN UINTN TimeOut\r
688 )\r
689{\r
690 EFI_STATUS Status;\r
691 UINTN Index;\r
692 UINTN Loop;\r
693 BOOLEAN Finished;\r
17a6c337 694 BOOLEAN InfiniteLoop;\r
913cb9dc 695\r
17a6c337 696 Status = EFI_SUCCESS;\r
697 Loop = (TimeOut * EHC_1_MILLISECOND / EHC_SYNC_POLL_INTERVAL) + 1;\r
698 Finished = FALSE;\r
699 InfiniteLoop = FALSE;\r
913cb9dc 700\r
17a6c337 701 //\r
702 // According to UEFI spec section 16.2.4, If Timeout is 0, then the caller\r
703 // must wait for the function to be completed until EFI_SUCCESS or EFI_DEVICE_ERROR\r
704 // is returned.\r
705 //\r
706 if (TimeOut == 0) {\r
707 InfiniteLoop = TRUE;\r
708 }\r
709\r
710 for (Index = 0; InfiniteLoop || (Index < Loop); Index++) {\r
913cb9dc 711 Finished = EhcCheckUrbResult (Ehc, Urb);\r
712\r
713 if (Finished) {\r
714 break;\r
715 }\r
716\r
41e8ff27 717 gBS->Stall (EHC_SYNC_POLL_INTERVAL);\r
913cb9dc 718 }\r
719\r
720 if (!Finished) {\r
7df7393f 721 DEBUG ((EFI_D_ERROR, "EhcExecTransfer: transfer not finished in %dms\n", (UINT32)TimeOut));\r
1c619535 722 EhcDumpQh (Urb->Qh, NULL, FALSE);\r
913cb9dc 723\r
724 Status = EFI_TIMEOUT;\r
725\r
726 } else if (Urb->Result != EFI_USB_NOERROR) {\r
1c619535 727 DEBUG ((EFI_D_ERROR, "EhcExecTransfer: transfer failed with %x\n", Urb->Result));\r
728 EhcDumpQh (Urb->Qh, NULL, FALSE);\r
913cb9dc 729\r
730 Status = EFI_DEVICE_ERROR;\r
731 }\r
732\r
733 return Status;\r
734}\r
735\r
736\r
737/**\r
738 Delete a single asynchronous interrupt transfer for\r
78c2ffb5 739 the device and endpoint.\r
913cb9dc 740\r
78c2ffb5 741 @param Ehc The EHCI device.\r
742 @param DevAddr The address of the target device.\r
743 @param EpNum The endpoint of the target.\r
744 @param DataToggle Return the next data toggle to use.\r
913cb9dc 745\r
78c2ffb5 746 @retval EFI_SUCCESS An asynchronous transfer is removed.\r
747 @retval EFI_NOT_FOUND No transfer for the device is found.\r
913cb9dc 748\r
749**/\r
750EFI_STATUS\r
751EhciDelAsyncIntTransfer (\r
752 IN USB2_HC_DEV *Ehc,\r
753 IN UINT8 DevAddr,\r
754 IN UINT8 EpNum,\r
755 OUT UINT8 *DataToggle\r
756 )\r
757{\r
758 LIST_ENTRY *Entry;\r
759 LIST_ENTRY *Next;\r
760 URB *Urb;\r
761 EFI_USB_DATA_DIRECTION Direction;\r
762\r
78c2ffb5 763 Direction = (((EpNum & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut);\r
913cb9dc 764 EpNum &= 0x0F;\r
765\r
766 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Ehc->AsyncIntTransfers) {\r
767 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
768\r
769 if ((Urb->Ep.DevAddr == DevAddr) && (Urb->Ep.EpAddr == EpNum) &&\r
770 (Urb->Ep.Direction == Direction)) {\r
771 //\r
772 // Check the URB status to retrieve the next data toggle\r
773 // from the associated queue head.\r
774 //\r
775 EhcCheckUrbResult (Ehc, Urb);\r
776 *DataToggle = Urb->DataToggle;\r
777\r
778 EhcUnlinkQhFromPeriod (Ehc, Urb->Qh);\r
779 RemoveEntryList (&Urb->UrbList);\r
780\r
781 gBS->FreePool (Urb->Data);\r
782 EhcFreeUrb (Ehc, Urb);\r
783 return EFI_SUCCESS;\r
784 }\r
785 }\r
786\r
787 return EFI_NOT_FOUND;\r
788}\r
789\r
790\r
791/**\r
78c2ffb5 792 Remove all the asynchronous interrutp transfers.\r
913cb9dc 793\r
78c2ffb5 794 @param Ehc The EHCI device.\r
913cb9dc 795\r
913cb9dc 796**/\r
797VOID\r
798EhciDelAllAsyncIntTransfers (\r
799 IN USB2_HC_DEV *Ehc\r
800 )\r
801{\r
802 LIST_ENTRY *Entry;\r
803 LIST_ENTRY *Next;\r
804 URB *Urb;\r
805\r
806 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Ehc->AsyncIntTransfers) {\r
807 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
808\r
809 EhcUnlinkQhFromPeriod (Ehc, Urb->Qh);\r
810 RemoveEntryList (&Urb->UrbList);\r
811\r
812 gBS->FreePool (Urb->Data);\r
813 EhcFreeUrb (Ehc, Urb);\r
814 }\r
815}\r
816\r
50fa1b3a 817\r
78c2ffb5 818/**\r
1c619535 819 Flush data from PCI controller specific address to mapped system\r
50fa1b3a 820 memory address.\r
821\r
78c2ffb5 822 @param Ehc The EHCI device.\r
823 @param Urb The URB to unmap.\r
50fa1b3a 824\r
78c2ffb5 825 @retval EFI_SUCCESS Success to flush data to mapped system memory.\r
826 @retval EFI_DEVICE_ERROR Fail to flush data to mapped system memory.\r
1c619535 827\r
78c2ffb5 828**/\r
829EFI_STATUS\r
830EhcFlushAsyncIntMap (\r
831 IN USB2_HC_DEV *Ehc,\r
832 IN URB *Urb\r
833 )\r
50fa1b3a 834{\r
835 EFI_STATUS Status;\r
836 EFI_PHYSICAL_ADDRESS PhyAddr;\r
837 EFI_PCI_IO_PROTOCOL_OPERATION MapOp;\r
838 EFI_PCI_IO_PROTOCOL *PciIo;\r
839 UINTN Len;\r
840 VOID *Map;\r
841\r
842 PciIo = Ehc->PciIo;\r
843 Len = Urb->DataLen;\r
844\r
845 if (Urb->Ep.Direction == EfiUsbDataIn) {\r
846 MapOp = EfiPciIoOperationBusMasterWrite;\r
847 } else {\r
848 MapOp = EfiPciIoOperationBusMasterRead;\r
849 }\r
1c619535 850\r
50fa1b3a 851 Status = PciIo->Unmap (PciIo, Urb->DataMap);\r
852 if (EFI_ERROR (Status)) {\r
853 goto ON_ERROR;\r
854 }\r
855\r
856 Urb->DataMap = NULL;\r
857\r
858 Status = PciIo->Map (PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);\r
859 if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {\r
860 goto ON_ERROR;\r
861 }\r
862\r
863 Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);\r
864 Urb->DataMap = Map;\r
865 return EFI_SUCCESS;\r
866\r
867ON_ERROR:\r
868 return EFI_DEVICE_ERROR;\r
869}\r
870\r
913cb9dc 871\r
913cb9dc 872/**\r
78c2ffb5 873 Update the queue head for next round of asynchronous transfer.\r
913cb9dc 874\r
739802e4 875 @param Ehc The EHCI device.\r
78c2ffb5 876 @param Urb The URB to update.\r
913cb9dc 877\r
913cb9dc 878**/\r
913cb9dc 879VOID\r
880EhcUpdateAsyncRequest (\r
739802e4 881 IN USB2_HC_DEV *Ehc,\r
913cb9dc 882 IN URB *Urb\r
883 )\r
884{\r
885 LIST_ENTRY *Entry;\r
886 EHC_QTD *FirstQtd;\r
887 QH_HW *QhHw;\r
888 EHC_QTD *Qtd;\r
889 QTD_HW *QtdHw;\r
890 UINTN Index;\r
739802e4 891 EFI_PHYSICAL_ADDRESS PciAddr;\r
913cb9dc 892\r
893 Qtd = NULL;\r
894\r
895 if (Urb->Result == EFI_USB_NOERROR) {\r
896 FirstQtd = NULL;\r
897\r
898 EFI_LIST_FOR_EACH (Entry, &Urb->Qh->Qtds) {\r
899 Qtd = EFI_LIST_CONTAINER (Entry, EHC_QTD, QtdList);\r
900\r
901 if (FirstQtd == NULL) {\r
902 FirstQtd = Qtd;\r
903 }\r
904\r
905 //\r
906 // Update the QTD for next round of transfer. Host control\r
907 // may change dt/Total Bytes to Transfer/C_Page/Cerr/Status/\r
908 // Current Offset. These fields need to be updated. DT isn't\r
909 // used by interrupt transfer. It uses DT in queue head.\r
910 // Current Offset is in Page[0], only need to reset Page[0]\r
911 // to initial data buffer.\r
912 //\r
913 QtdHw = &Qtd->QtdHw;\r
914 QtdHw->Status = QTD_STAT_ACTIVE;\r
915 QtdHw->ErrCnt = QTD_MAX_ERR;\r
916 QtdHw->CurPage = 0;\r
917 QtdHw->TotalBytes = (UINT32) Qtd->DataLen;\r
aa91de05 918 //\r
919 // calculate physical address by offset.\r
920 //\r
921 PciAddr = (UINTN)Urb->DataPhy + ((UINTN)Qtd->Data - (UINTN)Urb->Data); \r
922 QtdHw->Page[0] = EHC_LOW_32BIT (PciAddr);\r
923 QtdHw->PageHigh[0]= EHC_HIGH_32BIT (PciAddr);\r
913cb9dc 924 }\r
925\r
926 //\r
927 // Update QH for next round of transfer. Host control only\r
928 // touch the fields in transfer overlay area. Only need to\r
929 // zero out the overlay area and set NextQtd to the first\r
930 // QTD. DateToggle bit is left untouched.\r
931 //\r
932 QhHw = &Urb->Qh->QhHw;\r
933 QhHw->CurQtd = QTD_LINK (0, TRUE);\r
934 QhHw->AltQtd = 0;\r
935\r
936 QhHw->Status = 0;\r
937 QhHw->Pid = 0;\r
938 QhHw->ErrCnt = 0;\r
939 QhHw->CurPage = 0;\r
1ccdbf2a 940 QhHw->Ioc = 0;\r
913cb9dc 941 QhHw->TotalBytes = 0;\r
942\r
943 for (Index = 0; Index < 5; Index++) {\r
944 QhHw->Page[Index] = 0;\r
945 QhHw->PageHigh[Index] = 0;\r
946 }\r
947\r
739802e4 948 PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, FirstQtd, sizeof (EHC_QTD));\r
949 QhHw->NextQtd = QTD_LINK (PciAddr, FALSE);\r
913cb9dc 950 }\r
951\r
952 return ;\r
953}\r
954\r
955\r
956/**\r
78c2ffb5 957 Interrupt transfer periodic check handler.\r
913cb9dc 958\r
78c2ffb5 959 @param Event Interrupt event.\r
960 @param Context Pointer to USB2_HC_DEV.\r
913cb9dc 961\r
913cb9dc 962**/\r
963VOID\r
6d3ea23f 964EFIAPI\r
597f4ee2 965EhcMonitorAsyncRequests (\r
913cb9dc 966 IN EFI_EVENT Event,\r
967 IN VOID *Context\r
968 )\r
969{\r
970 USB2_HC_DEV *Ehc;\r
971 EFI_TPL OldTpl;\r
972 LIST_ENTRY *Entry;\r
973 LIST_ENTRY *Next;\r
974 BOOLEAN Finished;\r
975 UINT8 *ProcBuf;\r
976 URB *Urb;\r
50fa1b3a 977 EFI_STATUS Status;\r
913cb9dc 978\r
979 OldTpl = gBS->RaiseTPL (EHC_TPL);\r
980 Ehc = (USB2_HC_DEV *) Context;\r
981\r
982 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Ehc->AsyncIntTransfers) {\r
983 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
984\r
985 //\r
986 // Check the result of URB execution. If it is still\r
987 // active, check the next one.\r
988 //\r
989 Finished = EhcCheckUrbResult (Ehc, Urb);\r
990\r
991 if (!Finished) {\r
992 continue;\r
993 }\r
994\r
50fa1b3a 995 //\r
1c619535 996 // Flush any PCI posted write transactions from a PCI host\r
50fa1b3a 997 // bridge to system memory.\r
998 //\r
999 Status = EhcFlushAsyncIntMap (Ehc, Urb);\r
1000 if (EFI_ERROR (Status)) {\r
597f4ee2 1001 DEBUG ((EFI_D_ERROR, "EhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));\r
50fa1b3a 1002 }\r
1c619535 1003\r
913cb9dc 1004 //\r
1005 // Allocate a buffer then copy the transferred data for user.\r
1006 // If failed to allocate the buffer, update the URB for next\r
1007 // round of transfer. Ignore the data of this round.\r
1008 //\r
1009 ProcBuf = NULL;\r
1010\r
1011 if (Urb->Result == EFI_USB_NOERROR) {\r
1012 ASSERT (Urb->Completed <= Urb->DataLen);\r
1013\r
1014 ProcBuf = AllocatePool (Urb->Completed);\r
1015\r
1016 if (ProcBuf == NULL) {\r
739802e4 1017 EhcUpdateAsyncRequest (Ehc, Urb);\r
913cb9dc 1018 continue;\r
1019 }\r
1020\r
1021 CopyMem (ProcBuf, Urb->Data, Urb->Completed);\r
1022 }\r
1023\r
739802e4 1024 EhcUpdateAsyncRequest (Ehc, Urb);\r
913cb9dc 1025\r
1026 //\r
1027 // Leave error recovery to its related device driver. A\r
1028 // common case of the error recovery is to re-submit the\r
1029 // interrupt transfer which is linked to the head of the\r
1030 // list. This function scans from head to tail. So the\r
1031 // re-submitted interrupt transfer's callback function\r
1032 // will not be called again in this round. Don't touch this\r
1033 // URB after the callback, it may have been removed by the\r
1034 // callback.\r
1035 //\r
1036 if (Urb->Callback != NULL) {\r
1037 //\r
1038 // Restore the old TPL, USB bus maybe connect device in\r
1039 // his callback. Some drivers may has a lower TPL restriction.\r
1040 //\r
1041 gBS->RestoreTPL (OldTpl);\r
1042 (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);\r
1043 OldTpl = gBS->RaiseTPL (EHC_TPL);\r
1044 }\r
1045\r
1046 if (ProcBuf != NULL) {\r
7351070b 1047 FreePool (ProcBuf);\r
913cb9dc 1048 }\r
1049 }\r
1050\r
1051 gBS->RestoreTPL (OldTpl);\r
1052}\r