| 913cb9dc |
1 | /** @file\r |
| 2 | \r |
| 3 | Copyright (c) 2007, Intel Corporation\r |
| 4 | All rights reserved. This program and the accompanying materials\r |
| 5 | are licensed and made available under the terms and conditions of the BSD License\r |
| 6 | which accompanies this distribution. The full text of the license may be found at\r |
| 7 | http://opensource.org/licenses/bsd-license.php\r |
| 8 | \r |
| 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 11 | \r |
| 12 | Module Name:\r |
| 13 | \r |
| 14 | EhciUrb.h\r |
| 15 | \r |
| 16 | Abstract:\r |
| 17 | \r |
| 18 | This file contains URB request, each request is warpped in a\r |
| 19 | URB (Usb Request Block)\r |
| 20 | \r |
| 21 | Revision History\r |
| 22 | \r |
| 23 | **/\r |
| 24 | \r |
| 25 | #ifndef _EFI_EHCI_URB_H_\r |
| 26 | #define _EFI_EHCI_URB_H_\r |
| 27 | \r |
| 28 | \r |
| 29 | typedef struct _EHC_QTD EHC_QTD;\r |
| 30 | typedef struct _EHC_QH EHC_QH;\r |
| 31 | typedef struct _URB URB;\r |
| 32 | \r |
| 33 | enum {\r |
| 34 | //\r |
| 35 | // Transfer types, used in URB to identify the transfer type\r |
| 36 | //\r |
| 37 | EHC_CTRL_TRANSFER = 0x01,\r |
| 38 | EHC_BULK_TRANSFER = 0x02,\r |
| 39 | EHC_INT_TRANSFER_SYNC = 0x04,\r |
| 40 | EHC_INT_TRANSFER_ASYNC = 0x08,\r |
| 41 | \r |
| 42 | EHC_QTD_SIG = EFI_SIGNATURE_32 ('U', 'S', 'B', 'T'),\r |
| 43 | EHC_QH_SIG = EFI_SIGNATURE_32 ('U', 'S', 'B', 'H'),\r |
| 44 | EHC_URB_SIG = EFI_SIGNATURE_32 ('U', 'S', 'B', 'R'),\r |
| 45 | \r |
| 46 | //\r |
| 47 | // Hardware related bit definitions\r |
| 48 | //\r |
| 49 | EHC_TYPE_ITD = 0x00,\r |
| 50 | EHC_TYPE_QH = 0x02,\r |
| 51 | EHC_TYPE_SITD = 0x04,\r |
| 52 | EHC_TYPE_FSTN = 0x06,\r |
| 53 | \r |
| 54 | QH_NAK_RELOAD = 3,\r |
| 55 | QH_HSHBW_MULTI = 1,\r |
| 56 | \r |
| 57 | QTD_MAX_ERR = 3,\r |
| 58 | QTD_PID_OUTPUT = 0x00,\r |
| 59 | QTD_PID_INPUT = 0x01,\r |
| 60 | QTD_PID_SETUP = 0x02,\r |
| 61 | \r |
| 62 | QTD_STAT_DO_OUT = 0,\r |
| 63 | QTD_STAT_DO_SS = 0,\r |
| 64 | QTD_STAT_DO_PING = 0x01,\r |
| 65 | QTD_STAT_DO_CS = 0x02,\r |
| 66 | QTD_STAT_TRANS_ERR = 0x08,\r |
| 67 | QTD_STAT_BABBLE_ERR = 0x10,\r |
| 68 | QTD_STAT_BUFF_ERR = 0x20,\r |
| 69 | QTD_STAT_HALTED = 0x40,\r |
| 70 | QTD_STAT_ACTIVE = 0x80,\r |
| 71 | QTD_STAT_ERR_MASK = QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR,\r |
| 72 | \r |
| 73 | QTD_MAX_BUFFER = 4,\r |
| 74 | QTD_BUF_LEN = 4096,\r |
| 75 | QTD_BUF_MASK = 0x0FFF,\r |
| 76 | \r |
| 77 | QH_MICROFRAME_0 = 0x01,\r |
| 78 | QH_MICROFRAME_1 = 0x02,\r |
| 79 | QH_MICROFRAME_2 = 0x04,\r |
| 80 | QH_MICROFRAME_3 = 0x08,\r |
| 81 | QH_MICROFRAME_4 = 0x10,\r |
| 82 | QH_MICROFRAME_5 = 0x20,\r |
| 83 | QH_MICROFRAME_6 = 0x40,\r |
| 84 | QH_MICROFRAME_7 = 0x80,\r |
| 85 | \r |
| c52fa98c |
86 | USB_ERR_SHORT_PACKET = 0x200\r |
| 913cb9dc |
87 | };\r |
| 88 | \r |
| 89 | //\r |
| 90 | // Fill in the hardware link point: pass in a EHC_QH/QH_HW\r |
| 91 | // pointer to QH_LINK; A EHC_QTD/QTD_HW pointer to QTD_LINK\r |
| 92 | //\r |
| 93 | #define QH_LINK(Addr, Type, Term) \\r |
| 94 | ((UINT32) ((EHC_LOW_32BIT (Addr) & 0xFFFFFFE0) | (Type) | ((Term) ? 1 : 0)))\r |
| 95 | \r |
| 96 | #define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))\r |
| 97 | \r |
| 98 | //\r |
| 99 | // The defination of EHCI hardware used data structure for\r |
| 100 | // little endian architecture. The QTD and QH structures\r |
| 101 | // are required to be 32 bytes aligned. Don't add members\r |
| 102 | // to the head of the associated software strucuture.\r |
| 103 | //\r |
| 104 | #pragma pack(1)\r |
| 105 | typedef struct {\r |
| 106 | UINT32 NextQtd;\r |
| 107 | UINT32 AltNext;\r |
| 108 | \r |
| 109 | UINT32 Status : 8;\r |
| 110 | UINT32 Pid : 2;\r |
| 111 | UINT32 ErrCnt : 2;\r |
| 112 | UINT32 CurPage : 3;\r |
| 113 | UINT32 IOC : 1;\r |
| 114 | UINT32 TotalBytes : 15;\r |
| 115 | UINT32 DataToggle : 1;\r |
| 116 | \r |
| 117 | UINT32 Page[5];\r |
| 118 | UINT32 PageHigh[5];\r |
| 119 | } QTD_HW;\r |
| 120 | \r |
| 121 | typedef struct {\r |
| 122 | UINT32 HorizonLink;\r |
| 123 | //\r |
| 124 | // Endpoint capabilities/Characteristics DWord 1 and DWord 2\r |
| 125 | //\r |
| 126 | UINT32 DeviceAddr : 7;\r |
| 127 | UINT32 Inactive : 1;\r |
| 128 | UINT32 EpNum : 4;\r |
| 129 | UINT32 EpSpeed : 2;\r |
| 130 | UINT32 DtCtrl : 1;\r |
| 131 | UINT32 ReclaimHead : 1;\r |
| 132 | UINT32 MaxPacketLen : 11;\r |
| 133 | UINT32 CtrlEp : 1;\r |
| 134 | UINT32 NakReload : 4;\r |
| 135 | \r |
| 136 | UINT32 SMask : 8;\r |
| 137 | UINT32 CMask : 8;\r |
| 138 | UINT32 HubAddr : 7;\r |
| 139 | UINT32 PortNum : 7;\r |
| 140 | UINT32 Multiplier : 2;\r |
| 141 | \r |
| 142 | //\r |
| 143 | // Transaction execution overlay area\r |
| 144 | //\r |
| 145 | UINT32 CurQtd;\r |
| 146 | UINT32 NextQtd;\r |
| 147 | UINT32 AltQtd;\r |
| 148 | \r |
| 149 | UINT32 Status : 8;\r |
| 150 | UINT32 Pid : 2;\r |
| 151 | UINT32 ErrCnt : 2;\r |
| 152 | UINT32 CurPage : 3;\r |
| 153 | UINT32 IOC : 1;\r |
| 154 | UINT32 TotalBytes : 15;\r |
| 155 | UINT32 DataToggle : 1;\r |
| 156 | \r |
| 157 | UINT32 Page[5];\r |
| 158 | UINT32 PageHigh[5];\r |
| 159 | } QH_HW;\r |
| 160 | #pragma pack()\r |
| 161 | \r |
| 162 | \r |
| 163 | //\r |
| 164 | // Endpoint address and its capabilities\r |
| 165 | //\r |
| 166 | typedef struct _USB_ENDPOINT {\r |
| 167 | UINT8 DevAddr;\r |
| 168 | UINT8 EpAddr; // Endpoint address, no direction encoded in\r |
| 169 | EFI_USB_DATA_DIRECTION Direction;\r |
| 170 | UINT8 DevSpeed;\r |
| 171 | UINTN MaxPacket;\r |
| 172 | UINT8 HubAddr;\r |
| 173 | UINT8 HubPort;\r |
| 174 | UINT8 Toggle; // Data toggle, not used for control transfer\r |
| 175 | UINTN Type;\r |
| 176 | UINTN PollRate; // Polling interval used by EHCI\r |
| 177 | } USB_ENDPOINT;\r |
| 178 | \r |
| 179 | //\r |
| 180 | // Software QTD strcture, this is used to manage all the\r |
| 181 | // QTD generated from a URB. Don't add fields before QtdHw.\r |
| 182 | //\r |
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183 | struct _EHC_QTD {\r |
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184 | QTD_HW QtdHw;\r |
| 185 | UINT32 Signature;\r |
| 186 | LIST_ENTRY QtdList; // The list of QTDs to one end point\r |
| 187 | UINT8 *Data; // Buffer of the original data\r |
| 188 | UINTN DataLen; // Original amount of data in this QTD\r |
| c52fa98c |
189 | };\r |
| 913cb9dc |
190 | \r |
| 191 | //\r |
| 192 | // Software QH structure. All three different transaction types\r |
| 193 | // supported by UEFI USB, that is the control/bulk/interrupt\r |
| 194 | // transfers use the queue head and queue token strcuture.\r |
| 195 | //\r |
| 196 | // Interrupt QHs are linked to periodic frame list in the reversed\r |
| 197 | // 2^N tree. Each interrupt QH is linked to the list starting at\r |
| 198 | // frame 0. There is a dummy interrupt QH linked to each frame as\r |
| 199 | // a sentinental whose polling interval is 1. Synchronous interrupt\r |
| 200 | // transfer is linked after this dummy QH.\r |
| 201 | //\r |
| 202 | // For control/bulk transfer, only synchronous (in the sense of UEFI)\r |
| 203 | // transfer is supported. A dummy QH is linked to EHCI AsyncListAddr\r |
| 204 | // as the reclamation header. New transfer is inserted after this QH.\r |
| 205 | //\r |
| c52fa98c |
206 | struct _EHC_QH {\r |
| 913cb9dc |
207 | QH_HW QhHw;\r |
| 208 | UINT32 Signature;\r |
| 209 | EHC_QH *NextQh; // The queue head pointed to by horizontal link\r |
| 210 | LIST_ENTRY Qtds; // The list of QTDs to this queue head\r |
| 211 | UINTN Interval;\r |
| c52fa98c |
212 | };\r |
| 913cb9dc |
213 | \r |
| 214 | //\r |
| 215 | // URB (Usb Request Block) contains information for all kinds of\r |
| 216 | // usb requests.\r |
| 217 | //\r |
| c52fa98c |
218 | struct _URB {\r |
| 913cb9dc |
219 | UINT32 Signature;\r |
| 220 | LIST_ENTRY UrbList;\r |
| 221 | \r |
| 222 | //\r |
| 223 | // Transaction information\r |
| 224 | //\r |
| 225 | USB_ENDPOINT Ep;\r |
| 226 | EFI_USB_DEVICE_REQUEST *Request; // Control transfer only\r |
| 227 | VOID *RequestPhy; // Address of the mapped request\r |
| 228 | VOID *RequestMap;\r |
| 229 | VOID *Data;\r |
| 230 | UINTN DataLen;\r |
| 231 | VOID *DataPhy; // Address of the mapped user data\r |
| 232 | VOID *DataMap;\r |
| 233 | EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r |
| 234 | VOID *Context;\r |
| 235 | \r |
| 236 | //\r |
| 237 | // Schedule data\r |
| 238 | //\r |
| 239 | EHC_QH *Qh;\r |
| 240 | \r |
| 241 | //\r |
| 242 | // Transaction result\r |
| 243 | //\r |
| 244 | UINT32 Result;\r |
| 245 | UINTN Completed; // completed data length\r |
| 246 | UINT8 DataToggle;\r |
| c52fa98c |
247 | };\r |
| 913cb9dc |
248 | \r |
| 249 | \r |
| 250 | \r |
| 251 | /**\r |
| 252 | Create a single QTD to hold the data\r |
| 253 | \r |
| 254 | @param Ehc The EHCI device\r |
| 255 | @param Data Current data not associated with a QTD\r |
| 256 | @param DataLen The length of the data\r |
| 257 | @param PktId Packet ID to use in the QTD\r |
| 258 | @param Toggle Data toggle to use in the QTD\r |
| 259 | @param MaxPacket Maximu packet length of the endpoint\r |
| 260 | \r |
| 261 | @return Created QTD or NULL if failed to create one\r |
| 262 | \r |
| 263 | **/\r |
| 264 | EHC_QTD *\r |
| 265 | EhcCreateQtd (\r |
| 266 | IN USB2_HC_DEV *Ehc,\r |
| 267 | IN UINT8 *Data,\r |
| 268 | IN UINTN DataLen,\r |
| 269 | IN UINT8 PktId,\r |
| 270 | IN UINT8 Toggle,\r |
| 271 | IN UINTN MaxPacket\r |
| 272 | )\r |
| 273 | ;\r |
| 274 | \r |
| 275 | \r |
| 276 | \r |
| 277 | /**\r |
| 278 | Allocate and initialize a EHCI queue head\r |
| 279 | \r |
| 280 | @param Ehci The EHCI device\r |
| 281 | @param Ep The endpoint to create queue head for\r |
| 282 | \r |
| 283 | @return Created queue head or NULL if failed to create one\r |
| 284 | \r |
| 285 | **/\r |
| 286 | EHC_QH *\r |
| 287 | EhcCreateQh (\r |
| 288 | IN USB2_HC_DEV *Ehci,\r |
| 289 | IN USB_ENDPOINT *Ep\r |
| 290 | )\r |
| 291 | ;\r |
| 292 | \r |
| 293 | \r |
| 294 | /**\r |
| 295 | Free an allocated URB. It is possible for it to be partially inited.\r |
| 296 | \r |
| 297 | @param Ehc The EHCI device\r |
| 298 | @param Urb The URB to free\r |
| 299 | \r |
| 300 | @return None\r |
| 301 | \r |
| 302 | **/\r |
| 303 | VOID\r |
| 304 | EhcFreeUrb (\r |
| 305 | IN USB2_HC_DEV *Ehc,\r |
| 306 | IN URB *Urb\r |
| 307 | )\r |
| 308 | ;\r |
| 309 | \r |
| 310 | \r |
| 311 | /**\r |
| 312 | Create a new URB and its associated QTD\r |
| 313 | \r |
| 314 | @param Ehc The EHCI device\r |
| 315 | @param DevAddr The device address\r |
| 316 | @param EpAddr Endpoint addrress & its direction\r |
| 317 | @param DevSpeed The device speed\r |
| 318 | @param Toggle Initial data toggle to use\r |
| 319 | @param MaxPacket The max packet length of the endpoint\r |
| 320 | @param Hub The transaction translator to use\r |
| 321 | @param Type The transaction type\r |
| 322 | @param Request The standard USB request for control transfer\r |
| 323 | @param Data The user data to transfer\r |
| 324 | @param DataLen The length of data buffer\r |
| 325 | @param Callback The function to call when data is transferred\r |
| 326 | @param Context The context to the callback\r |
| 327 | @param Interval The interval for interrupt transfer\r |
| 328 | \r |
| 329 | @return Created URB or NULL\r |
| 330 | \r |
| 331 | **/\r |
| 332 | URB *\r |
| 333 | EhcCreateUrb (\r |
| 334 | IN USB2_HC_DEV *Ehc,\r |
| 335 | IN UINT8 DevAddr,\r |
| 336 | IN UINT8 EpAddr,\r |
| 337 | IN UINT8 DevSpeed,\r |
| 338 | IN UINT8 Toggle,\r |
| 339 | IN UINTN MaxPacket,\r |
| 340 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,\r |
| 341 | IN UINTN Type,\r |
| 342 | IN EFI_USB_DEVICE_REQUEST *Request,\r |
| 343 | IN VOID *Data,\r |
| 344 | IN UINTN DataLen,\r |
| 345 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r |
| 346 | IN VOID *Context,\r |
| 347 | IN UINTN Interval\r |
| 348 | )\r |
| 349 | ;\r |
| 350 | #endif\r |
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