]> git.proxmox.com Git - mirror_edk2.git/blame - MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.h
clean up the un-suitable ';' location when declaring the functions.
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / EhciUrb.h
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913cb9dc 1/** @file\r
2\r
78c2ffb5 3 This file contains URB request, each request is warpped in a\r
4 URB (Usb Request Block).\r
5\r
913cb9dc 6Copyright (c) 2007, Intel Corporation\r
7All rights reserved. This program and the accompanying materials\r
8are licensed and made available under the terms and conditions of the BSD License\r
9which accompanies this distribution. The full text of the license may be found at\r
10http://opensource.org/licenses/bsd-license.php\r
11\r
12THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
913cb9dc 15**/\r
16\r
17#ifndef _EFI_EHCI_URB_H_\r
18#define _EFI_EHCI_URB_H_\r
19\r
20\r
21typedef struct _EHC_QTD EHC_QTD;\r
22typedef struct _EHC_QH EHC_QH;\r
23typedef struct _URB URB;\r
24\r
78c2ffb5 25typedef enum {\r
913cb9dc 26 //\r
27 // Transfer types, used in URB to identify the transfer type\r
28 //\r
29 EHC_CTRL_TRANSFER = 0x01,\r
30 EHC_BULK_TRANSFER = 0x02,\r
31 EHC_INT_TRANSFER_SYNC = 0x04,\r
32 EHC_INT_TRANSFER_ASYNC = 0x08,\r
33\r
34 EHC_QTD_SIG = EFI_SIGNATURE_32 ('U', 'S', 'B', 'T'),\r
35 EHC_QH_SIG = EFI_SIGNATURE_32 ('U', 'S', 'B', 'H'),\r
36 EHC_URB_SIG = EFI_SIGNATURE_32 ('U', 'S', 'B', 'R'),\r
37\r
38 //\r
39 // Hardware related bit definitions\r
40 //\r
41 EHC_TYPE_ITD = 0x00,\r
42 EHC_TYPE_QH = 0x02,\r
43 EHC_TYPE_SITD = 0x04,\r
44 EHC_TYPE_FSTN = 0x06,\r
45\r
46 QH_NAK_RELOAD = 3,\r
47 QH_HSHBW_MULTI = 1,\r
48\r
49 QTD_MAX_ERR = 3,\r
50 QTD_PID_OUTPUT = 0x00,\r
51 QTD_PID_INPUT = 0x01,\r
52 QTD_PID_SETUP = 0x02,\r
53\r
54 QTD_STAT_DO_OUT = 0,\r
55 QTD_STAT_DO_SS = 0,\r
56 QTD_STAT_DO_PING = 0x01,\r
57 QTD_STAT_DO_CS = 0x02,\r
58 QTD_STAT_TRANS_ERR = 0x08,\r
59 QTD_STAT_BABBLE_ERR = 0x10,\r
60 QTD_STAT_BUFF_ERR = 0x20,\r
61 QTD_STAT_HALTED = 0x40,\r
62 QTD_STAT_ACTIVE = 0x80,\r
63 QTD_STAT_ERR_MASK = QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR,\r
64\r
65 QTD_MAX_BUFFER = 4,\r
66 QTD_BUF_LEN = 4096,\r
67 QTD_BUF_MASK = 0x0FFF,\r
68\r
69 QH_MICROFRAME_0 = 0x01,\r
70 QH_MICROFRAME_1 = 0x02,\r
71 QH_MICROFRAME_2 = 0x04,\r
72 QH_MICROFRAME_3 = 0x08,\r
73 QH_MICROFRAME_4 = 0x10,\r
74 QH_MICROFRAME_5 = 0x20,\r
75 QH_MICROFRAME_6 = 0x40,\r
76 QH_MICROFRAME_7 = 0x80,\r
77\r
c52fa98c 78 USB_ERR_SHORT_PACKET = 0x200\r
78c2ffb5 79}EHCI_URB_FLAG_VALUE;\r
913cb9dc 80\r
81//\r
82// Fill in the hardware link point: pass in a EHC_QH/QH_HW\r
83// pointer to QH_LINK; A EHC_QTD/QTD_HW pointer to QTD_LINK\r
84//\r
85#define QH_LINK(Addr, Type, Term) \\r
86 ((UINT32) ((EHC_LOW_32BIT (Addr) & 0xFFFFFFE0) | (Type) | ((Term) ? 1 : 0)))\r
87\r
88#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))\r
89\r
90//\r
91// The defination of EHCI hardware used data structure for\r
92// little endian architecture. The QTD and QH structures\r
93// are required to be 32 bytes aligned. Don't add members\r
94// to the head of the associated software strucuture.\r
95//\r
96#pragma pack(1)\r
97typedef struct {\r
98 UINT32 NextQtd;\r
99 UINT32 AltNext;\r
100\r
101 UINT32 Status : 8;\r
102 UINT32 Pid : 2;\r
103 UINT32 ErrCnt : 2;\r
104 UINT32 CurPage : 3;\r
105 UINT32 IOC : 1;\r
106 UINT32 TotalBytes : 15;\r
107 UINT32 DataToggle : 1;\r
108\r
109 UINT32 Page[5];\r
110 UINT32 PageHigh[5];\r
111} QTD_HW;\r
112\r
113typedef struct {\r
114 UINT32 HorizonLink;\r
115 //\r
116 // Endpoint capabilities/Characteristics DWord 1 and DWord 2\r
117 //\r
118 UINT32 DeviceAddr : 7;\r
119 UINT32 Inactive : 1;\r
120 UINT32 EpNum : 4;\r
121 UINT32 EpSpeed : 2;\r
122 UINT32 DtCtrl : 1;\r
123 UINT32 ReclaimHead : 1;\r
124 UINT32 MaxPacketLen : 11;\r
125 UINT32 CtrlEp : 1;\r
126 UINT32 NakReload : 4;\r
127\r
128 UINT32 SMask : 8;\r
129 UINT32 CMask : 8;\r
130 UINT32 HubAddr : 7;\r
131 UINT32 PortNum : 7;\r
132 UINT32 Multiplier : 2;\r
133\r
134 //\r
135 // Transaction execution overlay area\r
136 //\r
137 UINT32 CurQtd;\r
138 UINT32 NextQtd;\r
139 UINT32 AltQtd;\r
140\r
141 UINT32 Status : 8;\r
142 UINT32 Pid : 2;\r
143 UINT32 ErrCnt : 2;\r
144 UINT32 CurPage : 3;\r
145 UINT32 IOC : 1;\r
146 UINT32 TotalBytes : 15;\r
147 UINT32 DataToggle : 1;\r
148\r
149 UINT32 Page[5];\r
150 UINT32 PageHigh[5];\r
151} QH_HW;\r
152#pragma pack()\r
153\r
154\r
155//\r
156// Endpoint address and its capabilities\r
157//\r
158typedef struct _USB_ENDPOINT {\r
159 UINT8 DevAddr;\r
160 UINT8 EpAddr; // Endpoint address, no direction encoded in\r
161 EFI_USB_DATA_DIRECTION Direction;\r
162 UINT8 DevSpeed;\r
163 UINTN MaxPacket;\r
164 UINT8 HubAddr;\r
165 UINT8 HubPort;\r
166 UINT8 Toggle; // Data toggle, not used for control transfer\r
167 UINTN Type;\r
168 UINTN PollRate; // Polling interval used by EHCI\r
169} USB_ENDPOINT;\r
170\r
171//\r
172// Software QTD strcture, this is used to manage all the\r
173// QTD generated from a URB. Don't add fields before QtdHw.\r
174//\r
c52fa98c 175struct _EHC_QTD {\r
913cb9dc 176 QTD_HW QtdHw;\r
177 UINT32 Signature;\r
178 LIST_ENTRY QtdList; // The list of QTDs to one end point\r
179 UINT8 *Data; // Buffer of the original data\r
180 UINTN DataLen; // Original amount of data in this QTD\r
c52fa98c 181};\r
913cb9dc 182\r
183//\r
184// Software QH structure. All three different transaction types\r
185// supported by UEFI USB, that is the control/bulk/interrupt\r
186// transfers use the queue head and queue token strcuture.\r
187//\r
188// Interrupt QHs are linked to periodic frame list in the reversed\r
189// 2^N tree. Each interrupt QH is linked to the list starting at\r
190// frame 0. There is a dummy interrupt QH linked to each frame as\r
191// a sentinental whose polling interval is 1. Synchronous interrupt\r
192// transfer is linked after this dummy QH.\r
193//\r
194// For control/bulk transfer, only synchronous (in the sense of UEFI)\r
195// transfer is supported. A dummy QH is linked to EHCI AsyncListAddr\r
196// as the reclamation header. New transfer is inserted after this QH.\r
197//\r
c52fa98c 198struct _EHC_QH {\r
913cb9dc 199 QH_HW QhHw;\r
200 UINT32 Signature;\r
201 EHC_QH *NextQh; // The queue head pointed to by horizontal link\r
202 LIST_ENTRY Qtds; // The list of QTDs to this queue head\r
203 UINTN Interval;\r
c52fa98c 204};\r
913cb9dc 205\r
206//\r
207// URB (Usb Request Block) contains information for all kinds of\r
208// usb requests.\r
209//\r
c52fa98c 210struct _URB {\r
913cb9dc 211 UINT32 Signature;\r
212 LIST_ENTRY UrbList;\r
213\r
214 //\r
215 // Transaction information\r
216 //\r
217 USB_ENDPOINT Ep;\r
218 EFI_USB_DEVICE_REQUEST *Request; // Control transfer only\r
219 VOID *RequestPhy; // Address of the mapped request\r
220 VOID *RequestMap;\r
221 VOID *Data;\r
222 UINTN DataLen;\r
223 VOID *DataPhy; // Address of the mapped user data\r
224 VOID *DataMap;\r
225 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r
226 VOID *Context;\r
227\r
228 //\r
229 // Schedule data\r
230 //\r
231 EHC_QH *Qh;\r
232\r
233 //\r
234 // Transaction result\r
235 //\r
236 UINT32 Result;\r
237 UINTN Completed; // completed data length\r
238 UINT8 DataToggle;\r
c52fa98c 239};\r
913cb9dc 240\r
241\r
242\r
243/**\r
78c2ffb5 244 Create a single QTD to hold the data.\r
913cb9dc 245\r
78c2ffb5 246 @param Ehc The EHCI device.\r
247 @param Data Current data not associated with a QTD.\r
248 @param DataLen The length of the data.\r
249 @param PktId Packet ID to use in the QTD.\r
250 @param Toggle Data toggle to use in the QTD.\r
251 @param MaxPacket Maximu packet length of the endpoint.\r
913cb9dc 252\r
78c2ffb5 253 @return Created QTD or NULL if failed to create one.\r
913cb9dc 254\r
255**/\r
256EHC_QTD *\r
257EhcCreateQtd (\r
258 IN USB2_HC_DEV *Ehc,\r
259 IN UINT8 *Data,\r
260 IN UINTN DataLen,\r
261 IN UINT8 PktId,\r
262 IN UINT8 Toggle,\r
263 IN UINTN MaxPacket\r
ed66e1bc 264 );\r
913cb9dc 265\r
266\r
267\r
268/**\r
78c2ffb5 269 Allocate and initialize a EHCI queue head.\r
913cb9dc 270\r
78c2ffb5 271 @param Ehci The EHCI device.\r
272 @param Ep The endpoint to create queue head for.\r
913cb9dc 273\r
78c2ffb5 274 @return Created queue head or NULL if failed to create one.\r
913cb9dc 275\r
276**/\r
277EHC_QH *\r
278EhcCreateQh (\r
279 IN USB2_HC_DEV *Ehci,\r
280 IN USB_ENDPOINT *Ep\r
ed66e1bc 281 );\r
913cb9dc 282\r
283\r
284/**\r
285 Free an allocated URB. It is possible for it to be partially inited.\r
286\r
78c2ffb5 287 @param Ehc The EHCI device.\r
288 @param Urb The URB to free.\r
913cb9dc 289\r
78c2ffb5 290 @return None.\r
913cb9dc 291\r
292**/\r
293VOID\r
294EhcFreeUrb (\r
295 IN USB2_HC_DEV *Ehc,\r
296 IN URB *Urb\r
ed66e1bc 297 );\r
913cb9dc 298\r
299\r
300/**\r
78c2ffb5 301 Create a new URB and its associated QTD.\r
302\r
303 @param Ehc The EHCI device.\r
304 @param DevAddr The device address.\r
305 @param EpAddr Endpoint addrress & its direction.\r
306 @param DevSpeed The device speed.\r
307 @param Toggle Initial data toggle to use.\r
308 @param MaxPacket The max packet length of the endpoint.\r
309 @param Hub The transaction translator to use.\r
310 @param Type The transaction type.\r
311 @param Request The standard USB request for control transfer.\r
312 @param Data The user data to transfer.\r
313 @param DataLen The length of data buffer.\r
314 @param Callback The function to call when data is transferred.\r
315 @param Context The context to the callback.\r
316 @param Interval The interval for interrupt transfer.\r
317\r
318 @return Created URB or NULL.\r
913cb9dc 319\r
320**/\r
321URB *\r
322EhcCreateUrb (\r
323 IN USB2_HC_DEV *Ehc,\r
324 IN UINT8 DevAddr,\r
325 IN UINT8 EpAddr,\r
326 IN UINT8 DevSpeed,\r
327 IN UINT8 Toggle,\r
328 IN UINTN MaxPacket,\r
329 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,\r
330 IN UINTN Type,\r
331 IN EFI_USB_DEVICE_REQUEST *Request,\r
332 IN VOID *Data,\r
333 IN UINTN DataLen,\r
334 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
335 IN VOID *Context,\r
336 IN UINTN Interval\r
ed66e1bc 337 );\r
913cb9dc 338#endif\r