4b1bf81c |
1 | /** @file\r |
2 | Private Header file for Usb Host Controller PEIM\r |
3 | \r |
4 | Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r |
5 | \r |
6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions\r |
8 | of the BSD License which accompanies this distribution. The\r |
9 | full text of the license may be found at\r |
10 | http://opensource.org/licenses/bsd-license.php\r |
11 | \r |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
14 | \r |
15 | **/\r |
16 | \r |
17 | #ifndef _RECOVERY_EHC_H_\r |
18 | #define _RECOVERY_EHC_H_\r |
19 | \r |
20 | #include <PiPei.h>\r |
21 | \r |
22 | #include <Ppi/UsbController.h>\r |
23 | #include <Ppi/Usb2HostController.h>\r |
24 | \r |
25 | #include <Library/DebugLib.h>\r |
26 | #include <Library/PeimEntryPoint.h>\r |
27 | #include <Library/PeiServicesLib.h>\r |
28 | #include <Library/BaseMemoryLib.h>\r |
29 | #include <Library/TimerLib.h>\r |
30 | #include <Library/IoLib.h>\r |
31 | \r |
32 | typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV;\r |
33 | \r |
34 | #define EFI_LIST_ENTRY LIST_ENTRY\r |
35 | \r |
36 | #include "UsbHcMem.h"\r |
37 | #include "EhciReg.h"\r |
38 | #include "EhciUrb.h"\r |
39 | #include "EhciSched.h"\r |
40 | \r |
41 | #define EFI_USB_SPEED_FULL 0x0000\r |
42 | #define EFI_USB_SPEED_LOW 0x0001\r |
43 | #define EFI_USB_SPEED_HIGH 0x0002\r |
44 | \r |
45 | #define PAGESIZE 4096\r |
46 | \r |
47 | #define EHC_1_MICROSECOND 1\r |
48 | #define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)\r |
49 | #define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)\r |
50 | \r |
51 | //\r |
52 | // EHCI register operation timeout, set by experience\r |
53 | //\r |
54 | #define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)\r |
55 | #define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)\r |
56 | \r |
57 | \r |
58 | //\r |
59 | // Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]\r |
60 | //\r |
61 | #define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)\r |
62 | \r |
63 | //\r |
64 | // Sync and Async transfer polling interval, set by experience, \r |
65 | // and the unit of Async is 100us, means 50ms as interval.\r |
66 | //\r |
67 | #define EHC_SYNC_POLL_INTERVAL (6 * EHC_1_MILLISECOND)\r |
68 | \r |
69 | #define EHC_ASYNC_POLL_INTERVAL (50 * 10000U)\r |
70 | \r |
71 | //\r |
72 | //Iterate through the doule linked list. NOT delete safe\r |
73 | //\r |
74 | #define EFI_LIST_FOR_EACH(Entry, ListHead) \\r |
75 | for(Entry = (ListHead)->ForwardLink; Entry != (ListHead); Entry = Entry->ForwardLink)\r |
76 | \r |
77 | //\r |
78 | //Iterate through the doule linked list. This is delete-safe.\r |
79 | //Don't touch NextEntry\r |
80 | //\r |
81 | #define EFI_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead) \\r |
82 | for(Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\\r |
83 | Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink)\r |
84 | \r |
85 | #define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)\r |
86 | \r |
87 | \r |
88 | #define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r |
89 | #define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r |
90 | #define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r |
91 | \r |
92 | #define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \\r |
93 | (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))\r |
94 | \r |
95 | #define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i')\r |
96 | \r |
97 | struct _PEI_USB2_HC_DEV {\r |
98 | UINTN Signature;\r |
99 | PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;\r |
100 | EFI_PEI_PPI_DESCRIPTOR PpiDescriptor; \r |
101 | UINT32 UsbHostControllerBaseAddress;\r |
102 | PEI_URB *Urb;\r |
103 | USBHC_MEM_POOL *MemPool;\r |
104 | \r |
105 | //\r |
106 | // Schedule data shared between asynchronous and periodic\r |
107 | // transfers:\r |
108 | // ShortReadStop, as its name indicates, is used to terminate\r |
109 | // the short read except the control transfer. EHCI follows\r |
110 | // the alternative next QTD point when a short read happens.\r |
111 | // For control transfer, even the short read happens, try the\r |
112 | // status stage.\r |
113 | //\r |
114 | PEI_EHC_QTD *ShortReadStop;\r |
115 | EFI_EVENT PollTimer;\r |
116 | \r |
117 | //\r |
118 | // Asynchronous(bulk and control) transfer schedule data: \r |
119 | // ReclaimHead is used as the head of the asynchronous transfer\r |
120 | // list. It acts as the reclamation header. \r |
121 | //\r |
122 | PEI_EHC_QH *ReclaimHead;\r |
123 | \r |
124 | //\r |
125 | // Peroidic (interrupt) transfer schedule data:\r |
126 | //\r |
127 | VOID *PeriodFrame; // Mapped as common buffer \r |
128 | VOID *PeriodFrameHost;\r |
129 | VOID *PeriodFrameMap;\r |
130 | \r |
131 | PEI_EHC_QH *PeriodOne;\r |
132 | EFI_LIST_ENTRY AsyncIntTransfers;\r |
133 | \r |
134 | //\r |
135 | // EHCI configuration data\r |
136 | //\r |
137 | UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET\r |
138 | UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS\r |
139 | UINT32 CapLen; // Capability length\r |
140 | UINT32 High32bitAddr;\r |
141 | };\r |
142 | \r |
143 | #define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a) CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)\r |
144 | \r |
145 | /**\r |
146 | @param EhcDev EHCI Device.\r |
147 | \r |
148 | @retval EFI_SUCCESS EHCI successfully initialized.\r |
149 | @retval EFI_ABORTED EHCI was failed to be initialized.\r |
150 | \r |
151 | **/\r |
152 | EFI_STATUS\r |
153 | InitializeUsbHC (\r |
154 | IN PEI_USB2_HC_DEV *EhcDev \r |
155 | );\r |
156 | \r |
157 | /**\r |
158 | Initialize the memory management pool for the host controller.\r |
159 | \r |
160 | @param Ehc The EHCI device.\r |
161 | @param Check4G Whether the host controller requires allocated memory \r |
162 | from one 4G address space.\r |
163 | @param Which4G The 4G memory area each memory allocated should be from.\r |
164 | \r |
165 | @retval EFI_SUCCESS The memory pool is initialized.\r |
166 | @retval EFI_OUT_OF_RESOURCE Fail to init the memory pool.\r |
167 | \r |
168 | **/\r |
169 | USBHC_MEM_POOL *\r |
170 | UsbHcInitMemPool (\r |
171 | IN PEI_USB2_HC_DEV *Ehc,\r |
172 | IN BOOLEAN Check4G,\r |
173 | IN UINT32 Which4G\r |
174 | )\r |
175 | ;\r |
176 | \r |
177 | /**\r |
178 | Release the memory management pool.\r |
179 | \r |
180 | @param Pool The USB memory pool to free.\r |
181 | \r |
182 | @retval EFI_DEVICE_ERROR Fail to free the memory pool.\r |
183 | @retval EFI_SUCCESS The memory pool is freed.\r |
184 | \r |
185 | **/\r |
186 | EFI_STATUS\r |
187 | UsbHcFreeMemPool (\r |
188 | IN USBHC_MEM_POOL *Pool\r |
189 | )\r |
190 | ;\r |
191 | \r |
192 | /**\r |
193 | Allocate some memory from the host controller's memory pool\r |
194 | which can be used to communicate with host controller.\r |
195 | \r |
196 | @param Ehc The EHCI device.\r |
197 | @param Pool The host controller's memory pool.\r |
198 | @param Size Size of the memory to allocate.\r |
199 | \r |
200 | @return The allocated memory or NULL.\r |
201 | \r |
202 | **/\r |
203 | VOID *\r |
204 | UsbHcAllocateMem (\r |
205 | IN PEI_USB2_HC_DEV *Ehc,\r |
206 | IN USBHC_MEM_POOL *Pool,\r |
207 | IN UINTN Size\r |
208 | )\r |
209 | ;\r |
210 | \r |
211 | /**\r |
212 | Free the allocated memory back to the memory pool.\r |
213 | \r |
214 | @param Pool The memory pool of the host controller.\r |
215 | @param Mem The memory to free.\r |
216 | @param Size The size of the memory to free.\r |
217 | \r |
218 | **/\r |
219 | VOID\r |
220 | UsbHcFreeMem (\r |
221 | IN USBHC_MEM_POOL *Pool,\r |
222 | IN VOID *Mem,\r |
223 | IN UINTN Size\r |
224 | )\r |
225 | ;\r |
226 | \r |
227 | #endif\r |