MdeModulePkg EhciPei: Minor refinement about IOMMU
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciPei / EhcPeim.h
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4b1bf81c 1/** @file\r
2Private Header file for Usb Host Controller PEIM\r
3\r
2c656af0 4Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>\r
4b1bf81c 5 \r
6This program and the accompanying materials\r
7are licensed and made available under the terms and conditions\r
8of the BSD License which accompanies this distribution. The\r
9full text of the license may be found at\r
10http://opensource.org/licenses/bsd-license.php\r
11\r
12THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17#ifndef _RECOVERY_EHC_H_\r
18#define _RECOVERY_EHC_H_\r
19\r
20#include <PiPei.h>\r
21\r
22#include <Ppi/UsbController.h>\r
23#include <Ppi/Usb2HostController.h>\r
2c656af0
SZ
24#include <Ppi/IoMmu.h>\r
25#include <Ppi/EndOfPeiPhase.h>\r
4b1bf81c 26\r
27#include <Library/DebugLib.h>\r
28#include <Library/PeimEntryPoint.h>\r
29#include <Library/PeiServicesLib.h>\r
30#include <Library/BaseMemoryLib.h>\r
31#include <Library/TimerLib.h>\r
32#include <Library/IoLib.h>\r
33\r
34typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV;\r
35\r
36#define EFI_LIST_ENTRY LIST_ENTRY\r
37\r
38#include "UsbHcMem.h"\r
39#include "EhciReg.h"\r
40#include "EhciUrb.h"\r
41#include "EhciSched.h"\r
42\r
43#define EFI_USB_SPEED_FULL 0x0000\r
44#define EFI_USB_SPEED_LOW 0x0001\r
45#define EFI_USB_SPEED_HIGH 0x0002\r
46\r
47#define PAGESIZE 4096\r
48\r
49#define EHC_1_MICROSECOND 1\r
50#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)\r
51#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)\r
52\r
53//\r
54// EHCI register operation timeout, set by experience\r
55//\r
56#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)\r
57#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)\r
58\r
59\r
60//\r
61// Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]\r
62//\r
63#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)\r
64\r
65//\r
bfe37a77 66// Sync transfer polling interval, set by experience.\r
4b1bf81c 67//\r
68#define EHC_SYNC_POLL_INTERVAL (6 * EHC_1_MILLISECOND)\r
69\r
4b1bf81c 70//\r
ed356b9e 71//Iterate through the double linked list. NOT delete safe\r
4b1bf81c 72//\r
73#define EFI_LIST_FOR_EACH(Entry, ListHead) \\r
74 for(Entry = (ListHead)->ForwardLink; Entry != (ListHead); Entry = Entry->ForwardLink)\r
75\r
76//\r
ed356b9e 77//Iterate through the double linked list. This is delete-safe.\r
4b1bf81c 78//Don't touch NextEntry\r
79//\r
80#define EFI_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead) \\r
81 for(Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\\r
82 Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink)\r
83\r
84#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)\r
85\r
86\r
87#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r
88#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r
89#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
90\r
91#define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \\r
92 (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))\r
93\r
94#define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i')\r
95\r
96struct _PEI_USB2_HC_DEV {\r
97 UINTN Signature;\r
98 PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;\r
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99 EDKII_IOMMU_PPI *IoMmu;\r
100 EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;\r
101 //\r
c34a5aab 102 // EndOfPei callback is used to stop the EHC DMA operation\r
2c656af0
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103 // after exit PEI phase.\r
104 //\r
105 EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;\r
4b1bf81c 106 UINT32 UsbHostControllerBaseAddress;\r
107 PEI_URB *Urb;\r
108 USBHC_MEM_POOL *MemPool;\r
109\r
110 //\r
111 // Schedule data shared between asynchronous and periodic\r
112 // transfers:\r
113 // ShortReadStop, as its name indicates, is used to terminate\r
114 // the short read except the control transfer. EHCI follows\r
115 // the alternative next QTD point when a short read happens.\r
116 // For control transfer, even the short read happens, try the\r
117 // status stage.\r
118 //\r
119 PEI_EHC_QTD *ShortReadStop;\r
120 EFI_EVENT PollTimer;\r
121 \r
122 //\r
123 // Asynchronous(bulk and control) transfer schedule data: \r
124 // ReclaimHead is used as the head of the asynchronous transfer\r
125 // list. It acts as the reclamation header. \r
126 //\r
127 PEI_EHC_QH *ReclaimHead;\r
128 \r
129 //\r
ed356b9e 130 // Periodic (interrupt) transfer schedule data:\r
4b1bf81c 131 //\r
132 VOID *PeriodFrame; // Mapped as common buffer \r
4b1bf81c 133 VOID *PeriodFrameMap;\r
134 \r
135 PEI_EHC_QH *PeriodOne;\r
136 EFI_LIST_ENTRY AsyncIntTransfers;\r
137\r
138 //\r
139 // EHCI configuration data\r
140 //\r
141 UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET\r
142 UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS\r
143 UINT32 CapLen; // Capability length\r
144 UINT32 High32bitAddr;\r
145};\r
146\r
147#define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a) CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)\r
2c656af0 148#define PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_USB2_HC_DEV, EndOfPeiNotifyList, USB2_HC_DEV_SIGNATURE)\r
4b1bf81c 149\r
150/**\r
151 @param EhcDev EHCI Device.\r
152\r
153 @retval EFI_SUCCESS EHCI successfully initialized.\r
154 @retval EFI_ABORTED EHCI was failed to be initialized.\r
155\r
156**/\r
157EFI_STATUS\r
158InitializeUsbHC (\r
159 IN PEI_USB2_HC_DEV *EhcDev \r
160 );\r
161\r
162/**\r
163 Initialize the memory management pool for the host controller.\r
164 \r
165 @param Ehc The EHCI device.\r
166 @param Check4G Whether the host controller requires allocated memory \r
167 from one 4G address space.\r
168 @param Which4G The 4G memory area each memory allocated should be from.\r
169\r
170 @retval EFI_SUCCESS The memory pool is initialized.\r
171 @retval EFI_OUT_OF_RESOURCE Fail to init the memory pool.\r
172\r
173**/\r
174USBHC_MEM_POOL *\r
175UsbHcInitMemPool (\r
176 IN PEI_USB2_HC_DEV *Ehc,\r
177 IN BOOLEAN Check4G,\r
178 IN UINT32 Which4G\r
179 )\r
180;\r
181 \r
182/**\r
183 Release the memory management pool.\r
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184\r
185 @param Ehc The EHCI device.\r
4b1bf81c 186 @param Pool The USB memory pool to free.\r
187\r
188 @retval EFI_DEVICE_ERROR Fail to free the memory pool.\r
189 @retval EFI_SUCCESS The memory pool is freed.\r
190\r
191**/\r
192EFI_STATUS\r
193UsbHcFreeMemPool (\r
2c656af0 194 IN PEI_USB2_HC_DEV *Ehc,\r
4b1bf81c 195 IN USBHC_MEM_POOL *Pool\r
196 )\r
197;\r
198\r
199/**\r
200 Allocate some memory from the host controller's memory pool\r
201 which can be used to communicate with host controller.\r
202 \r
203 @param Ehc The EHCI device.\r
204 @param Pool The host controller's memory pool.\r
205 @param Size Size of the memory to allocate.\r
206\r
207 @return The allocated memory or NULL.\r
208\r
209**/\r
210VOID *\r
211UsbHcAllocateMem (\r
212 IN PEI_USB2_HC_DEV *Ehc,\r
213 IN USBHC_MEM_POOL *Pool,\r
214 IN UINTN Size\r
215 )\r
216;\r
217\r
218/**\r
219 Free the allocated memory back to the memory pool.\r
220\r
2c656af0 221 @param Ehc The EHCI device.\r
4b1bf81c 222 @param Pool The memory pool of the host controller.\r
223 @param Mem The memory to free.\r
224 @param Size The size of the memory to free.\r
225\r
226**/\r
227VOID\r
228UsbHcFreeMem (\r
2c656af0 229 IN PEI_USB2_HC_DEV *Ehc,\r
4b1bf81c 230 IN USBHC_MEM_POOL *Pool,\r
231 IN VOID *Mem,\r
232 IN UINTN Size\r
233 )\r
234;\r
235\r
2c656af0
SZ
236/**\r
237 Provides the controller-specific addresses required to access system memory from a\r
238 DMA bus master.\r
239\r
240 @param IoMmu Pointer to IOMMU PPI.\r
241 @param Operation Indicates if the bus master is going to read or write to system memory.\r
242 @param HostAddress The system memory address to map to the PCI controller.\r
243 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
244 that were mapped.\r
245 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
246 access the hosts HostAddress.\r
247 @param Mapping A resulting value to pass to Unmap().\r
248\r
249 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
250 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
251 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
252 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
253 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
254\r
255**/\r
256EFI_STATUS\r
257IoMmuMap (\r
258 IN EDKII_IOMMU_PPI *IoMmu,\r
259 IN EDKII_IOMMU_OPERATION Operation,\r
260 IN VOID *HostAddress,\r
261 IN OUT UINTN *NumberOfBytes,\r
262 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
263 OUT VOID **Mapping\r
264 );\r
265\r
266/**\r
267 Completes the Map() operation and releases any corresponding resources.\r
268\r
269 @param IoMmu Pointer to IOMMU PPI.\r
270 @param Mapping The mapping value returned from Map().\r
271\r
272**/\r
273VOID\r
274IoMmuUnmap (\r
275 IN EDKII_IOMMU_PPI *IoMmu,\r
276 IN VOID *Mapping\r
277 );\r
278\r
279/**\r
280 Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r
281 OperationBusMasterCommonBuffer64 mapping.\r
282\r
283 @param IoMmu Pointer to IOMMU PPI.\r
284 @param Pages The number of pages to allocate.\r
285 @param HostAddress A pointer to store the base system memory address of the\r
286 allocated range.\r
287 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
288 access the hosts HostAddress.\r
289 @param Mapping A resulting value to pass to Unmap().\r
290\r
291 @retval EFI_SUCCESS The requested memory pages were allocated.\r
292 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
293 MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
294 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
295 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
296\r
297**/\r
298EFI_STATUS\r
299IoMmuAllocateBuffer (\r
300 IN EDKII_IOMMU_PPI *IoMmu,\r
301 IN UINTN Pages,\r
302 OUT VOID **HostAddress,\r
303 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
304 OUT VOID **Mapping\r
305 );\r
306\r
307/**\r
308 Frees memory that was allocated with AllocateBuffer().\r
309\r
310 @param IoMmu Pointer to IOMMU PPI.\r
311 @param Pages The number of pages to free.\r
312 @param HostAddress The base system memory address of the allocated range.\r
313 @param Mapping The mapping value returned from Map().\r
314\r
315**/\r
316VOID\r
317IoMmuFreeBuffer (\r
318 IN EDKII_IOMMU_PPI *IoMmu,\r
319 IN UINTN Pages,\r
320 IN VOID *HostAddress,\r
321 IN VOID *Mapping\r
322 );\r
323\r
324/**\r
325 Initialize IOMMU.\r
326\r
327 @param IoMmu Pointer to pointer to IOMMU PPI.\r
328\r
329**/\r
330VOID\r
331IoMmuInit (\r
332 OUT EDKII_IOMMU_PPI **IoMmu\r
333 );\r
334\r
4b1bf81c 335#endif\r