MdeModulePkg: Clean up source files

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciPei / EhcPeim.h

/** @file\r
Private Header file for Usb Host Controller PEIM\r
\r
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
of the BSD License which accompanies this distribution.  The\r
full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _RECOVERY_EHC_H_\r
#define _RECOVERY_EHC_H_\r
\r
#include <PiPei.h>\r
\r
#include <Ppi/UsbController.h>\r
#include <Ppi/Usb2HostController.h>\r
#include <Ppi/IoMmu.h>\r
#include <Ppi/EndOfPeiPhase.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/TimerLib.h>\r
#include <Library/IoLib.h>\r
\r
typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV;\r
\r
#define EFI_LIST_ENTRY LIST_ENTRY\r
\r
#include "UsbHcMem.h"\r
#include "EhciReg.h"\r
#include "EhciUrb.h"\r
#include "EhciSched.h"\r
\r
#define EFI_USB_SPEED_FULL 0x0000\r
#define EFI_USB_SPEED_LOW  0x0001\r
#define EFI_USB_SPEED_HIGH 0x0002\r
\r
#define PAGESIZE           4096\r
\r
#define EHC_1_MICROSECOND            1\r
#define EHC_1_MILLISECOND            (1000 * EHC_1_MICROSECOND)\r
#define EHC_1_SECOND                 (1000 * EHC_1_MILLISECOND)\r
\r
//\r
// EHCI register operation timeout, set by experience\r
//\r
#define EHC_RESET_TIMEOUT            (1 * EHC_1_SECOND)\r
#define EHC_GENERIC_TIMEOUT          (10 * EHC_1_MILLISECOND)\r
\r
\r
//\r
// Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]\r
//\r
#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)\r
\r
//\r
// Sync transfer polling interval, set by experience.\r
//\r
#define EHC_SYNC_POLL_INTERVAL       (6 * EHC_1_MILLISECOND)\r
\r
//\r
//Iterate through the double linked list. NOT delete safe\r
//\r
#define EFI_LIST_FOR_EACH(Entry, ListHead)    \\r
  for(Entry = (ListHead)->ForwardLink; Entry != (ListHead); Entry = Entry->ForwardLink)\r
\r
//\r
//Iterate through the double linked list. This is delete-safe.\r
//Don't touch NextEntry\r
//\r
#define EFI_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead)            \\r
  for(Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\\r
      Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink)\r
\r
#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)\r
\r
\r
#define EHC_LOW_32BIT(Addr64)     ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r
#define EHC_HIGH_32BIT(Addr64)    ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r
#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
\r
#define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \\r
          (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))\r
\r
#define USB2_HC_DEV_SIGNATURE  SIGNATURE_32 ('e', 'h', 'c', 'i')\r
\r
struct _PEI_USB2_HC_DEV {\r
  UINTN                               Signature;\r
  PEI_USB2_HOST_CONTROLLER_PPI        Usb2HostControllerPpi;\r
  EDKII_IOMMU_PPI                     *IoMmu;\r
  EFI_PEI_PPI_DESCRIPTOR              PpiDescriptor;\r
  //\r
  // EndOfPei callback is used to stop the EHC DMA operation\r
  // after exit PEI phase.\r
  //\r
  EFI_PEI_NOTIFY_DESCRIPTOR           EndOfPeiNotifyList;\r
  UINT32                              UsbHostControllerBaseAddress;\r
  PEI_URB                             *Urb;\r
  USBHC_MEM_POOL                      *MemPool;\r
\r
  //\r
  // Schedule data shared between asynchronous and periodic\r
  // transfers:\r
  // ShortReadStop, as its name indicates, is used to terminate\r
  // the short read except the control transfer. EHCI follows\r
  // the alternative next QTD point when a short read happens.\r
  // For control transfer, even the short read happens, try the\r
  // status stage.\r
  //\r
  PEI_EHC_QTD                         *ShortReadStop;\r
  EFI_EVENT                           PollTimer;\r
\r
  //\r
  // Asynchronous(bulk and control) transfer schedule data:\r
  // ReclaimHead is used as the head of the asynchronous transfer\r
  // list. It acts as the reclamation header.\r
  //\r
  PEI_EHC_QH                          *ReclaimHead;\r
\r
  //\r
  // Periodic (interrupt) transfer schedule data:\r
  //\r
  VOID                                *PeriodFrame;     // Mapped as common buffer\r
  VOID                                *PeriodFrameMap;\r
\r
  PEI_EHC_QH                          *PeriodOne;\r
  EFI_LIST_ENTRY                      AsyncIntTransfers;\r
\r
  //\r
  // EHCI configuration data\r
  //\r
  UINT32                              HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET\r
  UINT32                              HcCapParams;    // Cache of HC capability parameter, HCCPARAMS\r
  UINT32                              CapLen;         // Capability length\r
  UINT32                              High32bitAddr;\r
};\r
\r
#define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a)  CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)\r
#define PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_USB2_HC_DEV, EndOfPeiNotifyList, USB2_HC_DEV_SIGNATURE)\r
\r
/**\r
  @param  EhcDev                 EHCI Device.\r
\r
  @retval EFI_SUCCESS            EHCI successfully initialized.\r
  @retval EFI_ABORTED            EHCI was failed to be initialized.\r
\r
**/\r
EFI_STATUS\r
InitializeUsbHC (\r
  IN PEI_USB2_HC_DEV      *EhcDev\r
  );\r
\r
/**\r
  Initialize the memory management pool for the host controller.\r
\r
  @param  Ehc                   The EHCI device.\r
  @param  Check4G               Whether the host controller requires allocated memory\r
                                from one 4G address space.\r
  @param  Which4G               The 4G memory area each memory allocated should be from.\r
\r
  @retval EFI_SUCCESS           The memory pool is initialized.\r
  @retval EFI_OUT_OF_RESOURCE   Fail to init the memory pool.\r
\r
**/\r
USBHC_MEM_POOL *\r
UsbHcInitMemPool (\r
  IN PEI_USB2_HC_DEV      *Ehc,\r
  IN BOOLEAN              Check4G,\r
  IN UINT32               Which4G\r
  )\r
;\r
\r
/**\r
  Release the memory management pool.\r
\r
  @param  Ehc                   The EHCI device.\r
  @param  Pool                  The USB memory pool to free.\r
\r
  @retval EFI_DEVICE_ERROR      Fail to free the memory pool.\r
  @retval EFI_SUCCESS           The memory pool is freed.\r
\r
**/\r
EFI_STATUS\r
UsbHcFreeMemPool (\r
  IN PEI_USB2_HC_DEV      *Ehc,\r
  IN USBHC_MEM_POOL       *Pool\r
  )\r
;\r
\r
/**\r
  Allocate some memory from the host controller's memory pool\r
  which can be used to communicate with host controller.\r
\r
  @param  Ehc       The EHCI device.\r
  @param  Pool      The host controller's memory pool.\r
  @param  Size      Size of the memory to allocate.\r
\r
  @return The allocated memory or NULL.\r
\r
**/\r
VOID *\r
UsbHcAllocateMem (\r
  IN PEI_USB2_HC_DEV      *Ehc,\r
  IN  USBHC_MEM_POOL      *Pool,\r
  IN  UINTN               Size\r
  )\r
;\r
\r
/**\r
  Free the allocated memory back to the memory pool.\r
\r
  @param  Ehc            The EHCI device.\r
  @param  Pool           The memory pool of the host controller.\r
  @param  Mem            The memory to free.\r
  @param  Size           The size of the memory to free.\r
\r
**/\r
VOID\r
UsbHcFreeMem (\r
  IN PEI_USB2_HC_DEV      *Ehc,\r
  IN USBHC_MEM_POOL       *Pool,\r
  IN VOID                 *Mem,\r
  IN UINTN                Size\r
  )\r
;\r
\r
/**\r
  Provides the controller-specific addresses required to access system memory from a\r
  DMA bus master.\r
\r
  @param IoMmu                  Pointer to IOMMU PPI.\r
  @param Operation              Indicates if the bus master is going to read or write to system memory.\r
  @param HostAddress            The system memory address to map to the PCI controller.\r
  @param NumberOfBytes          On input the number of bytes to map. On output the number of bytes\r
                                that were mapped.\r
  @param DeviceAddress          The resulting map address for the bus master PCI controller to use to\r
                                access the hosts HostAddress.\r
  @param Mapping                A resulting value to pass to Unmap().\r
\r
  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.\r
  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.\r
\r
**/\r
EFI_STATUS\r
IoMmuMap (\r
  IN EDKII_IOMMU_PPI        *IoMmu,\r
  IN EDKII_IOMMU_OPERATION  Operation,\r
  IN VOID                   *HostAddress,\r
  IN OUT UINTN              *NumberOfBytes,\r
  OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,\r
  OUT VOID                  **Mapping\r
  );\r
\r
/**\r
  Completes the Map() operation and releases any corresponding resources.\r
\r
  @param IoMmu              Pointer to IOMMU PPI.\r
  @param Mapping            The mapping value returned from Map().\r
\r
**/\r
VOID\r
IoMmuUnmap (\r
  IN EDKII_IOMMU_PPI        *IoMmu,\r
  IN VOID                  *Mapping\r
  );\r
\r
/**\r
  Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r
  OperationBusMasterCommonBuffer64 mapping.\r
\r
  @param IoMmu                  Pointer to IOMMU PPI.\r
  @param Pages                  The number of pages to allocate.\r
  @param HostAddress            A pointer to store the base system memory address of the\r
                                allocated range.\r
  @param DeviceAddress          The resulting map address for the bus master PCI controller to use to\r
                                access the hosts HostAddress.\r
  @param Mapping                A resulting value to pass to Unmap().\r
\r
  @retval EFI_SUCCESS           The requested memory pages were allocated.\r
  @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are\r
                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.\r
\r
**/\r
EFI_STATUS\r
IoMmuAllocateBuffer (\r
  IN EDKII_IOMMU_PPI        *IoMmu,\r
  IN UINTN                  Pages,\r
  OUT VOID                  **HostAddress,\r
  OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,\r
  OUT VOID                  **Mapping\r
  );\r
\r
/**\r
  Frees memory that was allocated with AllocateBuffer().\r
\r
  @param IoMmu              Pointer to IOMMU PPI.\r
  @param Pages              The number of pages to free.\r
  @param HostAddress        The base system memory address of the allocated range.\r
  @param Mapping            The mapping value returned from Map().\r
\r
**/\r
VOID\r
IoMmuFreeBuffer (\r
  IN EDKII_IOMMU_PPI        *IoMmu,\r
  IN UINTN                  Pages,\r
  IN VOID                   *HostAddress,\r
  IN VOID                   *Mapping\r
  );\r
\r
/**\r
  Initialize IOMMU.\r
\r
  @param IoMmu              Pointer to pointer to IOMMU PPI.\r
\r
**/\r
VOID\r
IoMmuInit (\r
  OUT EDKII_IOMMU_PPI       **IoMmu\r
  );\r
\r
#endif\r