[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciPei / EhciUrb.h

/** @file\r
Private Header file for Usb Host Controller PEIM\r
\r
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
of the BSD License which accompanies this distribution.  The\r
full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _EFI_EHCI_URB_H_\r
#define _EFI_EHCI_URB_H_\r
\r
typedef struct _PEI_EHC_QTD PEI_EHC_QTD;\r
typedef struct _PEI_EHC_QH  PEI_EHC_QH;\r
typedef struct _PEI_URB     PEI_URB;\r
\r
#define EHC_CTRL_TRANSFER       0x01\r
#define EHC_BULK_TRANSFER       0x02\r
#define EHC_INT_TRANSFER_SYNC   0x04\r
#define EHC_INT_TRANSFER_ASYNC  0x08\r
\r
#define EHC_QTD_SIG             SIGNATURE_32 ('U', 'S', 'B', 'T')\r
#define EHC_QH_SIG              SIGNATURE_32 ('U', 'S', 'B', 'H')\r
#define EHC_URB_SIG             SIGNATURE_32 ('U', 'S', 'B', 'R')\r
\r
//\r
// Hardware related bit definitions\r
//\r
#define EHC_TYPE_ITD            0x00\r
#define EHC_TYPE_QH             0x02\r
#define EHC_TYPE_SITD           0x04\r
#define EHC_TYPE_FSTN           0x06\r
\r
#define QH_NAK_RELOAD           3\r
#define QH_HSHBW_MULTI          1\r
\r
#define QTD_MAX_ERR             3\r
#define QTD_PID_OUTPUT          0x00\r
#define QTD_PID_INPUT           0x01\r
#define QTD_PID_SETUP           0x02\r
\r
#define QTD_STAT_DO_OUT         0\r
#define QTD_STAT_DO_SS          0\r
#define QTD_STAT_DO_PING        0x01\r
#define QTD_STAT_DO_CS          0x02\r
#define QTD_STAT_TRANS_ERR      0x08\r
#define QTD_STAT_BABBLE_ERR     0x10\r
#define QTD_STAT_BUFF_ERR       0x20\r
#define QTD_STAT_HALTED         0x40\r
#define QTD_STAT_ACTIVE         0x80\r
#define QTD_STAT_ERR_MASK       (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)\r
\r
#define QTD_MAX_BUFFER          4\r
#define QTD_BUF_LEN             4096\r
#define QTD_BUF_MASK            0x0FFF\r
\r
#define QH_MICROFRAME_0         0x01\r
#define QH_MICROFRAME_1         0x02\r
#define QH_MICROFRAME_2         0x04\r
#define QH_MICROFRAME_3         0x08\r
#define QH_MICROFRAME_4         0x10\r
#define QH_MICROFRAME_5         0x20\r
#define QH_MICROFRAME_6         0x40\r
#define QH_MICROFRAME_7         0x80\r
\r
#define USB_ERR_SHORT_PACKET    0x200\r
\r
//\r
// Fill in the hardware link point: pass in a EHC_QH/QH_HW\r
// pointer to QH_LINK; A EHC_QTD/QTD_HW pointer to QTD_LINK\r
//\r
#define QH_LINK(Addr, Type, Term) \\r
          ((UINT32) ((EHC_LOW_32BIT (Addr) & 0xFFFFFFE0) | (Type) | ((Term) ? 1 : 0)))\r
\r
#define QTD_LINK(Addr, Term)      QH_LINK((Addr), 0, (Term))\r
\r
//\r
// The defination of EHCI hardware used data structure for\r
// little endian architecture. The QTD and QH structures\r
// are required to be 32 bytes aligned. Don't add members\r
// to the head of the associated software strucuture.\r
//\r
#pragma pack(1)\r
typedef struct {\r
  UINT32                  NextQtd;\r
  UINT32                  AltNext;\r
\r
  UINT32                  Status       : 8;\r
  UINT32                  Pid          : 2;\r
  UINT32                  ErrCnt       : 2;\r
  UINT32                  CurPage      : 3;\r
  UINT32                  Ioc          : 1;\r
  UINT32                  TotalBytes   : 15;\r
  UINT32                  DataToggle   : 1;\r
\r
  UINT32                  Page[5];\r
  UINT32                  PageHigh[5];\r
} QTD_HW;\r
\r
typedef struct {\r
  UINT32                  HorizonLink;\r
  //\r
  // Endpoint capabilities/Characteristics DWord 1 and DWord 2\r
  //\r
  UINT32                  DeviceAddr   : 7;\r
  UINT32                  Inactive     : 1;\r
  UINT32                  EpNum        : 4;\r
  UINT32                  EpSpeed      : 2;\r
  UINT32                  DtCtrl       : 1;\r
  UINT32                  ReclaimHead  : 1;\r
  UINT32                  MaxPacketLen : 11;\r
  UINT32                  CtrlEp       : 1;\r
  UINT32                  NakReload    : 4;\r
\r
  UINT32                  SMask        : 8;\r
  UINT32                  CMask        : 8;\r
  UINT32                  HubAddr      : 7;\r
  UINT32                  PortNum      : 7;\r
  UINT32                  Multiplier   : 2;\r
\r
  //\r
  // Transaction execution overlay area\r
  //\r
  UINT32                  CurQtd;\r
  UINT32                  NextQtd;\r
  UINT32                  AltQtd;\r
\r
  UINT32                  Status       : 8;\r
  UINT32                  Pid          : 2;\r
  UINT32                  ErrCnt       : 2;\r
  UINT32                  CurPage      : 3;\r
  UINT32                  Ioc          : 1;\r
  UINT32                  TotalBytes   : 15;\r
  UINT32                  DataToggle   : 1;\r
\r
  UINT32                  Page[5];\r
  UINT32                  PageHigh[5];\r
} QH_HW;\r
#pragma pack()\r
\r
\r
//\r
// Endpoint address and its capabilities\r
//\r
typedef struct _USB_ENDPOINT {\r
  UINT8                   DevAddr;\r
  UINT8                   EpAddr;     // Endpoint address, no direction encoded in\r
  EFI_USB_DATA_DIRECTION  Direction;\r
  UINT8                   DevSpeed;\r
  UINTN                   MaxPacket;\r
  UINT8                   HubAddr;\r
  UINT8                   HubPort;\r
  UINT8                   Toggle;     // Data toggle, not used for control transfer\r
  UINTN                   Type;\r
  UINTN                   PollRate;   // Polling interval used by EHCI\r
} USB_ENDPOINT;\r
\r
//\r
// Software QTD strcture, this is used to manage all the\r
// QTD generated from a URB. Don't add fields before QtdHw.\r
//\r
struct _PEI_EHC_QTD {\r
  QTD_HW                  QtdHw;\r
  UINT32                  Signature;\r
  EFI_LIST_ENTRY          QtdList;   // The list of QTDs to one end point\r
  UINT8                   *Data;     // Buffer of the original data\r
  UINTN                   DataLen;   // Original amount of data in this QTD\r
};\r
\r
\r
\r
//\r
// Software QH structure. All three different transaction types\r
// supported by UEFI USB, that is the control/bulk/interrupt\r
// transfers use the queue head and queue token strcuture.\r
//\r
// Interrupt QHs are linked to periodic frame list in the reversed\r
// 2^N tree. Each interrupt QH is linked to the list starting at\r
// frame 0. There is a dummy interrupt QH linked to each frame as\r
// a sentinental whose polling interval is 1. Synchronous interrupt\r
// transfer is linked after this dummy QH.\r
//\r
// For control/bulk transfer, only synchronous (in the sense of UEFI)\r
// transfer is supported. A dummy QH is linked to EHCI AsyncListAddr\r
// as the reclamation header. New transfer is inserted after this QH.\r
//\r
struct _PEI_EHC_QH {\r
  QH_HW                   QhHw;\r
  UINT32                  Signature;\r
  PEI_EHC_QH              *NextQh;    // The queue head pointed to by horizontal link\r
  EFI_LIST_ENTRY          Qtds;       // The list of QTDs to this queue head\r
  UINTN                   Interval;\r
};\r
\r
//\r
// URB (Usb Request Block) contains information for all kinds of\r
// usb requests.\r
//\r
struct _PEI_URB {\r
  UINT32                          Signature;\r
  EFI_LIST_ENTRY                  UrbList;\r
\r
  //\r
  // Transaction information\r
  //\r
  USB_ENDPOINT                    Ep;\r
  EFI_USB_DEVICE_REQUEST          *Request;     // Control transfer only\r
  VOID                            *RequestPhy;  // Address of the mapped request\r
  VOID                            *RequestMap;\r
  VOID                            *Data;\r
  UINTN                           DataLen;\r
  VOID                            *DataPhy;     // Address of the mapped user data\r
  VOID                            *DataMap;\r
  EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r
  VOID                            *Context;\r
\r
  //\r
  // Schedule data\r
  //\r
  PEI_EHC_QH                      *Qh;\r
\r
  //\r
  // Transaction result\r
  //\r
  UINT32                          Result;\r
  UINTN                           Completed;    // completed data length\r
  UINT8                           DataToggle;\r
};\r
\r
/**\r
  Delete a single asynchronous interrupt transfer for\r
  the device and endpoint.\r
\r
  @param  Ehc         The EHCI device.\r
  @param  Data        Current data not associated with a QTD.\r
  @param  DataLen     The length of the data.\r
  @param  PktId       Packet ID to use in the QTD.\r
  @param  Toggle      Data toggle to use in the QTD.\r
  @param  MaxPacket   Maximu packet length of the endpoint.\r
\r
  @retval the pointer to the created QTD or NULL if failed to create one.\r
\r
**/\r
PEI_EHC_QTD *\r
EhcCreateQtd (\r
  IN PEI_USB2_HC_DEV      *Ehc,\r
  IN UINT8                *Data,\r
  IN UINTN                DataLen,\r
  IN UINT8                PktId,\r
  IN UINT8                Toggle,\r
  IN UINTN                MaxPacket\r
  )\r
;\r
\r
/**\r
  Allocate and initialize a EHCI queue head.\r
\r
  @param  Ehci      The EHCI device.\r
  @param  Ep        The endpoint to create queue head for.\r
\r
  @retval the pointer to the created queue head or NULL if failed to create one.\r
\r
**/\r
PEI_EHC_QH *\r
EhcCreateQh (\r
  IN PEI_USB2_HC_DEV      *Ehci,\r
  IN USB_ENDPOINT         *Ep\r
  )\r
;\r
\r
/**\r
  Free an allocated URB. It is possible for it to be partially inited.\r
\r
  @param  Ehc         The EHCI device.\r
  @param  Urb         The URB to free.\r
\r
**/\r
VOID\r
EhcFreeUrb (\r
  IN PEI_USB2_HC_DEV      *Ehc,\r
  IN PEI_URB              *Urb\r
  )\r
;\r
\r
/**\r
  Create a new URB and its associated QTD.\r
\r
  @param  Ehc               The EHCI device.\r
  @param  DevAddr           The device address.\r
  @param  EpAddr            Endpoint addrress & its direction.\r
  @param  DevSpeed          The device speed.\r
  @param  Toggle            Initial data toggle to use.\r
  @param  MaxPacket         The max packet length of the endpoint.\r
  @param  Hub               The transaction translator to use.\r
  @param  Type              The transaction type.\r
  @param  Request           The standard USB request for control transfer.\r
  @param  Data              The user data to transfer.\r
  @param  DataLen           The length of data buffer.\r
  @param  Callback          The function to call when data is transferred.\r
  @param  Context           The context to the callback.\r
  @param  Interval          The interval for interrupt transfer.\r
\r
  @retval the pointer to the created URB or NULL.\r
\r
**/\r
PEI_URB *\r
EhcCreateUrb (\r
  IN PEI_USB2_HC_DEV                    *Ehc,\r
  IN UINT8                              DevAddr,\r
  IN UINT8                              EpAddr,\r
  IN UINT8                              DevSpeed,\r
  IN UINT8                              Toggle,\r
  IN UINTN                              MaxPacket,\r
  IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,\r
  IN UINTN                              Type,\r
  IN EFI_USB_DEVICE_REQUEST             *Request,\r
  IN VOID                               *Data,\r
  IN UINTN                              DataLen,\r
  IN EFI_ASYNC_USB_TRANSFER_CALLBACK    Callback,\r
  IN VOID                               *Context,\r
  IN UINTN                              Interval\r
  )\r
;\r
#endif\r
Commit	Line	Data
4b1bf81c	1	/** @file\r
	2	Private Header file for Usb Host Controller PEIM\r
	3	\r
d1102dba LG	4	Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
d1102dba LG	5	\r
4b1bf81c	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions\r
	8	of the BSD License which accompanies this distribution. The\r
	9	full text of the license may be found at\r
	10	http://opensource.org/licenses/bsd-license.php\r
	11	\r
	12	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	\r
	15	**/\r
	16	\r
	17	#ifndef _EFI_EHCI_URB_H_\r
	18	#define _EFI_EHCI_URB_H_\r
	19	\r
	20	typedef struct _PEI_EHC_QTD PEI_EHC_QTD;\r
	21	typedef struct _PEI_EHC_QH PEI_EHC_QH;\r
	22	typedef struct _PEI_URB PEI_URB;\r
	23	\r
	24	#define EHC_CTRL_TRANSFER 0x01\r
	25	#define EHC_BULK_TRANSFER 0x02\r
	26	#define EHC_INT_TRANSFER_SYNC 0x04\r
	27	#define EHC_INT_TRANSFER_ASYNC 0x08\r
	28	\r
	29	#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')\r
	30	#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')\r
	31	#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')\r
	32	\r
	33	//\r
	34	// Hardware related bit definitions\r
	35	//\r
	36	#define EHC_TYPE_ITD 0x00\r
	37	#define EHC_TYPE_QH 0x02\r
	38	#define EHC_TYPE_SITD 0x04\r
	39	#define EHC_TYPE_FSTN 0x06\r
	40	\r
	41	#define QH_NAK_RELOAD 3\r
	42	#define QH_HSHBW_MULTI 1\r
	43	\r
	44	#define QTD_MAX_ERR 3\r
	45	#define QTD_PID_OUTPUT 0x00\r
	46	#define QTD_PID_INPUT 0x01\r
	47	#define QTD_PID_SETUP 0x02\r
	48	\r
	49	#define QTD_STAT_DO_OUT 0\r
	50	#define QTD_STAT_DO_SS 0\r
	51	#define QTD_STAT_DO_PING 0x01\r
	52	#define QTD_STAT_DO_CS 0x02\r
	53	#define QTD_STAT_TRANS_ERR 0x08\r
	54	#define QTD_STAT_BABBLE_ERR 0x10\r
	55	#define QTD_STAT_BUFF_ERR 0x20\r
	56	#define QTD_STAT_HALTED 0x40\r
	57	#define QTD_STAT_ACTIVE 0x80\r
	58	#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR \| QTD_STAT_BABBLE_ERR \| QTD_STAT_BUFF_ERR)\r
	59	\r
	60	#define QTD_MAX_BUFFER 4\r
	61	#define QTD_BUF_LEN 4096\r
	62	#define QTD_BUF_MASK 0x0FFF\r
	63	\r
	64	#define QH_MICROFRAME_0 0x01\r
	65	#define QH_MICROFRAME_1 0x02\r
	66	#define QH_MICROFRAME_2 0x04\r
	67	#define QH_MICROFRAME_3 0x08\r
	68	#define QH_MICROFRAME_4 0x10\r
	69	#define QH_MICROFRAME_5 0x20\r
70	#define QH_MICROFRAME_6 0x40\r
71	#define QH_MICROFRAME_7 0x80\r
72	\r
73	#define USB_ERR_SHORT_PACKET 0x200\r
74	\r
75	//\r
d1102dba	76	// Fill in the hardware link point: pass in a EHC_QH/QH_HW\r
4b1bf81c	77	// pointer to QH_LINK; A EHC_QTD/QTD_HW pointer to QTD_LINK\r
	78	//\r
	79	#define QH_LINK(Addr, Type, Term) \\r
	80	((UINT32) ((EHC_LOW_32BIT (Addr) & 0xFFFFFFE0) \| (Type) \| ((Term) ? 1 : 0)))\r
	81	\r
	82	#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))\r
	83	\r
	84	//\r
d1102dba LG	85	// The defination of EHCI hardware used data structure for\r
	86	// little endian architecture. The QTD and QH structures\r
	87	// are required to be 32 bytes aligned. Don't add members\r
4b1bf81c	88	// to the head of the associated software strucuture.\r
	89	//\r
	90	#pragma pack(1)\r
	91	typedef struct {\r
	92	UINT32 NextQtd;\r
	93	UINT32 AltNext;\r
d1102dba	94	\r
4b1bf81c	95	UINT32 Status : 8;\r
	96	UINT32 Pid : 2;\r
	97	UINT32 ErrCnt : 2;\r
	98	UINT32 CurPage : 3;\r
	99	UINT32 Ioc : 1;\r
	100	UINT32 TotalBytes : 15;\r
	101	UINT32 DataToggle : 1;\r
	102	\r
	103	UINT32 Page[5];\r
	104	UINT32 PageHigh[5];\r
	105	} QTD_HW;\r
	106	\r
	107	typedef struct {\r
d1102dba	108	UINT32 HorizonLink;\r
4b1bf81c	109	//\r
	110	// Endpoint capabilities/Characteristics DWord 1 and DWord 2\r
	111	//\r
	112	UINT32 DeviceAddr : 7;\r
	113	UINT32 Inactive : 1;\r
	114	UINT32 EpNum : 4;\r
	115	UINT32 EpSpeed : 2;\r
	116	UINT32 DtCtrl : 1;\r
	117	UINT32 ReclaimHead : 1;\r
	118	UINT32 MaxPacketLen : 11;\r
	119	UINT32 CtrlEp : 1;\r
	120	UINT32 NakReload : 4;\r
	121	\r
	122	UINT32 SMask : 8;\r
	123	UINT32 CMask : 8;\r
	124	UINT32 HubAddr : 7;\r
	125	UINT32 PortNum : 7;\r
	126	UINT32 Multiplier : 2;\r
	127	\r
	128	//\r
	129	// Transaction execution overlay area\r
	130	//\r
	131	UINT32 CurQtd;\r
	132	UINT32 NextQtd;\r
	133	UINT32 AltQtd;\r
d1102dba	134	\r
4b1bf81c	135	UINT32 Status : 8;\r
	136	UINT32 Pid : 2;\r
	137	UINT32 ErrCnt : 2;\r
	138	UINT32 CurPage : 3;\r
	139	UINT32 Ioc : 1;\r
	140	UINT32 TotalBytes : 15;\r
	141	UINT32 DataToggle : 1;\r
	142	\r
	143	UINT32 Page[5];\r
	144	UINT32 PageHigh[5];\r
	145	} QH_HW;\r
	146	#pragma pack()\r
	147	\r
	148	\r
	149	//\r
	150	// Endpoint address and its capabilities\r
	151	//\r
	152	typedef struct _USB_ENDPOINT {\r
	153	UINT8 DevAddr;\r
	154	UINT8 EpAddr; // Endpoint address, no direction encoded in\r
	155	EFI_USB_DATA_DIRECTION Direction;\r
	156	UINT8 DevSpeed;\r
	157	UINTN MaxPacket;\r
	158	UINT8 HubAddr;\r
	159	UINT8 HubPort;\r
	160	UINT8 Toggle; // Data toggle, not used for control transfer\r
	161	UINTN Type;\r
	162	UINTN PollRate; // Polling interval used by EHCI\r
	163	} USB_ENDPOINT;\r
	164	\r
	165	//\r
d1102dba	166	// Software QTD strcture, this is used to manage all the\r
4b1bf81c	167	// QTD generated from a URB. Don't add fields before QtdHw.\r
	168	//\r
	169	struct _PEI_EHC_QTD {\r
	170	QTD_HW QtdHw;\r
	171	UINT32 Signature;\r
	172	EFI_LIST_ENTRY QtdList; // The list of QTDs to one end point\r
	173	UINT8 *Data; // Buffer of the original data\r
	174	UINTN DataLen; // Original amount of data in this QTD\r
	175	};\r
	176	\r
	177	\r
	178	\r
	179	//\r
d1102dba LG	180	// Software QH structure. All three different transaction types\r
	181	// supported by UEFI USB, that is the control/bulk/interrupt\r
	182	// transfers use the queue head and queue token strcuture.\r
4b1bf81c	183	//\r
4b1bf81c	184	// Interrupt QHs are linked to periodic frame list in the reversed\r
d1102dba	185	// 2^N tree. Each interrupt QH is linked to the list starting at\r
4b1bf81c	186	// frame 0. There is a dummy interrupt QH linked to each frame as\r
4b1bf81c	187	// a sentinental whose polling interval is 1. Synchronous interrupt\r
d1102dba LG	188	// transfer is linked after this dummy QH.\r
	189	//\r
	190	// For control/bulk transfer, only synchronous (in the sense of UEFI)\r
4b1bf81c	191	// transfer is supported. A dummy QH is linked to EHCI AsyncListAddr\r
	192	// as the reclamation header. New transfer is inserted after this QH.\r
	193	//\r
	194	struct _PEI_EHC_QH {\r
	195	QH_HW QhHw;\r
	196	UINT32 Signature;\r
	197	PEI_EHC_QH *NextQh; // The queue head pointed to by horizontal link\r
	198	EFI_LIST_ENTRY Qtds; // The list of QTDs to this queue head\r
d1102dba	199	UINTN Interval;\r
4b1bf81c	200	};\r
	201	\r
	202	//\r
d1102dba	203	// URB (Usb Request Block) contains information for all kinds of\r
4b1bf81c	204	// usb requests.\r
	205	//\r
	206	struct _PEI_URB {\r
	207	UINT32 Signature;\r
	208	EFI_LIST_ENTRY UrbList;\r
d1102dba	209	\r
4b1bf81c	210	//\r
	211	// Transaction information\r
	212	//\r
	213	USB_ENDPOINT Ep;\r
	214	EFI_USB_DEVICE_REQUEST *Request; // Control transfer only\r
	215	VOID *RequestPhy; // Address of the mapped request\r
	216	VOID *RequestMap;\r
	217	VOID *Data;\r
	218	UINTN DataLen;\r
	219	VOID *DataPhy; // Address of the mapped user data\r
	220	VOID *DataMap;\r
d1102dba	221	EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r
4b1bf81c	222	VOID *Context;\r
	223	\r
	224	//\r
	225	// Schedule data\r
	226	//\r
	227	PEI_EHC_QH *Qh;\r
d1102dba	228	\r
4b1bf81c	229	//\r
	230	// Transaction result\r
	231	//\r
	232	UINT32 Result;\r
	233	UINTN Completed; // completed data length\r
	234	UINT8 DataToggle;\r
	235	};\r
	236	\r
	237	/**\r
	238	Delete a single asynchronous interrupt transfer for\r
	239	the device and endpoint.\r
d1102dba	240	\r
4b1bf81c	241	@param Ehc The EHCI device.\r
	242	@param Data Current data not associated with a QTD.\r
	243	@param DataLen The length of the data.\r
	244	@param PktId Packet ID to use in the QTD.\r
	245	@param Toggle Data toggle to use in the QTD.\r
	246	@param MaxPacket Maximu packet length of the endpoint.\r
	247	\r
	248	@retval the pointer to the created QTD or NULL if failed to create one.\r
	249	\r
	250	**/\r
	251	PEI_EHC_QTD *\r
	252	EhcCreateQtd (\r
	253	IN PEI_USB2_HC_DEV *Ehc,\r
	254	IN UINT8 *Data,\r
	255	IN UINTN DataLen,\r
	256	IN UINT8 PktId,\r
	257	IN UINT8 Toggle,\r
	258	IN UINTN MaxPacket\r
	259	)\r
	260	;\r
	261	\r
	262	/**\r
	263	Allocate and initialize a EHCI queue head.\r
d1102dba	264	\r
4b1bf81c	265	@param Ehci The EHCI device.\r
	266	@param Ep The endpoint to create queue head for.\r
	267	\r
	268	@retval the pointer to the created queue head or NULL if failed to create one.\r
	269	\r
	270	**/\r
	271	PEI_EHC_QH *\r
	272	EhcCreateQh (\r
	273	IN PEI_USB2_HC_DEV *Ehci,\r
	274	IN USB_ENDPOINT *Ep\r
	275	)\r
	276	;\r
	277	\r
	278	/**\r
	279	Free an allocated URB. It is possible for it to be partially inited.\r
d1102dba	280	\r
4b1bf81c	281	@param Ehc The EHCI device.\r
	282	@param Urb The URB to free.\r
	283	\r
	284	**/\r
	285	VOID\r
	286	EhcFreeUrb (\r
	287	IN PEI_USB2_HC_DEV *Ehc,\r
	288	IN PEI_URB *Urb\r
	289	)\r
	290	;\r
	291	\r
	292	/**\r
	293	Create a new URB and its associated QTD.\r
d1102dba	294	\r
4b1bf81c	295	@param Ehc The EHCI device.\r
	296	@param DevAddr The device address.\r
	297	@param EpAddr Endpoint addrress & its direction.\r
	298	@param DevSpeed The device speed.\r
	299	@param Toggle Initial data toggle to use.\r
	300	@param MaxPacket The max packet length of the endpoint.\r
	301	@param Hub The transaction translator to use.\r
	302	@param Type The transaction type.\r
	303	@param Request The standard USB request for control transfer.\r
	304	@param Data The user data to transfer.\r
	305	@param DataLen The length of data buffer.\r
	306	@param Callback The function to call when data is transferred.\r
	307	@param Context The context to the callback.\r
	308	@param Interval The interval for interrupt transfer.\r
	309	\r
	310	@retval the pointer to the created URB or NULL.\r
	311	\r
	312	**/\r
	313	PEI_URB *\r
	314	EhcCreateUrb (\r
	315	IN PEI_USB2_HC_DEV *Ehc,\r
	316	IN UINT8 DevAddr,\r
d1102dba	317	IN UINT8 EpAddr,\r
4b1bf81c	318	IN UINT8 DevSpeed,\r
	319	IN UINT8 Toggle,\r
	320	IN UINTN MaxPacket,\r
	321	IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,\r
	322	IN UINTN Type,\r
	323	IN EFI_USB_DEVICE_REQUEST *Request,\r
	324	IN VOID *Data,\r
	325	IN UINTN DataLen,\r
	326	IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
	327	IN VOID *Context,\r
	328	IN UINTN Interval\r
	329	)\r
	330	;\r
	331	#endif\r