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[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressPassthru.c
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eb290d02
FT		 1/** @file\r
2 NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r
3 NVM Express specification.\r
4\r
35f910f0 5 (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>\r
eb290d02
FT		 6 Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
7 This program and the accompanying materials\r
8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php.\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17#include "NvmExpress.h"\r
18\r
19//\r
20// Page size should be set in the Controller Configuration register\r
21// during controller init, and the controller configuration save in\r
22// the controller's private data. The Max and Min supported page sizes\r
23// for the controller are specified in the Controller Capabilities register.\r
24//\r
25\r
26GLOBAL_REMOVE_IF_UNREFERENCED NVM_EXPRESS_PASS_THRU_MODE gNvmExpressPassThruMode = {\r
27 0,\r
28 NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL | NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVME,\r
29 sizeof (UINTN),\r
30 0x10000,\r
31 0,\r
32 0\r
33};\r
34\r
35\r
36/**\r
37 Dump the execution status from a given completion queue entry.\r
38\r
39 @param[in] Cq A pointer to the NVME_CQ item.\r
40\r
41**/\r
42VOID\r
43NvmeDumpStatus (\r
44 IN NVME_CQ *Cq\r
45 )\r
46{\r
47 DEBUG ((EFI_D_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));\r
48\r
49 DEBUG ((EFI_D_VERBOSE, " SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));\r
50\r
51 DEBUG ((EFI_D_VERBOSE, " NVMe Cmd Execution Result - "));\r
52\r
53 switch (Cq->Sct) {\r
54 case 0x0:\r
55 switch (Cq->Sc) {\r
56 case 0x0:\r
57 DEBUG ((EFI_D_VERBOSE, "Successful Completion\n"));\r
58 break;\r
59 case 0x1:\r
60 DEBUG ((EFI_D_VERBOSE, "Invalid Command Opcode\n"));\r
61 break;\r
62 case 0x2:\r
63 DEBUG ((EFI_D_VERBOSE, "Invalid Field in Command\n"));\r
64 break;\r
65 case 0x3:\r
66 DEBUG ((EFI_D_VERBOSE, "Command ID Conflict\n"));\r
67 break;\r
68 case 0x4:\r
69 DEBUG ((EFI_D_VERBOSE, "Data Transfer Error\n"));\r
70 break;\r
71 case 0x5:\r
72 DEBUG ((EFI_D_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));\r
73 break;\r
74 case 0x6:\r
75 DEBUG ((EFI_D_VERBOSE, "Internal Device Error\n"));\r
76 break;\r
77 case 0x7:\r
78 DEBUG ((EFI_D_VERBOSE, "Command Abort Requested\n"));\r
79 break;\r
80 case 0x8:\r
81 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to SQ Deletion\n"));\r
82 break;\r
83 case 0x9:\r
84 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Failed Fused Command\n"));\r
85 break;\r
86 case 0xA:\r
87 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Missing Fused Command\n"));\r
88 break;\r
89 case 0xB:\r
90 DEBUG ((EFI_D_VERBOSE, "Invalid Namespace or Format\n"));\r
91 break;\r
92 case 0xC:\r
93 DEBUG ((EFI_D_VERBOSE, "Command Sequence Error\n"));\r
94 break;\r
95 case 0xD:\r
96 DEBUG ((EFI_D_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));\r
97 break;\r
98 case 0xE:\r
99 DEBUG ((EFI_D_VERBOSE, "Invalid Number of SGL Descriptors\n"));\r
100 break;\r
101 case 0xF:\r
102 DEBUG ((EFI_D_VERBOSE, "Data SGL Length Invalid\n"));\r
103 break;\r
104 case 0x10:\r
105 DEBUG ((EFI_D_VERBOSE, "Metadata SGL Length Invalid\n"));\r
106 break;\r
107 case 0x11:\r
108 DEBUG ((EFI_D_VERBOSE, "SGL Descriptor Type Invalid\n"));\r
109 break;\r
110 case 0x80:\r
111 DEBUG ((EFI_D_VERBOSE, "LBA Out of Range\n"));\r
112 break;\r
113 case 0x81:\r
114 DEBUG ((EFI_D_VERBOSE, "Capacity Exceeded\n"));\r
115 break;\r
116 case 0x82:\r
117 DEBUG ((EFI_D_VERBOSE, "Namespace Not Ready\n"));\r
118 break;\r
119 case 0x83:\r
120 DEBUG ((EFI_D_VERBOSE, "Reservation Conflict\n"));\r
121 break;\r
122 }\r
123 break;\r
124\r
125 case 0x1:\r
126 switch (Cq->Sc) {\r
127 case 0x0:\r
128 DEBUG ((EFI_D_VERBOSE, "Completion Queue Invalid\n"));\r
129 break;\r
130 case 0x1:\r
131 DEBUG ((EFI_D_VERBOSE, "Invalid Queue Identifier\n"));\r
132 break;\r
133 case 0x2:\r
134 DEBUG ((EFI_D_VERBOSE, "Maximum Queue Size Exceeded\n"));\r
135 break;\r
136 case 0x3:\r
137 DEBUG ((EFI_D_VERBOSE, "Abort Command Limit Exceeded\n"));\r
138 break;\r
139 case 0x5:\r
140 DEBUG ((EFI_D_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));\r
141 break;\r
142 case 0x6:\r
143 DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Slot\n"));\r
144 break;\r
145 case 0x7:\r
146 DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Image\n"));\r
147 break;\r
148 case 0x8:\r
149 DEBUG ((EFI_D_VERBOSE, "Invalid Interrupt Vector\n"));\r
150 break;\r
151 case 0x9:\r
152 DEBUG ((EFI_D_VERBOSE, "Invalid Log Page\n"));\r
153 break;\r
154 case 0xA:\r
155 DEBUG ((EFI_D_VERBOSE, "Invalid Format\n"));\r
156 break;\r
157 case 0xB:\r
158 DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires Conventional Reset\n"));\r
159 break;\r
160 case 0xC:\r
161 DEBUG ((EFI_D_VERBOSE, "Invalid Queue Deletion\n"));\r
162 break;\r
163 case 0xD:\r
164 DEBUG ((EFI_D_VERBOSE, "Feature Identifier Not Saveable\n"));\r
165 break;\r
166 case 0xE:\r
167 DEBUG ((EFI_D_VERBOSE, "Feature Not Changeable\n"));\r
168 break;\r
169 case 0xF:\r
170 DEBUG ((EFI_D_VERBOSE, "Feature Not Namespace Specific\n"));\r
171 break;\r
172 case 0x10:\r
173 DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));\r
174 break;\r
175 case 0x80:\r
176 DEBUG ((EFI_D_VERBOSE, "Conflicting Attributes\n"));\r
177 break;\r
178 case 0x81:\r
179 DEBUG ((EFI_D_VERBOSE, "Invalid Protection Information\n"));\r
180 break;\r
181 case 0x82:\r
182 DEBUG ((EFI_D_VERBOSE, "Attempted Write to Read Only Range\n"));\r
183 break;\r
184 }\r
185 break;\r
186\r
187 case 0x2:\r
188 switch (Cq->Sc) {\r
189 case 0x80:\r
190 DEBUG ((EFI_D_VERBOSE, "Write Fault\n"));\r
191 break;\r
192 case 0x81:\r
193 DEBUG ((EFI_D_VERBOSE, "Unrecovered Read Error\n"));\r
194 break;\r
195 case 0x82:\r
196 DEBUG ((EFI_D_VERBOSE, "End-to-end Guard Check Error\n"));\r
197 break;\r
198 case 0x83:\r
199 DEBUG ((EFI_D_VERBOSE, "End-to-end Application Tag Check Error\n"));\r
200 break;\r
201 case 0x84:\r
202 DEBUG ((EFI_D_VERBOSE, "End-to-end Reference Tag Check Error\n"));\r
203 break;\r
204 case 0x85:\r
205 DEBUG ((EFI_D_VERBOSE, "Compare Failure\n"));\r
206 break;\r
207 case 0x86:\r
208 DEBUG ((EFI_D_VERBOSE, "Access Denied\n"));\r
209 break;\r
210 }\r
211 break;\r
212\r
213 default:\r
214 break;\r
215 }\r
216}\r
217\r
218/**\r
219 Create PRP lists for data transfer which is larger than 2 memory pages.\r
220 Note here we calcuate the number of required PRP lists and allocate them at one time.\r
221\r
222 @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
223 @param[in] PhysicalAddr The physical base address of data buffer.\r
224 @param[in] Pages The number of pages to be transfered.\r
225 @param[out] PrpListHost The host base address of PRP lists.\r
226 @param[in,out] PrpListNo The number of PRP List.\r
227 @param[out] Mapping The mapping value returned from PciIo.Map().\r
228\r
229 @retval The pointer to the first PRP List of the PRP lists.\r
230\r
231**/\r
232VOID*\r
233NvmeCreatePrpList (\r
234 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
235 IN EFI_PHYSICAL_ADDRESS PhysicalAddr,\r
236 IN UINTN Pages,\r
237 OUT VOID **PrpListHost,\r
238 IN OUT UINTN *PrpListNo,\r
239 OUT VOID **Mapping\r
240 )\r
241{\r
242 UINTN PrpEntryNo;\r
243 UINT64 PrpListBase;\r
244 UINTN PrpListIndex;\r
245 UINTN PrpEntryIndex;\r
246 UINT64 Remainder;\r
247 EFI_PHYSICAL_ADDRESS PrpListPhyAddr;\r
248 UINTN Bytes;\r
249 EFI_STATUS Status;\r
250\r
251 //\r
252 // The number of Prp Entry in a memory page.\r
253 //\r
254 PrpEntryNo = EFI_PAGE_SIZE / sizeof (UINT64);\r
255\r
256 //\r
257 // Calculate total PrpList number.\r
258 //\r
259 *PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo, &Remainder);\r
260 if (Remainder != 0) {\r
261 *PrpListNo += 1;\r
262 }\r
263\r
264 Status = PciIo->AllocateBuffer (\r
265 PciIo,\r
266 AllocateAnyPages,\r
267 EfiBootServicesData,\r
268 *PrpListNo,\r
269 PrpListHost,\r
270 0\r
271 );\r
272\r
273 if (EFI_ERROR (Status)) {\r
274 return NULL;\r
275 }\r
276\r
277 Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);\r
278 Status = PciIo->Map (\r
279 PciIo,\r
280 EfiPciIoOperationBusMasterCommonBuffer,\r
281 *PrpListHost,\r
282 &Bytes,\r
283 &PrpListPhyAddr,\r
284 Mapping\r
285 );\r
286\r
287 if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (*PrpListNo))) {\r
288 DEBUG ((EFI_D_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));\r
289 goto EXIT;\r
290 }\r
291 //\r
292 // Fill all PRP lists except of last one.\r
293 //\r
294 ZeroMem (*PrpListHost, Bytes);\r
295 for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {\r
296 PrpListBase = *(UINT8*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r
297\r
298 for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {\r
299 if (PrpEntryIndex != PrpEntryNo - 1) {\r
300 //\r
301 // Fill all PRP entries except of last one.\r
302 //\r
303 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r
304 PhysicalAddr += EFI_PAGE_SIZE;\r
305 } else {\r
306 //\r
307 // Fill last PRP entries with next PRP List pointer.\r
308 //\r
309 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;\r
310 }\r
311 }\r
312 }\r
313 //\r
314 // Fill last PRP list.\r
315 //\r
316 PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r
317 for (PrpEntryIndex = 0; PrpEntryIndex < ((Remainder != 0) ? Remainder : PrpEntryNo); ++PrpEntryIndex) {\r
318 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r
319 PhysicalAddr += EFI_PAGE_SIZE;\r
320 }\r
321\r
322 return (VOID*)(UINTN)PrpListPhyAddr;\r
323\r
324EXIT:\r
325 PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);\r
326 return NULL;\r
327}\r
328\r
329\r
330/**\r
331 Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports\r
332 both blocking I/O and nonblocking I/O. The blocking I/O functionality is required, and the nonblocking\r
333 I/O functionality is optional.\r
334\r
335 @param[in] This A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
336 @param[in] NamespaceId Is a 32 bit Namespace ID to which the Express HCI command packet will be sent.\r
337 A value of 0 denotes the NVM Express controller, a value of all 0FFh in the namespace\r
338 ID specifies that the command packet should be sent to all valid namespaces.\r
339 @param[in] NamespaceUuid Is a 64 bit Namespace UUID to which the Express HCI command packet will be sent.\r
340 A value of 0 denotes the NVM Express controller, a value of all 0FFh in the namespace\r
341 UUID specifies that the command packet should be sent to all valid namespaces.\r
342 @param[in,out] Packet A pointer to the NVM Express HCI Command Packet to send to the NVMe namespace specified\r
343 by NamespaceId.\r
344 @param[in] Event If nonblocking I/O is not supported then Event is ignored, and blocking I/O is performed.\r
345 If Event is NULL, then blocking I/O is performed. If Event is not NULL and non blocking I/O\r
346 is supported, then nonblocking I/O is performed, and Event will be signaled when the NVM\r
347 Express Command Packet completes.\r
348\r
349 @retval EFI_SUCCESS The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred\r
350 to, or from DataBuffer.\r
351 @retval EFI_BAD_BUFFER_SIZE The NVM Express Command Packet was not executed. The number of bytes that could be transferred\r
352 is returned in TransferLength.\r
353 @retval EFI_NOT_READY The NVM Express Command Packet could not be sent because the controller is not ready. The caller\r
354 may retry again later.\r
355 @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the NVM Express Command Packet.\r
356 @retval EFI_INVALID_PARAMETER Namespace, or the contents of NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM\r
357 Express Command Packet was not sent, so no additional status information is available.\r
358 @retval EFI_UNSUPPORTED The command described by the NVM Express Command Packet is not supported by the host adapter.\r
359 The NVM Express Command Packet was not sent, so no additional status information is available.\r
360 @retval EFI_TIMEOUT A timeout occurred while waiting for the NVM Express Command Packet to execute.\r
361\r
362**/\r
363EFI_STATUS\r
364EFIAPI\r
365NvmExpressPassThru (\r
366 IN NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
367 IN UINT32 NamespaceId,\r
368 IN UINT64 NamespaceUuid,\r
369 IN OUT NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,\r
370 IN EFI_EVENT Event OPTIONAL\r
371 )\r
372{\r
373 NVME_CONTROLLER_PRIVATE_DATA *Private;\r
374 EFI_STATUS Status;\r
375 EFI_PCI_IO_PROTOCOL *PciIo;\r
376 NVME_SQ *Sq;\r
377 NVME_CQ *Cq;\r
378 UINT8 Qid;\r
379 UINT32 Bytes;\r
380 UINT16 Offset;\r
381 EFI_EVENT TimerEvent;\r
382 EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r
383 EFI_PHYSICAL_ADDRESS PhyAddr;\r
384 VOID *MapData;\r
385 VOID *MapMeta;\r
386 VOID *MapPrpList;\r
387 UINTN MapLength;\r
388 UINT64 *Prp;\r
389 VOID *PrpListHost;\r
390 UINTN PrpListNo;\r
7b8883c6 391 UINT32 Data;\r
eb290d02
FT		 392\r
393 //\r
394 // check the data fields in Packet parameter.\r
395 //\r
396 if ((This == NULL) || (Packet == NULL)) {\r
397 return EFI_INVALID_PARAMETER;\r
398 }\r
399\r
400 if ((Packet->NvmeCmd == NULL) || (Packet->NvmeResponse == NULL)) {\r
401 return EFI_INVALID_PARAMETER;\r
402 }\r
403\r
404 if (Packet->QueueId != NVME_ADMIN_QUEUE && Packet->QueueId != NVME_IO_QUEUE) {\r
405 return EFI_INVALID_PARAMETER;\r
406 }\r
407\r
408 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r
409 PciIo = Private->PciIo;\r
410 MapData = NULL;\r
411 MapMeta = NULL;\r
412 MapPrpList = NULL;\r
413 PrpListHost = NULL;\r
414 PrpListNo = 0;\r
415 Prp = NULL;\r
416 TimerEvent = NULL;\r
417 Status = EFI_SUCCESS;\r
418\r
419 Qid = Packet->QueueId;\r
420 Sq = Private->SqBuffer[Qid] + Private->SqTdbl[Qid].Sqt;\r
421 Cq = Private->CqBuffer[Qid] + Private->CqHdbl[Qid].Cqh;\r
422\r
423 if (Packet->NvmeCmd->Nsid != NamespaceId) {\r
424 return EFI_INVALID_PARAMETER;\r
425 }\r
426\r
427 ZeroMem (Sq, sizeof (NVME_SQ));\r
428 Sq->Opc = Packet->NvmeCmd->Cdw0.Opcode;\r
429 Sq->Fuse = Packet->NvmeCmd->Cdw0.FusedOperation;\r
430 Sq->Cid = Packet->NvmeCmd->Cdw0.Cid;\r
431 Sq->Nsid = Packet->NvmeCmd->Nsid;\r
432\r
433 //\r
434 // Currently we only support PRP for data transfer, SGL is NOT supported.\r
435 //\r
7b8883c6
FT		 436 ASSERT (Sq->Psdt == 0);\r
437 if (Sq->Psdt != 0) {\r
eb290d02
FT		 438 DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));\r
439 return EFI_UNSUPPORTED;\r
440 }\r
441\r
442 Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;\r
443 //\r
444 // If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.\r
445 // Note here we don't handle data buffer for CreateIOSubmitionQueue and CreateIOCompletionQueue cmds because\r
446 // these two cmds are special which requires their data buffer must support simultaneous access by both the\r
447 // processor and a PCI Bus Master. It's caller's responsbility to ensure this.\r
448 //\r
449 if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_OPC) && (Sq->Opc != NVME_ADMIN_CRIOSQ_OPC)) {\r
450 if ((Sq->Opc & BIT0) != 0) {\r
451 Flag = EfiPciIoOperationBusMasterRead;\r
452 } else {\r
453 Flag = EfiPciIoOperationBusMasterWrite;\r
454 }\r
455\r
456 MapLength = Packet->TransferLength;\r
457 Status = PciIo->Map (\r
458 PciIo,\r
459 Flag,\r
460 Packet->TransferBuffer,\r
461 &MapLength,\r
462 &PhyAddr,\r
463 &MapData\r
464 );\r
465 if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {\r
466 return EFI_OUT_OF_RESOURCES;\r
467 }\r
468\r
469 Sq->Prp[0] = PhyAddr;\r
470 Sq->Prp[1] = 0;\r
471\r
472 MapLength = Packet->MetadataLength;\r
473 if(Packet->MetadataBuffer != NULL) {\r
474 MapLength = Packet->MetadataLength;\r
475 Status = PciIo->Map (\r
476 PciIo,\r
477 Flag,\r
478 Packet->MetadataBuffer,\r
479 &MapLength,\r
480 &PhyAddr,\r
481 &MapMeta\r
482 );\r
483 if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {\r
484 PciIo->Unmap (\r
485 PciIo,\r
486 MapData\r
487 );\r
488\r
489 return EFI_OUT_OF_RESOURCES;\r
490 }\r
491 Sq->Mptr = PhyAddr;\r
492 }\r
493 }\r
494 //\r
495 // If the buffer size spans more than two memory pages (page size as defined in CC.Mps),\r
496 // then build a PRP list in the second PRP submission queue entry.\r
497 //\r
498 Offset = ((UINT16)Sq->Prp[0]) & (EFI_PAGE_SIZE - 1);\r
499 Bytes = Packet->TransferLength;\r
500\r
501 if ((Offset + Bytes) > (EFI_PAGE_SIZE * 2)) {\r
502 //\r
503 // Create PrpList for remaining data buffer.\r
504 //\r
505 PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r
506 Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);\r
507 if (Prp == NULL) {\r
508 goto EXIT;\r
509 }\r
510\r
511 Sq->Prp[1] = (UINT64)(UINTN)Prp;\r
512 } else if ((Offset + Bytes) > EFI_PAGE_SIZE) {\r
513 Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r
514 }\r
515\r
516 if(Packet->NvmeCmd->Flags & CDW10_VALID) {\r
517 Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;\r
518 }\r
519 if(Packet->NvmeCmd->Flags & CDW11_VALID) {\r
520 Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;\r
521 }\r
522 if(Packet->NvmeCmd->Flags & CDW12_VALID) {\r
523 Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;\r
524 }\r
525 if(Packet->NvmeCmd->Flags & CDW13_VALID) {\r
526 Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;\r
527 }\r
528 if(Packet->NvmeCmd->Flags & CDW14_VALID) {\r
529 Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;\r
530 }\r
531 if(Packet->NvmeCmd->Flags & CDW15_VALID) {\r
532 Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;\r
533 }\r
534\r
535 //\r
536 // Ring the submission queue doorbell.\r
537 //\r
538 Private->SqTdbl[Qid].Sqt ^= 1;\r
7b8883c6 539 Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[Qid]);\r
eb290d02
FT		 540 PciIo->Mem.Write (\r
541 PciIo,\r
542 EfiPciIoWidthUint32,\r
543 NVME_BAR,\r
544 NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd),\r
545 1,\r
7b8883c6 546 &Data\r
eb290d02
FT		 547 );\r
548\r
549 Status = gBS->CreateEvent (\r
550 EVT_TIMER,\r
551 TPL_CALLBACK,\r
552 NULL,\r
553 NULL,\r
554 &TimerEvent\r
555 );\r
556 if (EFI_ERROR (Status)) {\r
557 goto EXIT;\r
558 }\r
559\r
560 Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);\r
561\r
562 if (EFI_ERROR(Status)) {\r
563 Packet->ControllerStatus = NVM_EXPRESS_STATUS_CONTROLLER_DEVICE_ERROR;\r
564 goto EXIT;\r
565 }\r
566\r
567 //\r
568 // Wait for completion queue to get filled in.\r
569 //\r
570 Status = EFI_TIMEOUT;\r
571 Packet->ControllerStatus = NVM_EXPRESS_STATUS_CONTROLLER_TIMEOUT_COMMAND;\r
572 while (EFI_ERROR (gBS->CheckEvent (TimerEvent))) {\r
573 if (Cq->Pt != Private->Pt[Qid]) {\r
574 Status = EFI_SUCCESS;\r
575 Packet->ControllerStatus = NVM_EXPRESS_STATUS_CONTROLLER_READY;\r
576 break;\r
577 }\r
578 }\r
579\r
580 if ((Private->CqHdbl[Qid].Cqh ^= 1) == 0) {\r
581 Private->Pt[Qid] ^= 1;\r
582 }\r
583\r
584 //\r
585 // Copy the Respose Queue entry for this command to the callers response buffer\r
586 //\r
587 CopyMem(Packet->NvmeResponse, Cq, sizeof(NVM_EXPRESS_RESPONSE));\r
588\r
589 //\r
590 // Dump every completion entry status for debugging.\r
591 //\r
592 DEBUG_CODE_BEGIN();\r
593 NvmeDumpStatus(Cq);\r
594 DEBUG_CODE_END();\r
595\r
7b8883c6 596 Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[Qid]);\r
eb290d02
FT		 597 PciIo->Mem.Write (\r
598 PciIo,\r
599 EfiPciIoWidthUint32,\r
600 NVME_BAR,\r
601 NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd),\r
602 1,\r
7b8883c6 603 &Data\r
eb290d02
FT		 604 );\r
605\r
606EXIT:\r
607 if (MapData != NULL) {\r
608 PciIo->Unmap (\r
609 PciIo,\r
610 MapData\r
611 );\r
612 }\r
613\r
614 if (MapMeta != NULL) {\r
615 PciIo->Unmap (\r
616 PciIo,\r
617 MapMeta\r
618 );\r
619 }\r
620\r
621 if (MapPrpList != NULL) {\r
622 PciIo->Unmap (\r
623 PciIo,\r
624 MapPrpList\r
625 );\r
626 }\r
627\r
628 if (Prp != NULL) {\r
629 PciIo->FreeBuffer (PciIo, PrpListNo, PrpListHost);\r
630 }\r
631\r
632 if (TimerEvent != NULL) {\r
633 gBS->CloseEvent (TimerEvent);\r
634 }\r
635 return Status;\r
636}\r
637\r
638/**\r
639 Used to retrieve the list of namespaces defined on an NVM Express controller.\r
640\r
641 The NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves a list of namespaces\r
642 defined on an NVM Express controller. If on input a NamespaceID is specified by all 0xFF in the\r
643 namespace buffer, then the first namespace defined on the NVM Express controller is returned in\r
644 NamespaceID, and a status of EFI_SUCCESS is returned.\r
645\r
646 If NamespaceId is a Namespace value that was returned on a previous call to GetNextNamespace(),\r
647 then the next valid NamespaceId for an NVM Express SSD namespace on the NVM Express controller\r
648 is returned in NamespaceId, and EFI_SUCCESS is returned.\r
649\r
650 If Namespace array is not a 0xFFFFFFFF and NamespaceId was not returned on a previous call to\r
651 GetNextNamespace(), then EFI_INVALID_PARAMETER is returned.\r
652\r
653 If NamespaceId is the NamespaceId of the last SSD namespace on the NVM Express controller, then\r
654 EFI_NOT_FOUND is returned\r
655\r
656 @param[in] This A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
657 @param[in,out] NamespaceId On input, a pointer to a legal NamespaceId for an NVM Express\r
658 namespace present on the NVM Express controller. On output, a\r
659 pointer to the next NamespaceId of an NVM Express namespace on\r
660 an NVM Express controller. An input value of 0xFFFFFFFF retrieves\r
661 the first NamespaceId for an NVM Express namespace present on an\r
662 NVM Express controller.\r
663 @param[out] NamespaceUuid On output, the UUID associated with the next namespace, if a UUID\r
664 is defined for that NamespaceId, otherwise, zero is returned in\r
665 this parameter. If the caller does not require a UUID, then a NULL\r
666 pointer may be passed.\r
667\r
668 @retval EFI_SUCCESS The NamespaceId of the next Namespace was returned.\r
669 @retval EFI_NOT_FOUND There are no more namespaces defined on this controller.\r
670 @retval EFI_INVALID_PARAMETER Namespace array is not a 0xFFFFFFFF and NamespaceId was not returned\r
671 on a previous call to GetNextNamespace().\r
672\r
673**/\r
674EFI_STATUS\r
675EFIAPI\r
676NvmExpressGetNextNamespace (\r
677 IN NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
678 IN OUT UINT32 *NamespaceId,\r
679 OUT UINT64 *NamespaceUuid OPTIONAL\r
680 )\r
681{\r
682 NVME_CONTROLLER_PRIVATE_DATA *Private;\r
683 NVME_ADMIN_NAMESPACE_DATA *NamespaceData;\r
684 UINT32 NextNamespaceId;\r
685 EFI_STATUS Status;\r
686\r
687 if ((This == NULL) || (NamespaceId == NULL)) {\r
688 return EFI_INVALID_PARAMETER;\r
689 }\r
690\r
691 NamespaceData = NULL;\r
692 Status = EFI_NOT_FOUND;\r
693\r
694 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r
695 //\r
696 // If the NamespaceId input value is 0xFFFFFFFF, then get the first valid namespace ID\r
697 //\r
698 if (*NamespaceId == 0xFFFFFFFF) {\r
699 //\r
700 // Start with the first namespace ID\r
701 //\r
702 NextNamespaceId = 1;\r
703 //\r
704 // Allocate buffer for Identify Namespace data.\r
705 //\r
706 NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r
707\r
708 if (NamespaceData == NULL) {\r
709 return EFI_NOT_FOUND;\r
710 }\r
711\r
712 Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r
713 if (EFI_ERROR(Status)) {\r
714 goto Done;\r
715 }\r
716\r
717 *NamespaceId = NextNamespaceId;\r
718 if (NamespaceUuid != NULL) {\r
719 *NamespaceUuid = NamespaceData->Eui64;\r
720 }\r
721 } else {\r
722 if (*NamespaceId >= Private->ControllerData->Nn) {\r
723 return EFI_INVALID_PARAMETER;\r
724 }\r
725\r
726 NextNamespaceId = *NamespaceId + 1;\r
727 //\r
728 // Allocate buffer for Identify Namespace data.\r
729 //\r
730 NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r
731 if (NamespaceData == NULL) {\r
732 return EFI_NOT_FOUND;\r
733 }\r
734\r
735 Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r
736 if (EFI_ERROR(Status)) {\r
737 goto Done;\r
738 }\r
739\r
740 *NamespaceId = NextNamespaceId;\r
741 if (NamespaceUuid != NULL) {\r
742 *NamespaceUuid = NamespaceData->Eui64;\r
743 }\r
744 }\r
745\r
746Done:\r
747 if (NamespaceData != NULL) {\r
748 FreePool(NamespaceData);\r
749 }\r
750\r
751 return Status;\r
752}\r
753\r
754/**\r
755 Used to translate a device path node to a Namespace ID and Namespace UUID.\r
756\r
757 The NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamwspace() function determines the Namespace ID and Namespace UUID\r
758 associated with the NVM Express SSD namespace described by DevicePath. If DevicePath is a device path node type\r
759 that the NVM Express Pass Thru driver supports, then the NVM Express Pass Thru driver will attempt to translate\r
760 the contents DevicePath into a Namespace ID and UUID. If this translation is successful, then that Namespace ID\r
761 and UUID are returned in NamespaceID and NamespaceUUID, and EFI_SUCCESS is returned.\r
762\r
763 @param[in] This A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
764 @param[in] DevicePath A pointer to the device path node that describes an NVM Express namespace on\r
765 the NVM Express controller.\r
766 @param[out] NamespaceId The NVM Express namespace ID contained in the device path node.\r
767 @param[out] NamespaceUuid The NVM Express namespace contained in the device path node.\r
768\r
769 @retval EFI_SUCCESS DevicePath was successfully translated to NamespaceId and NamespaceUuid.\r
770 @retval EFI_INVALID_PARAMETER If DevicePath, NamespaceId, or NamespaceUuid are NULL, then EFI_INVALID_PARAMETER\r
771 is returned.\r
772 @retval EFI_UNSUPPORTED If DevicePath is not a device path node type that the NVM Express Pass Thru driver\r
773 supports, then EFI_UNSUPPORTED is returned.\r
774 @retval EFI_NOT_FOUND If DevicePath is a device path node type that the Nvm Express Pass Thru driver\r
775 supports, but there is not a valid translation from DevicePath to a NamespaceID\r
776 and NamespaceUuid, then EFI_NOT_FOUND is returned.\r
777**/\r
778EFI_STATUS\r
779EFIAPI\r
780NvmExpressGetNamespace (\r
781 IN NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
782 IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
783 OUT UINT32 *NamespaceId,\r
784 OUT UINT64 *NamespaceUuid\r
785 )\r
786{\r
787 NVME_NAMESPACE_DEVICE_PATH *Node;\r
788\r
789 if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL) || (NamespaceUuid == NULL)) {\r
790 return EFI_INVALID_PARAMETER;\r
791 }\r
792\r
793 if (DevicePath->Type != MESSAGING_DEVICE_PATH) {\r
794 return EFI_UNSUPPORTED;\r
795 }\r
796\r
797 Node = (NVME_NAMESPACE_DEVICE_PATH *)DevicePath;\r
798\r
799 if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {\r
800 if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {\r
801 return EFI_NOT_FOUND;\r
802 }\r
803\r
804 *NamespaceId = Node->NamespaceId;\r
805 *NamespaceUuid = Node->NamespaceUuid;\r
806\r
807 return EFI_SUCCESS;\r
808 } else {\r
809 return EFI_UNSUPPORTED;\r
810 }\r
811}\r
812\r
813/**\r
814 Used to allocate and build a device path node for an NVM Express namespace on an NVM Express controller.\r
815\r
816 The NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device\r
817 path node for the NVM Express namespace specified by NamespaceId.\r
818\r
819 If the namespace device specified by NamespaceId is not valid , then EFI_NOT_FOUND is returned.\r
820\r
821 If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.\r
822\r
823 If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.\r
824\r
825 Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are\r
826 initialized to describe the NVM Express namespace specified by NamespaceId, and EFI_SUCCESS is returned.\r
827\r
828 @param[in] This A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
829 @param[in] NamespaceId The NVM Express namespace ID for which a device path node is to be\r
830 allocated and built. Caller must set the NamespaceId to zero if the\r
831 device path node will contain a valid UUID.\r
832 @param[in] NamespaceUuid The NVM Express namespace UUID for which a device path node is to be\r
833 allocated and built. UUID will only be valid of the Namespace ID is zero.\r
834 @param[in,out] DevicePath A pointer to a single device path node that describes the NVM Express\r
835 namespace specified by NamespaceId. This function is responsible for\r
836 allocating the buffer DevicePath with the boot service AllocatePool().\r
837 It is the caller's responsibility to free DevicePath when the caller\r
838 is finished with DevicePath.\r
839 @retval EFI_SUCCESS The device path node that describes the NVM Express namespace specified\r
840 by NamespaceId was allocated and returned in DevicePath.\r
841 @retval EFI_NOT_FOUND The NVM Express namespace specified by NamespaceId does not exist on the\r
842 NVM Express controller.\r
843 @retval EFI_INVALID_PARAMETER DevicePath is NULL.\r
844 @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate the DevicePath node.\r
845\r
846**/\r
847EFI_STATUS\r
848EFIAPI\r
849NvmExpressBuildDevicePath (\r
850 IN NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
851 IN UINT32 NamespaceId,\r
852 IN UINT64 NamespaceUuid,\r
853 IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
854 )\r
855{\r
eb290d02
FT		 856 NVME_NAMESPACE_DEVICE_PATH *Node;\r
857\r
858 //\r
859 // Validate parameters\r
860 //\r
861 if ((This == NULL) || (DevicePath == NULL)) {\r
862 return EFI_INVALID_PARAMETER;\r
863 }\r
864\r
eb290d02
FT		 865 if (NamespaceId == 0) {\r
866 return EFI_NOT_FOUND;\r
867 }\r
868\r
869 Node = (NVME_NAMESPACE_DEVICE_PATH *)AllocateZeroPool (sizeof (NVME_NAMESPACE_DEVICE_PATH));\r
870\r
871 if (Node == NULL) {\r
872 return EFI_OUT_OF_RESOURCES;\r
873 }\r
874\r
875 Node->Header.Type = MESSAGING_DEVICE_PATH;\r
876 Node->Header.SubType = MSG_NVME_NAMESPACE_DP;\r
877 SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));\r
878 Node->NamespaceId = NamespaceId;\r
879 Node->NamespaceUuid = NamespaceUuid;\r
880\r
881 *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;\r
882 return EFI_SUCCESS;\r
883}\r
884\r
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