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eb290d02 FT |
1 | /** @file\r |
2 | NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r | |
3 | NVM Express specification.\r | |
4 | \r | |
35f910f0 | 5 | (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>\r |
946f48eb | 6 | Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>\r |
eb290d02 FT |
7 | This program and the accompanying materials\r |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php.\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #include "NvmExpress.h"\r | |
18 | \r | |
eb290d02 FT |
19 | /**\r |
20 | Dump the execution status from a given completion queue entry.\r | |
21 | \r | |
22 | @param[in] Cq A pointer to the NVME_CQ item.\r | |
23 | \r | |
24 | **/\r | |
25 | VOID\r | |
26 | NvmeDumpStatus (\r | |
27 | IN NVME_CQ *Cq\r | |
28 | )\r | |
29 | {\r | |
30 | DEBUG ((EFI_D_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));\r | |
31 | \r | |
32 | DEBUG ((EFI_D_VERBOSE, " SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));\r | |
33 | \r | |
34 | DEBUG ((EFI_D_VERBOSE, " NVMe Cmd Execution Result - "));\r | |
35 | \r | |
36 | switch (Cq->Sct) {\r | |
37 | case 0x0:\r | |
38 | switch (Cq->Sc) {\r | |
39 | case 0x0:\r | |
40 | DEBUG ((EFI_D_VERBOSE, "Successful Completion\n"));\r | |
41 | break;\r | |
42 | case 0x1:\r | |
43 | DEBUG ((EFI_D_VERBOSE, "Invalid Command Opcode\n"));\r | |
44 | break;\r | |
45 | case 0x2:\r | |
46 | DEBUG ((EFI_D_VERBOSE, "Invalid Field in Command\n"));\r | |
47 | break;\r | |
48 | case 0x3:\r | |
49 | DEBUG ((EFI_D_VERBOSE, "Command ID Conflict\n"));\r | |
50 | break;\r | |
51 | case 0x4:\r | |
52 | DEBUG ((EFI_D_VERBOSE, "Data Transfer Error\n"));\r | |
53 | break;\r | |
54 | case 0x5:\r | |
55 | DEBUG ((EFI_D_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));\r | |
56 | break;\r | |
57 | case 0x6:\r | |
58 | DEBUG ((EFI_D_VERBOSE, "Internal Device Error\n"));\r | |
59 | break;\r | |
60 | case 0x7:\r | |
61 | DEBUG ((EFI_D_VERBOSE, "Command Abort Requested\n"));\r | |
62 | break;\r | |
63 | case 0x8:\r | |
64 | DEBUG ((EFI_D_VERBOSE, "Command Aborted due to SQ Deletion\n"));\r | |
65 | break;\r | |
66 | case 0x9:\r | |
67 | DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Failed Fused Command\n"));\r | |
68 | break;\r | |
69 | case 0xA:\r | |
70 | DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Missing Fused Command\n"));\r | |
71 | break;\r | |
72 | case 0xB:\r | |
73 | DEBUG ((EFI_D_VERBOSE, "Invalid Namespace or Format\n"));\r | |
74 | break;\r | |
75 | case 0xC:\r | |
76 | DEBUG ((EFI_D_VERBOSE, "Command Sequence Error\n"));\r | |
77 | break;\r | |
78 | case 0xD:\r | |
79 | DEBUG ((EFI_D_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));\r | |
80 | break;\r | |
81 | case 0xE:\r | |
82 | DEBUG ((EFI_D_VERBOSE, "Invalid Number of SGL Descriptors\n"));\r | |
83 | break;\r | |
84 | case 0xF:\r | |
85 | DEBUG ((EFI_D_VERBOSE, "Data SGL Length Invalid\n"));\r | |
86 | break;\r | |
87 | case 0x10:\r | |
88 | DEBUG ((EFI_D_VERBOSE, "Metadata SGL Length Invalid\n"));\r | |
89 | break;\r | |
90 | case 0x11:\r | |
91 | DEBUG ((EFI_D_VERBOSE, "SGL Descriptor Type Invalid\n"));\r | |
92 | break;\r | |
93 | case 0x80:\r | |
94 | DEBUG ((EFI_D_VERBOSE, "LBA Out of Range\n"));\r | |
95 | break;\r | |
96 | case 0x81:\r | |
97 | DEBUG ((EFI_D_VERBOSE, "Capacity Exceeded\n"));\r | |
98 | break;\r | |
99 | case 0x82:\r | |
100 | DEBUG ((EFI_D_VERBOSE, "Namespace Not Ready\n"));\r | |
101 | break;\r | |
102 | case 0x83:\r | |
103 | DEBUG ((EFI_D_VERBOSE, "Reservation Conflict\n"));\r | |
104 | break;\r | |
105 | }\r | |
106 | break;\r | |
107 | \r | |
108 | case 0x1:\r | |
109 | switch (Cq->Sc) {\r | |
110 | case 0x0:\r | |
111 | DEBUG ((EFI_D_VERBOSE, "Completion Queue Invalid\n"));\r | |
112 | break;\r | |
113 | case 0x1:\r | |
114 | DEBUG ((EFI_D_VERBOSE, "Invalid Queue Identifier\n"));\r | |
115 | break;\r | |
116 | case 0x2:\r | |
117 | DEBUG ((EFI_D_VERBOSE, "Maximum Queue Size Exceeded\n"));\r | |
118 | break;\r | |
119 | case 0x3:\r | |
120 | DEBUG ((EFI_D_VERBOSE, "Abort Command Limit Exceeded\n"));\r | |
121 | break;\r | |
122 | case 0x5:\r | |
123 | DEBUG ((EFI_D_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));\r | |
124 | break;\r | |
125 | case 0x6:\r | |
126 | DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Slot\n"));\r | |
127 | break;\r | |
128 | case 0x7:\r | |
129 | DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Image\n"));\r | |
130 | break;\r | |
131 | case 0x8:\r | |
132 | DEBUG ((EFI_D_VERBOSE, "Invalid Interrupt Vector\n"));\r | |
133 | break;\r | |
134 | case 0x9:\r | |
135 | DEBUG ((EFI_D_VERBOSE, "Invalid Log Page\n"));\r | |
136 | break;\r | |
137 | case 0xA:\r | |
138 | DEBUG ((EFI_D_VERBOSE, "Invalid Format\n"));\r | |
139 | break;\r | |
140 | case 0xB:\r | |
141 | DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires Conventional Reset\n"));\r | |
142 | break;\r | |
143 | case 0xC:\r | |
144 | DEBUG ((EFI_D_VERBOSE, "Invalid Queue Deletion\n"));\r | |
145 | break;\r | |
146 | case 0xD:\r | |
147 | DEBUG ((EFI_D_VERBOSE, "Feature Identifier Not Saveable\n"));\r | |
148 | break;\r | |
149 | case 0xE:\r | |
150 | DEBUG ((EFI_D_VERBOSE, "Feature Not Changeable\n"));\r | |
151 | break;\r | |
152 | case 0xF:\r | |
153 | DEBUG ((EFI_D_VERBOSE, "Feature Not Namespace Specific\n"));\r | |
154 | break;\r | |
155 | case 0x10:\r | |
156 | DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));\r | |
157 | break;\r | |
158 | case 0x80:\r | |
159 | DEBUG ((EFI_D_VERBOSE, "Conflicting Attributes\n"));\r | |
160 | break;\r | |
161 | case 0x81:\r | |
162 | DEBUG ((EFI_D_VERBOSE, "Invalid Protection Information\n"));\r | |
163 | break;\r | |
164 | case 0x82:\r | |
165 | DEBUG ((EFI_D_VERBOSE, "Attempted Write to Read Only Range\n"));\r | |
166 | break;\r | |
167 | }\r | |
168 | break;\r | |
169 | \r | |
170 | case 0x2:\r | |
171 | switch (Cq->Sc) {\r | |
172 | case 0x80:\r | |
173 | DEBUG ((EFI_D_VERBOSE, "Write Fault\n"));\r | |
174 | break;\r | |
175 | case 0x81:\r | |
176 | DEBUG ((EFI_D_VERBOSE, "Unrecovered Read Error\n"));\r | |
177 | break;\r | |
178 | case 0x82:\r | |
179 | DEBUG ((EFI_D_VERBOSE, "End-to-end Guard Check Error\n"));\r | |
180 | break;\r | |
181 | case 0x83:\r | |
182 | DEBUG ((EFI_D_VERBOSE, "End-to-end Application Tag Check Error\n"));\r | |
183 | break;\r | |
184 | case 0x84:\r | |
185 | DEBUG ((EFI_D_VERBOSE, "End-to-end Reference Tag Check Error\n"));\r | |
186 | break;\r | |
187 | case 0x85:\r | |
188 | DEBUG ((EFI_D_VERBOSE, "Compare Failure\n"));\r | |
189 | break;\r | |
190 | case 0x86:\r | |
191 | DEBUG ((EFI_D_VERBOSE, "Access Denied\n"));\r | |
192 | break;\r | |
193 | }\r | |
194 | break;\r | |
195 | \r | |
196 | default:\r | |
197 | break;\r | |
198 | }\r | |
199 | }\r | |
200 | \r | |
201 | /**\r | |
202 | Create PRP lists for data transfer which is larger than 2 memory pages.\r | |
203 | Note here we calcuate the number of required PRP lists and allocate them at one time.\r | |
204 | \r | |
205 | @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
206 | @param[in] PhysicalAddr The physical base address of data buffer.\r | |
207 | @param[in] Pages The number of pages to be transfered.\r | |
208 | @param[out] PrpListHost The host base address of PRP lists.\r | |
209 | @param[in,out] PrpListNo The number of PRP List.\r | |
210 | @param[out] Mapping The mapping value returned from PciIo.Map().\r | |
211 | \r | |
212 | @retval The pointer to the first PRP List of the PRP lists.\r | |
213 | \r | |
214 | **/\r | |
215 | VOID*\r | |
216 | NvmeCreatePrpList (\r | |
217 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
218 | IN EFI_PHYSICAL_ADDRESS PhysicalAddr,\r | |
219 | IN UINTN Pages,\r | |
220 | OUT VOID **PrpListHost,\r | |
221 | IN OUT UINTN *PrpListNo,\r | |
222 | OUT VOID **Mapping\r | |
223 | )\r | |
224 | {\r | |
225 | UINTN PrpEntryNo;\r | |
226 | UINT64 PrpListBase;\r | |
227 | UINTN PrpListIndex;\r | |
228 | UINTN PrpEntryIndex;\r | |
229 | UINT64 Remainder;\r | |
230 | EFI_PHYSICAL_ADDRESS PrpListPhyAddr;\r | |
231 | UINTN Bytes;\r | |
232 | EFI_STATUS Status;\r | |
233 | \r | |
234 | //\r | |
235 | // The number of Prp Entry in a memory page.\r | |
236 | //\r | |
237 | PrpEntryNo = EFI_PAGE_SIZE / sizeof (UINT64);\r | |
238 | \r | |
239 | //\r | |
240 | // Calculate total PrpList number.\r | |
241 | //\r | |
769402ef FT |
242 | *PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo - 1, &Remainder);\r |
243 | if (*PrpListNo == 0) {\r | |
244 | *PrpListNo = 1;\r | |
a9ec6d65 | 245 | } else if ((Remainder != 0) && (Remainder != 1)) {\r |
eb290d02 | 246 | *PrpListNo += 1;\r |
769402ef FT |
247 | } else if (Remainder == 1) {\r |
248 | Remainder = PrpEntryNo;\r | |
249 | } else if (Remainder == 0) {\r | |
250 | Remainder = PrpEntryNo - 1;\r | |
eb290d02 FT |
251 | }\r |
252 | \r | |
253 | Status = PciIo->AllocateBuffer (\r | |
254 | PciIo,\r | |
255 | AllocateAnyPages,\r | |
256 | EfiBootServicesData,\r | |
257 | *PrpListNo,\r | |
258 | PrpListHost,\r | |
259 | 0\r | |
260 | );\r | |
261 | \r | |
262 | if (EFI_ERROR (Status)) {\r | |
263 | return NULL;\r | |
264 | }\r | |
265 | \r | |
266 | Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);\r | |
267 | Status = PciIo->Map (\r | |
268 | PciIo,\r | |
269 | EfiPciIoOperationBusMasterCommonBuffer,\r | |
270 | *PrpListHost,\r | |
271 | &Bytes,\r | |
272 | &PrpListPhyAddr,\r | |
273 | Mapping\r | |
274 | );\r | |
275 | \r | |
276 | if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (*PrpListNo))) {\r | |
277 | DEBUG ((EFI_D_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));\r | |
278 | goto EXIT;\r | |
279 | }\r | |
280 | //\r | |
281 | // Fill all PRP lists except of last one.\r | |
282 | //\r | |
283 | ZeroMem (*PrpListHost, Bytes);\r | |
284 | for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {\r | |
769402ef | 285 | PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r |
eb290d02 FT |
286 | \r |
287 | for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {\r | |
288 | if (PrpEntryIndex != PrpEntryNo - 1) {\r | |
289 | //\r | |
290 | // Fill all PRP entries except of last one.\r | |
291 | //\r | |
292 | *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r | |
293 | PhysicalAddr += EFI_PAGE_SIZE;\r | |
294 | } else {\r | |
295 | //\r | |
296 | // Fill last PRP entries with next PRP List pointer.\r | |
297 | //\r | |
298 | *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;\r | |
299 | }\r | |
300 | }\r | |
301 | }\r | |
302 | //\r | |
303 | // Fill last PRP list.\r | |
304 | //\r | |
305 | PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r | |
769402ef | 306 | for (PrpEntryIndex = 0; PrpEntryIndex < Remainder; ++PrpEntryIndex) {\r |
eb290d02 FT |
307 | *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r |
308 | PhysicalAddr += EFI_PAGE_SIZE;\r | |
309 | }\r | |
310 | \r | |
311 | return (VOID*)(UINTN)PrpListPhyAddr;\r | |
312 | \r | |
313 | EXIT:\r | |
314 | PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);\r | |
315 | return NULL;\r | |
316 | }\r | |
317 | \r | |
318 | \r | |
319 | /**\r | |
320 | Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports\r | |
d6c55989 | 321 | both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking\r |
eb290d02 FT |
322 | I/O functionality is optional.\r |
323 | \r | |
d6c55989 FT |
324 | \r |
325 | @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r | |
326 | @param[in] NamespaceId A 32 bit namespace ID as defined in the NVMe specification to which the NVM Express Command\r | |
327 | Packet will be sent. A value of 0 denotes the NVM Express controller, a value of all 0xFF's\r | |
328 | (all bytes are 0xFF) in the namespace ID specifies that the command packet should be sent to\r | |
329 | all valid namespaces.\r | |
330 | @param[in,out] Packet A pointer to the NVM Express Command Packet.\r | |
331 | @param[in] Event If non-blocking I/O is not supported then Event is ignored, and blocking I/O is performed.\r | |
332 | If Event is NULL, then blocking I/O is performed. If Event is not NULL and non-blocking I/O\r | |
333 | is supported, then non-blocking I/O is performed, and Event will be signaled when the NVM\r | |
eb290d02 FT |
334 | Express Command Packet completes.\r |
335 | \r | |
336 | @retval EFI_SUCCESS The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred\r | |
337 | to, or from DataBuffer.\r | |
338 | @retval EFI_BAD_BUFFER_SIZE The NVM Express Command Packet was not executed. The number of bytes that could be transferred\r | |
339 | is returned in TransferLength.\r | |
340 | @retval EFI_NOT_READY The NVM Express Command Packet could not be sent because the controller is not ready. The caller\r | |
341 | may retry again later.\r | |
342 | @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the NVM Express Command Packet.\r | |
d6c55989 | 343 | @retval EFI_INVALID_PARAMETER NamespaceId or the contents of EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM\r |
eb290d02 | 344 | Express Command Packet was not sent, so no additional status information is available.\r |
d6c55989 FT |
345 | @retval EFI_UNSUPPORTED The command described by the NVM Express Command Packet is not supported by the NVM Express\r |
346 | controller. The NVM Express Command Packet was not sent so no additional status information\r | |
347 | is available.\r | |
eb290d02 FT |
348 | @retval EFI_TIMEOUT A timeout occurred while waiting for the NVM Express Command Packet to execute.\r |
349 | \r | |
350 | **/\r | |
351 | EFI_STATUS\r | |
352 | EFIAPI\r | |
353 | NvmExpressPassThru (\r | |
d6c55989 | 354 | IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r |
eb290d02 | 355 | IN UINT32 NamespaceId,\r |
d6c55989 | 356 | IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,\r |
eb290d02 FT |
357 | IN EFI_EVENT Event OPTIONAL\r |
358 | )\r | |
359 | {\r | |
3c52deaf HW |
360 | NVME_CONTROLLER_PRIVATE_DATA *Private;\r |
361 | EFI_STATUS Status;\r | |
362 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
363 | NVME_SQ *Sq;\r | |
364 | NVME_CQ *Cq;\r | |
365 | UINT16 QueueId;\r | |
366 | UINT32 Bytes;\r | |
367 | UINT16 Offset;\r | |
368 | EFI_EVENT TimerEvent;\r | |
369 | EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r | |
370 | EFI_PHYSICAL_ADDRESS PhyAddr;\r | |
371 | VOID *MapData;\r | |
372 | VOID *MapMeta;\r | |
373 | VOID *MapPrpList;\r | |
374 | UINTN MapLength;\r | |
375 | UINT64 *Prp;\r | |
376 | VOID *PrpListHost;\r | |
377 | UINTN PrpListNo;\r | |
378 | UINT32 IoAlign;\r | |
379 | UINT32 Data;\r | |
380 | NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;\r | |
381 | EFI_TPL OldTpl;\r | |
eb290d02 FT |
382 | \r |
383 | //\r | |
384 | // check the data fields in Packet parameter.\r | |
385 | //\r | |
386 | if ((This == NULL) || (Packet == NULL)) {\r | |
387 | return EFI_INVALID_PARAMETER;\r | |
388 | }\r | |
389 | \r | |
d6c55989 | 390 | if ((Packet->NvmeCmd == NULL) || (Packet->NvmeCompletion == NULL)) {\r |
eb290d02 FT |
391 | return EFI_INVALID_PARAMETER;\r |
392 | }\r | |
393 | \r | |
d6c55989 | 394 | if (Packet->QueueType != NVME_ADMIN_QUEUE && Packet->QueueType != NVME_IO_QUEUE) {\r |
eb290d02 FT |
395 | return EFI_INVALID_PARAMETER;\r |
396 | }\r | |
397 | \r | |
3c52deaf HW |
398 | //\r |
399 | // Buffer alignment check for TransferBuffer & MetadataBuffer.\r | |
400 | //\r | |
401 | IoAlign = This->Mode->IoAlign;\r | |
402 | if (IoAlign > 0 && (((UINTN) Packet->TransferBuffer & (IoAlign - 1)) != 0)) {\r | |
403 | return EFI_INVALID_PARAMETER;\r | |
404 | }\r | |
405 | \r | |
406 | if (IoAlign > 0 && (((UINTN) Packet->MetadataBuffer & (IoAlign - 1)) != 0)) {\r | |
407 | return EFI_INVALID_PARAMETER;\r | |
408 | }\r | |
409 | \r | |
eb290d02 FT |
410 | Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r |
411 | PciIo = Private->PciIo;\r | |
412 | MapData = NULL;\r | |
413 | MapMeta = NULL;\r | |
414 | MapPrpList = NULL;\r | |
415 | PrpListHost = NULL;\r | |
416 | PrpListNo = 0;\r | |
417 | Prp = NULL;\r | |
418 | TimerEvent = NULL;\r | |
419 | Status = EFI_SUCCESS;\r | |
420 | \r | |
758ea946 HW |
421 | if (Packet->QueueType == NVME_ADMIN_QUEUE) {\r |
422 | QueueId = 0;\r | |
423 | } else {\r | |
424 | if (Event == NULL) {\r | |
425 | QueueId = 1;\r | |
426 | } else {\r | |
427 | QueueId = 2;\r | |
428 | \r | |
429 | //\r | |
430 | // Submission queue full check.\r | |
431 | //\r | |
432 | if ((Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1) ==\r | |
433 | Private->AsyncSqHead) {\r | |
434 | return EFI_NOT_READY;\r | |
435 | }\r | |
436 | }\r | |
437 | }\r | |
438 | Sq = Private->SqBuffer[QueueId] + Private->SqTdbl[QueueId].Sqt;\r | |
439 | Cq = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;\r | |
eb290d02 FT |
440 | \r |
441 | if (Packet->NvmeCmd->Nsid != NamespaceId) {\r | |
442 | return EFI_INVALID_PARAMETER;\r | |
443 | }\r | |
444 | \r | |
445 | ZeroMem (Sq, sizeof (NVME_SQ));\r | |
d6c55989 FT |
446 | Sq->Opc = (UINT8)Packet->NvmeCmd->Cdw0.Opcode;\r |
447 | Sq->Fuse = (UINT8)Packet->NvmeCmd->Cdw0.FusedOperation;\r | |
758ea946 | 448 | Sq->Cid = Private->Cid[QueueId]++;\r |
eb290d02 FT |
449 | Sq->Nsid = Packet->NvmeCmd->Nsid;\r |
450 | \r | |
451 | //\r | |
452 | // Currently we only support PRP for data transfer, SGL is NOT supported.\r | |
453 | //\r | |
7b8883c6 FT |
454 | ASSERT (Sq->Psdt == 0);\r |
455 | if (Sq->Psdt != 0) {\r | |
eb290d02 FT |
456 | DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));\r |
457 | return EFI_UNSUPPORTED;\r | |
458 | }\r | |
459 | \r | |
460 | Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;\r | |
461 | //\r | |
462 | // If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.\r | |
463 | // Note here we don't handle data buffer for CreateIOSubmitionQueue and CreateIOCompletionQueue cmds because\r | |
464 | // these two cmds are special which requires their data buffer must support simultaneous access by both the\r | |
465 | // processor and a PCI Bus Master. It's caller's responsbility to ensure this.\r | |
466 | //\r | |
754b489b | 467 | if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_CMD) && (Sq->Opc != NVME_ADMIN_CRIOSQ_CMD)) {\r |
eb290d02 FT |
468 | if ((Sq->Opc & BIT0) != 0) {\r |
469 | Flag = EfiPciIoOperationBusMasterRead;\r | |
470 | } else {\r | |
471 | Flag = EfiPciIoOperationBusMasterWrite;\r | |
472 | }\r | |
473 | \r | |
474 | MapLength = Packet->TransferLength;\r | |
475 | Status = PciIo->Map (\r | |
476 | PciIo,\r | |
477 | Flag,\r | |
478 | Packet->TransferBuffer,\r | |
479 | &MapLength,\r | |
480 | &PhyAddr,\r | |
481 | &MapData\r | |
482 | );\r | |
483 | if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {\r | |
484 | return EFI_OUT_OF_RESOURCES;\r | |
485 | }\r | |
486 | \r | |
487 | Sq->Prp[0] = PhyAddr;\r | |
488 | Sq->Prp[1] = 0;\r | |
489 | \r | |
490 | MapLength = Packet->MetadataLength;\r | |
491 | if(Packet->MetadataBuffer != NULL) {\r | |
492 | MapLength = Packet->MetadataLength;\r | |
493 | Status = PciIo->Map (\r | |
494 | PciIo,\r | |
495 | Flag,\r | |
496 | Packet->MetadataBuffer,\r | |
497 | &MapLength,\r | |
498 | &PhyAddr,\r | |
499 | &MapMeta\r | |
500 | );\r | |
501 | if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {\r | |
502 | PciIo->Unmap (\r | |
503 | PciIo,\r | |
504 | MapData\r | |
505 | );\r | |
506 | \r | |
507 | return EFI_OUT_OF_RESOURCES;\r | |
508 | }\r | |
509 | Sq->Mptr = PhyAddr;\r | |
510 | }\r | |
511 | }\r | |
512 | //\r | |
513 | // If the buffer size spans more than two memory pages (page size as defined in CC.Mps),\r | |
514 | // then build a PRP list in the second PRP submission queue entry.\r | |
515 | //\r | |
516 | Offset = ((UINT16)Sq->Prp[0]) & (EFI_PAGE_SIZE - 1);\r | |
517 | Bytes = Packet->TransferLength;\r | |
518 | \r | |
519 | if ((Offset + Bytes) > (EFI_PAGE_SIZE * 2)) {\r | |
520 | //\r | |
521 | // Create PrpList for remaining data buffer.\r | |
522 | //\r | |
523 | PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r | |
524 | Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);\r | |
525 | if (Prp == NULL) {\r | |
526 | goto EXIT;\r | |
527 | }\r | |
528 | \r | |
529 | Sq->Prp[1] = (UINT64)(UINTN)Prp;\r | |
530 | } else if ((Offset + Bytes) > EFI_PAGE_SIZE) {\r | |
531 | Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r | |
532 | }\r | |
533 | \r | |
d6c55989 FT |
534 | if(Packet->NvmeCmd->Flags & CDW2_VALID) {\r |
535 | Sq->Rsvd2 = (UINT64)Packet->NvmeCmd->Cdw2;\r | |
536 | }\r | |
537 | if(Packet->NvmeCmd->Flags & CDW3_VALID) {\r | |
538 | Sq->Rsvd2 |= LShiftU64 ((UINT64)Packet->NvmeCmd->Cdw3, 32);\r | |
539 | }\r | |
eb290d02 FT |
540 | if(Packet->NvmeCmd->Flags & CDW10_VALID) {\r |
541 | Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;\r | |
542 | }\r | |
543 | if(Packet->NvmeCmd->Flags & CDW11_VALID) {\r | |
544 | Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;\r | |
545 | }\r | |
546 | if(Packet->NvmeCmd->Flags & CDW12_VALID) {\r | |
547 | Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;\r | |
548 | }\r | |
549 | if(Packet->NvmeCmd->Flags & CDW13_VALID) {\r | |
550 | Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;\r | |
551 | }\r | |
552 | if(Packet->NvmeCmd->Flags & CDW14_VALID) {\r | |
553 | Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;\r | |
554 | }\r | |
555 | if(Packet->NvmeCmd->Flags & CDW15_VALID) {\r | |
556 | Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;\r | |
557 | }\r | |
558 | \r | |
559 | //\r | |
560 | // Ring the submission queue doorbell.\r | |
561 | //\r | |
758ea946 HW |
562 | if (Event != NULL) {\r |
563 | Private->SqTdbl[QueueId].Sqt =\r | |
564 | (Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1);\r | |
565 | } else {\r | |
566 | Private->SqTdbl[QueueId].Sqt ^= 1;\r | |
567 | }\r | |
568 | Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[QueueId]);\r | |
eb290d02 FT |
569 | PciIo->Mem.Write (\r |
570 | PciIo,\r | |
571 | EfiPciIoWidthUint32,\r | |
572 | NVME_BAR,\r | |
758ea946 | 573 | NVME_SQTDBL_OFFSET(QueueId, Private->Cap.Dstrd),\r |
eb290d02 | 574 | 1,\r |
7b8883c6 | 575 | &Data\r |
eb290d02 FT |
576 | );\r |
577 | \r | |
758ea946 HW |
578 | //\r |
579 | // For non-blocking requests, return directly if the command is placed\r | |
580 | // in the submission queue.\r | |
581 | //\r | |
582 | if (Event != NULL) {\r | |
583 | AsyncRequest = AllocateZeroPool (sizeof (NVME_PASS_THRU_ASYNC_REQ));\r | |
584 | if (AsyncRequest == NULL) {\r | |
585 | Status = EFI_DEVICE_ERROR;\r | |
586 | goto EXIT;\r | |
587 | }\r | |
588 | \r | |
589 | AsyncRequest->Signature = NVME_PASS_THRU_ASYNC_REQ_SIG;\r | |
590 | AsyncRequest->Packet = Packet;\r | |
591 | AsyncRequest->CommandId = Sq->Cid;\r | |
592 | AsyncRequest->CallerEvent = Event;\r | |
593 | \r | |
594 | OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r | |
595 | InsertTailList (&Private->AsyncPassThruQueue, &AsyncRequest->Link);\r | |
596 | gBS->RestoreTPL (OldTpl);\r | |
597 | \r | |
598 | return EFI_SUCCESS;\r | |
599 | }\r | |
600 | \r | |
eb290d02 FT |
601 | Status = gBS->CreateEvent (\r |
602 | EVT_TIMER,\r | |
603 | TPL_CALLBACK,\r | |
604 | NULL,\r | |
605 | NULL,\r | |
606 | &TimerEvent\r | |
607 | );\r | |
608 | if (EFI_ERROR (Status)) {\r | |
609 | goto EXIT;\r | |
610 | }\r | |
611 | \r | |
612 | Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);\r | |
613 | \r | |
614 | if (EFI_ERROR(Status)) {\r | |
eb290d02 FT |
615 | goto EXIT;\r |
616 | }\r | |
617 | \r | |
618 | //\r | |
619 | // Wait for completion queue to get filled in.\r | |
620 | //\r | |
621 | Status = EFI_TIMEOUT;\r | |
eb290d02 | 622 | while (EFI_ERROR (gBS->CheckEvent (TimerEvent))) {\r |
758ea946 | 623 | if (Cq->Pt != Private->Pt[QueueId]) {\r |
eb290d02 | 624 | Status = EFI_SUCCESS;\r |
eb290d02 FT |
625 | break;\r |
626 | }\r | |
627 | }\r | |
628 | \r | |
eb290d02 | 629 | //\r |
754b489b | 630 | // Check the NVMe cmd execution result\r |
eb290d02 | 631 | //\r |
754b489b TF |
632 | if (Status != EFI_TIMEOUT) {\r |
633 | if ((Cq->Sct == 0) && (Cq->Sc == 0)) {\r | |
634 | Status = EFI_SUCCESS;\r | |
635 | } else {\r | |
636 | Status = EFI_DEVICE_ERROR;\r | |
637 | //\r | |
638 | // Copy the Respose Queue entry for this command to the callers response buffer\r | |
639 | //\r | |
640 | CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));\r | |
641 | \r | |
642 | //\r | |
643 | // Dump every completion entry status for debugging.\r | |
644 | //\r | |
645 | DEBUG_CODE_BEGIN();\r | |
646 | NvmeDumpStatus(Cq);\r | |
647 | DEBUG_CODE_END();\r | |
648 | }\r | |
649 | }\r | |
eb290d02 | 650 | \r |
758ea946 HW |
651 | if ((Private->CqHdbl[QueueId].Cqh ^= 1) == 0) {\r |
652 | Private->Pt[QueueId] ^= 1;\r | |
754b489b | 653 | }\r |
eb290d02 | 654 | \r |
758ea946 | 655 | Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]);\r |
eb290d02 FT |
656 | PciIo->Mem.Write (\r |
657 | PciIo,\r | |
658 | EfiPciIoWidthUint32,\r | |
659 | NVME_BAR,\r | |
758ea946 | 660 | NVME_CQHDBL_OFFSET(QueueId, Private->Cap.Dstrd),\r |
eb290d02 | 661 | 1,\r |
7b8883c6 | 662 | &Data\r |
eb290d02 FT |
663 | );\r |
664 | \r | |
665 | EXIT:\r | |
666 | if (MapData != NULL) {\r | |
667 | PciIo->Unmap (\r | |
668 | PciIo,\r | |
669 | MapData\r | |
670 | );\r | |
671 | }\r | |
672 | \r | |
673 | if (MapMeta != NULL) {\r | |
674 | PciIo->Unmap (\r | |
675 | PciIo,\r | |
676 | MapMeta\r | |
677 | );\r | |
678 | }\r | |
679 | \r | |
680 | if (MapPrpList != NULL) {\r | |
681 | PciIo->Unmap (\r | |
682 | PciIo,\r | |
683 | MapPrpList\r | |
684 | );\r | |
685 | }\r | |
686 | \r | |
687 | if (Prp != NULL) {\r | |
688 | PciIo->FreeBuffer (PciIo, PrpListNo, PrpListHost);\r | |
689 | }\r | |
690 | \r | |
691 | if (TimerEvent != NULL) {\r | |
692 | gBS->CloseEvent (TimerEvent);\r | |
693 | }\r | |
694 | return Status;\r | |
695 | }\r | |
696 | \r | |
697 | /**\r | |
d6c55989 | 698 | Used to retrieve the next namespace ID for this NVM Express controller.\r |
eb290d02 | 699 | \r |
d6c55989 FT |
700 | The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves the next valid\r |
701 | namespace ID on this NVM Express controller.\r | |
eb290d02 | 702 | \r |
d6c55989 FT |
703 | If on input the value pointed to by NamespaceId is 0xFFFFFFFF, then the first valid namespace\r |
704 | ID defined on the NVM Express controller is returned in the location pointed to by NamespaceId\r | |
705 | and a status of EFI_SUCCESS is returned.\r | |
eb290d02 | 706 | \r |
d6c55989 FT |
707 | If on input the value pointed to by NamespaceId is an invalid namespace ID other than 0xFFFFFFFF,\r |
708 | then EFI_INVALID_PARAMETER is returned.\r | |
eb290d02 | 709 | \r |
d6c55989 FT |
710 | If on input the value pointed to by NamespaceId is a valid namespace ID, then the next valid\r |
711 | namespace ID on the NVM Express controller is returned in the location pointed to by NamespaceId,\r | |
712 | and EFI_SUCCESS is returned.\r | |
eb290d02 | 713 | \r |
d6c55989 FT |
714 | If the value pointed to by NamespaceId is the namespace ID of the last namespace on the NVM\r |
715 | Express controller, then EFI_NOT_FOUND is returned.\r | |
716 | \r | |
717 | @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r | |
eb290d02 FT |
718 | @param[in,out] NamespaceId On input, a pointer to a legal NamespaceId for an NVM Express\r |
719 | namespace present on the NVM Express controller. On output, a\r | |
720 | pointer to the next NamespaceId of an NVM Express namespace on\r | |
721 | an NVM Express controller. An input value of 0xFFFFFFFF retrieves\r | |
722 | the first NamespaceId for an NVM Express namespace present on an\r | |
723 | NVM Express controller.\r | |
eb290d02 | 724 | \r |
d6c55989 | 725 | @retval EFI_SUCCESS The Namespace ID of the next Namespace was returned.\r |
eb290d02 | 726 | @retval EFI_NOT_FOUND There are no more namespaces defined on this controller.\r |
d6c55989 | 727 | @retval EFI_INVALID_PARAMETER NamespaceId is an invalid value other than 0xFFFFFFFF.\r |
eb290d02 FT |
728 | \r |
729 | **/\r | |
730 | EFI_STATUS\r | |
731 | EFIAPI\r | |
732 | NvmExpressGetNextNamespace (\r | |
d6c55989 FT |
733 | IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r |
734 | IN OUT UINT32 *NamespaceId\r | |
eb290d02 FT |
735 | )\r |
736 | {\r | |
737 | NVME_CONTROLLER_PRIVATE_DATA *Private;\r | |
738 | NVME_ADMIN_NAMESPACE_DATA *NamespaceData;\r | |
739 | UINT32 NextNamespaceId;\r | |
740 | EFI_STATUS Status;\r | |
741 | \r | |
742 | if ((This == NULL) || (NamespaceId == NULL)) {\r | |
743 | return EFI_INVALID_PARAMETER;\r | |
744 | }\r | |
745 | \r | |
746 | NamespaceData = NULL;\r | |
747 | Status = EFI_NOT_FOUND;\r | |
748 | \r | |
749 | Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r | |
750 | //\r | |
751 | // If the NamespaceId input value is 0xFFFFFFFF, then get the first valid namespace ID\r | |
752 | //\r | |
753 | if (*NamespaceId == 0xFFFFFFFF) {\r | |
754 | //\r | |
755 | // Start with the first namespace ID\r | |
756 | //\r | |
757 | NextNamespaceId = 1;\r | |
758 | //\r | |
759 | // Allocate buffer for Identify Namespace data.\r | |
760 | //\r | |
761 | NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r | |
762 | \r | |
763 | if (NamespaceData == NULL) {\r | |
764 | return EFI_NOT_FOUND;\r | |
765 | }\r | |
766 | \r | |
767 | Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r | |
768 | if (EFI_ERROR(Status)) {\r | |
769 | goto Done;\r | |
770 | }\r | |
771 | \r | |
772 | *NamespaceId = NextNamespaceId;\r | |
eb290d02 | 773 | } else {\r |
114358ea | 774 | if (*NamespaceId > Private->ControllerData->Nn) {\r |
eb290d02 FT |
775 | return EFI_INVALID_PARAMETER;\r |
776 | }\r | |
777 | \r | |
778 | NextNamespaceId = *NamespaceId + 1;\r | |
114358ea HW |
779 | if (NextNamespaceId > Private->ControllerData->Nn) {\r |
780 | return EFI_NOT_FOUND;\r | |
781 | }\r | |
782 | \r | |
eb290d02 FT |
783 | //\r |
784 | // Allocate buffer for Identify Namespace data.\r | |
785 | //\r | |
786 | NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r | |
787 | if (NamespaceData == NULL) {\r | |
788 | return EFI_NOT_FOUND;\r | |
789 | }\r | |
790 | \r | |
791 | Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r | |
792 | if (EFI_ERROR(Status)) {\r | |
793 | goto Done;\r | |
794 | }\r | |
795 | \r | |
796 | *NamespaceId = NextNamespaceId;\r | |
eb290d02 FT |
797 | }\r |
798 | \r | |
799 | Done:\r | |
800 | if (NamespaceData != NULL) {\r | |
801 | FreePool(NamespaceData);\r | |
802 | }\r | |
803 | \r | |
804 | return Status;\r | |
805 | }\r | |
806 | \r | |
807 | /**\r | |
d6c55989 FT |
808 | Used to translate a device path node to a namespace ID.\r |
809 | \r | |
810 | The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() function determines the namespace ID associated with the\r | |
811 | namespace described by DevicePath.\r | |
eb290d02 | 812 | \r |
d6c55989 FT |
813 | If DevicePath is a device path node type that the NVM Express Pass Thru driver supports, then the NVM Express\r |
814 | Pass Thru driver will attempt to translate the contents DevicePath into a namespace ID.\r | |
eb290d02 | 815 | \r |
d6c55989 FT |
816 | If this translation is successful, then that namespace ID is returned in NamespaceId, and EFI_SUCCESS is returned\r |
817 | \r | |
818 | @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r | |
eb290d02 FT |
819 | @param[in] DevicePath A pointer to the device path node that describes an NVM Express namespace on\r |
820 | the NVM Express controller.\r | |
821 | @param[out] NamespaceId The NVM Express namespace ID contained in the device path node.\r | |
eb290d02 | 822 | \r |
d6c55989 FT |
823 | @retval EFI_SUCCESS DevicePath was successfully translated to NamespaceId.\r |
824 | @retval EFI_INVALID_PARAMETER If DevicePath or NamespaceId are NULL, then EFI_INVALID_PARAMETER is returned.\r | |
eb290d02 FT |
825 | @retval EFI_UNSUPPORTED If DevicePath is not a device path node type that the NVM Express Pass Thru driver\r |
826 | supports, then EFI_UNSUPPORTED is returned.\r | |
d6c55989 FT |
827 | @retval EFI_NOT_FOUND If DevicePath is a device path node type that the NVM Express Pass Thru driver\r |
828 | supports, but there is not a valid translation from DevicePath to a namespace ID,\r | |
829 | then EFI_NOT_FOUND is returned.\r | |
eb290d02 FT |
830 | **/\r |
831 | EFI_STATUS\r | |
832 | EFIAPI\r | |
833 | NvmExpressGetNamespace (\r | |
d6c55989 | 834 | IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r |
eb290d02 | 835 | IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r |
d6c55989 | 836 | OUT UINT32 *NamespaceId\r |
eb290d02 FT |
837 | )\r |
838 | {\r | |
839 | NVME_NAMESPACE_DEVICE_PATH *Node;\r | |
284dc9bf | 840 | NVME_CONTROLLER_PRIVATE_DATA *Private;\r |
eb290d02 | 841 | \r |
d6c55989 | 842 | if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL)) {\r |
eb290d02 FT |
843 | return EFI_INVALID_PARAMETER;\r |
844 | }\r | |
845 | \r | |
846 | if (DevicePath->Type != MESSAGING_DEVICE_PATH) {\r | |
847 | return EFI_UNSUPPORTED;\r | |
848 | }\r | |
849 | \r | |
284dc9bf HW |
850 | Node = (NVME_NAMESPACE_DEVICE_PATH *)DevicePath;\r |
851 | Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r | |
eb290d02 FT |
852 | \r |
853 | if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {\r | |
854 | if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {\r | |
855 | return EFI_NOT_FOUND;\r | |
856 | }\r | |
857 | \r | |
284dc9bf HW |
858 | //\r |
859 | // Check NamespaceId in the device path node is valid or not.\r | |
860 | //\r | |
861 | if ((Node->NamespaceId == 0) ||\r | |
862 | (Node->NamespaceId > Private->ControllerData->Nn)) {\r | |
863 | return EFI_NOT_FOUND;\r | |
864 | }\r | |
865 | \r | |
d6c55989 | 866 | *NamespaceId = Node->NamespaceId;\r |
eb290d02 FT |
867 | \r |
868 | return EFI_SUCCESS;\r | |
869 | } else {\r | |
870 | return EFI_UNSUPPORTED;\r | |
871 | }\r | |
872 | }\r | |
873 | \r | |
874 | /**\r | |
875 | Used to allocate and build a device path node for an NVM Express namespace on an NVM Express controller.\r | |
876 | \r | |
d6c55989 | 877 | The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device\r |
eb290d02 FT |
878 | path node for the NVM Express namespace specified by NamespaceId.\r |
879 | \r | |
d6c55989 | 880 | If the NamespaceId is not valid, then EFI_NOT_FOUND is returned.\r |
eb290d02 FT |
881 | \r |
882 | If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.\r | |
883 | \r | |
884 | If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.\r | |
885 | \r | |
886 | Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are\r | |
887 | initialized to describe the NVM Express namespace specified by NamespaceId, and EFI_SUCCESS is returned.\r | |
888 | \r | |
d6c55989 | 889 | @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r |
eb290d02 FT |
890 | @param[in] NamespaceId The NVM Express namespace ID for which a device path node is to be\r |
891 | allocated and built. Caller must set the NamespaceId to zero if the\r | |
892 | device path node will contain a valid UUID.\r | |
eb290d02 FT |
893 | @param[in,out] DevicePath A pointer to a single device path node that describes the NVM Express\r |
894 | namespace specified by NamespaceId. This function is responsible for\r | |
895 | allocating the buffer DevicePath with the boot service AllocatePool().\r | |
896 | It is the caller's responsibility to free DevicePath when the caller\r | |
897 | is finished with DevicePath.\r | |
898 | @retval EFI_SUCCESS The device path node that describes the NVM Express namespace specified\r | |
899 | by NamespaceId was allocated and returned in DevicePath.\r | |
d6c55989 | 900 | @retval EFI_NOT_FOUND The NamespaceId is not valid.\r |
eb290d02 FT |
901 | @retval EFI_INVALID_PARAMETER DevicePath is NULL.\r |
902 | @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate the DevicePath node.\r | |
903 | \r | |
904 | **/\r | |
905 | EFI_STATUS\r | |
906 | EFIAPI\r | |
907 | NvmExpressBuildDevicePath (\r | |
d6c55989 | 908 | IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r |
eb290d02 | 909 | IN UINT32 NamespaceId,\r |
eb290d02 FT |
910 | IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r |
911 | )\r | |
912 | {\r | |
eb290d02 | 913 | NVME_NAMESPACE_DEVICE_PATH *Node;\r |
d6c55989 FT |
914 | NVME_CONTROLLER_PRIVATE_DATA *Private;\r |
915 | EFI_STATUS Status;\r | |
916 | NVME_ADMIN_NAMESPACE_DATA *NamespaceData;\r | |
eb290d02 FT |
917 | \r |
918 | //\r | |
919 | // Validate parameters\r | |
920 | //\r | |
921 | if ((This == NULL) || (DevicePath == NULL)) {\r | |
922 | return EFI_INVALID_PARAMETER;\r | |
923 | }\r | |
924 | \r | |
d6c55989 FT |
925 | Status = EFI_SUCCESS;\r |
926 | Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r | |
eb290d02 | 927 | \r |
946f48eb HW |
928 | //\r |
929 | // Check NamespaceId is valid or not.\r | |
930 | //\r | |
931 | if ((NamespaceId == 0) ||\r | |
932 | (NamespaceId > Private->ControllerData->Nn)) {\r | |
933 | return EFI_NOT_FOUND;\r | |
934 | }\r | |
935 | \r | |
d6c55989 | 936 | Node = (NVME_NAMESPACE_DEVICE_PATH *)AllocateZeroPool (sizeof (NVME_NAMESPACE_DEVICE_PATH));\r |
eb290d02 FT |
937 | if (Node == NULL) {\r |
938 | return EFI_OUT_OF_RESOURCES;\r | |
939 | }\r | |
940 | \r | |
941 | Node->Header.Type = MESSAGING_DEVICE_PATH;\r | |
942 | Node->Header.SubType = MSG_NVME_NAMESPACE_DP;\r | |
943 | SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));\r | |
944 | Node->NamespaceId = NamespaceId;\r | |
d6c55989 FT |
945 | \r |
946 | //\r | |
947 | // Allocate a buffer for Identify Namespace data.\r | |
948 | //\r | |
949 | NamespaceData = NULL;\r | |
950 | NamespaceData = AllocateZeroPool(sizeof (NVME_ADMIN_NAMESPACE_DATA));\r | |
951 | if(NamespaceData == NULL) {\r | |
952 | Status = EFI_OUT_OF_RESOURCES;\r | |
953 | goto Exit;\r | |
954 | }\r | |
955 | \r | |
956 | //\r | |
957 | // Get UUID from specified Identify Namespace data.\r | |
958 | //\r | |
959 | Status = NvmeIdentifyNamespace (\r | |
960 | Private,\r | |
961 | NamespaceId,\r | |
962 | (VOID *)NamespaceData\r | |
963 | );\r | |
964 | \r | |
965 | if (EFI_ERROR(Status)) {\r | |
966 | goto Exit;\r | |
967 | }\r | |
968 | \r | |
969 | Node->NamespaceUuid = NamespaceData->Eui64;\r | |
eb290d02 FT |
970 | \r |
971 | *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;\r | |
d6c55989 FT |
972 | \r |
973 | Exit:\r | |
974 | if(NamespaceData != NULL) {\r | |
975 | FreePool (NamespaceData);\r | |
976 | }\r | |
977 | \r | |
978 | if (EFI_ERROR (Status)) {\r | |
979 | FreePool (Node);\r | |
980 | }\r | |
981 | \r | |
982 | return Status;\r | |
eb290d02 FT |
983 | }\r |
984 | \r |