MdeModulePkg NvmExpressDxe: return error code in error path
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressPassthru.c
CommitLineData
eb290d02
FT
1/** @file\r
2 NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r
3 NVM Express specification.\r
4\r
35f910f0 5 (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>\r
748cd9a6 6 Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
eb290d02
FT
7 This program and the accompanying materials\r
8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php.\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17#include "NvmExpress.h"\r
18\r
eb290d02
FT
19/**\r
20 Dump the execution status from a given completion queue entry.\r
21\r
22 @param[in] Cq A pointer to the NVME_CQ item.\r
23\r
24**/\r
25VOID\r
26NvmeDumpStatus (\r
27 IN NVME_CQ *Cq\r
28 )\r
29{\r
30 DEBUG ((EFI_D_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));\r
31\r
32 DEBUG ((EFI_D_VERBOSE, " SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));\r
33\r
34 DEBUG ((EFI_D_VERBOSE, " NVMe Cmd Execution Result - "));\r
35\r
36 switch (Cq->Sct) {\r
37 case 0x0:\r
38 switch (Cq->Sc) {\r
39 case 0x0:\r
40 DEBUG ((EFI_D_VERBOSE, "Successful Completion\n"));\r
41 break;\r
42 case 0x1:\r
43 DEBUG ((EFI_D_VERBOSE, "Invalid Command Opcode\n"));\r
44 break;\r
45 case 0x2:\r
46 DEBUG ((EFI_D_VERBOSE, "Invalid Field in Command\n"));\r
47 break;\r
48 case 0x3:\r
49 DEBUG ((EFI_D_VERBOSE, "Command ID Conflict\n"));\r
50 break;\r
51 case 0x4:\r
52 DEBUG ((EFI_D_VERBOSE, "Data Transfer Error\n"));\r
53 break;\r
54 case 0x5:\r
55 DEBUG ((EFI_D_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));\r
56 break;\r
57 case 0x6:\r
58 DEBUG ((EFI_D_VERBOSE, "Internal Device Error\n"));\r
59 break;\r
60 case 0x7:\r
61 DEBUG ((EFI_D_VERBOSE, "Command Abort Requested\n"));\r
62 break;\r
63 case 0x8:\r
64 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to SQ Deletion\n"));\r
65 break;\r
66 case 0x9:\r
67 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Failed Fused Command\n"));\r
68 break;\r
69 case 0xA:\r
70 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Missing Fused Command\n"));\r
71 break;\r
72 case 0xB:\r
73 DEBUG ((EFI_D_VERBOSE, "Invalid Namespace or Format\n"));\r
74 break;\r
75 case 0xC:\r
76 DEBUG ((EFI_D_VERBOSE, "Command Sequence Error\n"));\r
77 break;\r
78 case 0xD:\r
79 DEBUG ((EFI_D_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));\r
80 break;\r
81 case 0xE:\r
82 DEBUG ((EFI_D_VERBOSE, "Invalid Number of SGL Descriptors\n"));\r
83 break;\r
84 case 0xF:\r
85 DEBUG ((EFI_D_VERBOSE, "Data SGL Length Invalid\n"));\r
86 break;\r
87 case 0x10:\r
88 DEBUG ((EFI_D_VERBOSE, "Metadata SGL Length Invalid\n"));\r
89 break;\r
90 case 0x11:\r
91 DEBUG ((EFI_D_VERBOSE, "SGL Descriptor Type Invalid\n"));\r
92 break;\r
93 case 0x80:\r
94 DEBUG ((EFI_D_VERBOSE, "LBA Out of Range\n"));\r
95 break;\r
96 case 0x81:\r
97 DEBUG ((EFI_D_VERBOSE, "Capacity Exceeded\n"));\r
98 break;\r
99 case 0x82:\r
100 DEBUG ((EFI_D_VERBOSE, "Namespace Not Ready\n"));\r
101 break;\r
102 case 0x83:\r
103 DEBUG ((EFI_D_VERBOSE, "Reservation Conflict\n"));\r
104 break;\r
105 }\r
106 break;\r
107\r
108 case 0x1:\r
109 switch (Cq->Sc) {\r
110 case 0x0:\r
111 DEBUG ((EFI_D_VERBOSE, "Completion Queue Invalid\n"));\r
112 break;\r
113 case 0x1:\r
114 DEBUG ((EFI_D_VERBOSE, "Invalid Queue Identifier\n"));\r
115 break;\r
116 case 0x2:\r
117 DEBUG ((EFI_D_VERBOSE, "Maximum Queue Size Exceeded\n"));\r
118 break;\r
119 case 0x3:\r
120 DEBUG ((EFI_D_VERBOSE, "Abort Command Limit Exceeded\n"));\r
121 break;\r
122 case 0x5:\r
123 DEBUG ((EFI_D_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));\r
124 break;\r
125 case 0x6:\r
126 DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Slot\n"));\r
127 break;\r
128 case 0x7:\r
129 DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Image\n"));\r
130 break;\r
131 case 0x8:\r
132 DEBUG ((EFI_D_VERBOSE, "Invalid Interrupt Vector\n"));\r
133 break;\r
134 case 0x9:\r
135 DEBUG ((EFI_D_VERBOSE, "Invalid Log Page\n"));\r
136 break;\r
137 case 0xA:\r
138 DEBUG ((EFI_D_VERBOSE, "Invalid Format\n"));\r
139 break;\r
140 case 0xB:\r
141 DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires Conventional Reset\n"));\r
142 break;\r
143 case 0xC:\r
144 DEBUG ((EFI_D_VERBOSE, "Invalid Queue Deletion\n"));\r
145 break;\r
146 case 0xD:\r
147 DEBUG ((EFI_D_VERBOSE, "Feature Identifier Not Saveable\n"));\r
148 break;\r
149 case 0xE:\r
150 DEBUG ((EFI_D_VERBOSE, "Feature Not Changeable\n"));\r
151 break;\r
152 case 0xF:\r
153 DEBUG ((EFI_D_VERBOSE, "Feature Not Namespace Specific\n"));\r
154 break;\r
155 case 0x10:\r
156 DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));\r
157 break;\r
158 case 0x80:\r
159 DEBUG ((EFI_D_VERBOSE, "Conflicting Attributes\n"));\r
160 break;\r
161 case 0x81:\r
162 DEBUG ((EFI_D_VERBOSE, "Invalid Protection Information\n"));\r
163 break;\r
164 case 0x82:\r
165 DEBUG ((EFI_D_VERBOSE, "Attempted Write to Read Only Range\n"));\r
166 break;\r
167 }\r
168 break;\r
169\r
170 case 0x2:\r
171 switch (Cq->Sc) {\r
172 case 0x80:\r
173 DEBUG ((EFI_D_VERBOSE, "Write Fault\n"));\r
174 break;\r
175 case 0x81:\r
176 DEBUG ((EFI_D_VERBOSE, "Unrecovered Read Error\n"));\r
177 break;\r
178 case 0x82:\r
179 DEBUG ((EFI_D_VERBOSE, "End-to-end Guard Check Error\n"));\r
180 break;\r
181 case 0x83:\r
182 DEBUG ((EFI_D_VERBOSE, "End-to-end Application Tag Check Error\n"));\r
183 break;\r
184 case 0x84:\r
185 DEBUG ((EFI_D_VERBOSE, "End-to-end Reference Tag Check Error\n"));\r
186 break;\r
187 case 0x85:\r
188 DEBUG ((EFI_D_VERBOSE, "Compare Failure\n"));\r
189 break;\r
190 case 0x86:\r
191 DEBUG ((EFI_D_VERBOSE, "Access Denied\n"));\r
192 break;\r
193 }\r
194 break;\r
195\r
196 default:\r
197 break;\r
198 }\r
199}\r
200\r
201/**\r
202 Create PRP lists for data transfer which is larger than 2 memory pages.\r
203 Note here we calcuate the number of required PRP lists and allocate them at one time.\r
204\r
205 @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
206 @param[in] PhysicalAddr The physical base address of data buffer.\r
207 @param[in] Pages The number of pages to be transfered.\r
208 @param[out] PrpListHost The host base address of PRP lists.\r
209 @param[in,out] PrpListNo The number of PRP List.\r
210 @param[out] Mapping The mapping value returned from PciIo.Map().\r
211\r
212 @retval The pointer to the first PRP List of the PRP lists.\r
213\r
214**/\r
215VOID*\r
216NvmeCreatePrpList (\r
217 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
218 IN EFI_PHYSICAL_ADDRESS PhysicalAddr,\r
219 IN UINTN Pages,\r
220 OUT VOID **PrpListHost,\r
221 IN OUT UINTN *PrpListNo,\r
222 OUT VOID **Mapping\r
223 )\r
224{\r
225 UINTN PrpEntryNo;\r
226 UINT64 PrpListBase;\r
227 UINTN PrpListIndex;\r
228 UINTN PrpEntryIndex;\r
229 UINT64 Remainder;\r
230 EFI_PHYSICAL_ADDRESS PrpListPhyAddr;\r
231 UINTN Bytes;\r
232 EFI_STATUS Status;\r
233\r
234 //\r
235 // The number of Prp Entry in a memory page.\r
236 //\r
237 PrpEntryNo = EFI_PAGE_SIZE / sizeof (UINT64);\r
238\r
239 //\r
240 // Calculate total PrpList number.\r
241 //\r
769402ef
FT
242 *PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo - 1, &Remainder);\r
243 if (*PrpListNo == 0) {\r
244 *PrpListNo = 1;\r
a9ec6d65 245 } else if ((Remainder != 0) && (Remainder != 1)) {\r
eb290d02 246 *PrpListNo += 1;\r
769402ef
FT
247 } else if (Remainder == 1) {\r
248 Remainder = PrpEntryNo;\r
249 } else if (Remainder == 0) {\r
250 Remainder = PrpEntryNo - 1;\r
eb290d02
FT
251 }\r
252\r
253 Status = PciIo->AllocateBuffer (\r
254 PciIo,\r
255 AllocateAnyPages,\r
256 EfiBootServicesData,\r
257 *PrpListNo,\r
258 PrpListHost,\r
259 0\r
260 );\r
261\r
262 if (EFI_ERROR (Status)) {\r
263 return NULL;\r
264 }\r
265\r
266 Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);\r
267 Status = PciIo->Map (\r
268 PciIo,\r
269 EfiPciIoOperationBusMasterCommonBuffer,\r
270 *PrpListHost,\r
271 &Bytes,\r
272 &PrpListPhyAddr,\r
273 Mapping\r
274 );\r
275\r
276 if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (*PrpListNo))) {\r
277 DEBUG ((EFI_D_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));\r
278 goto EXIT;\r
279 }\r
280 //\r
281 // Fill all PRP lists except of last one.\r
282 //\r
283 ZeroMem (*PrpListHost, Bytes);\r
284 for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {\r
769402ef 285 PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r
eb290d02
FT
286\r
287 for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {\r
288 if (PrpEntryIndex != PrpEntryNo - 1) {\r
289 //\r
290 // Fill all PRP entries except of last one.\r
291 //\r
292 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r
293 PhysicalAddr += EFI_PAGE_SIZE;\r
294 } else {\r
295 //\r
296 // Fill last PRP entries with next PRP List pointer.\r
297 //\r
298 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;\r
299 }\r
300 }\r
301 }\r
302 //\r
303 // Fill last PRP list.\r
304 //\r
305 PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r
769402ef 306 for (PrpEntryIndex = 0; PrpEntryIndex < Remainder; ++PrpEntryIndex) {\r
eb290d02
FT
307 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r
308 PhysicalAddr += EFI_PAGE_SIZE;\r
309 }\r
310\r
311 return (VOID*)(UINTN)PrpListPhyAddr;\r
312\r
313EXIT:\r
314 PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);\r
315 return NULL;\r
316}\r
317\r
318\r
5f5bba14
HW
319/**\r
320 Aborts the asynchronous PassThru requests.\r
321\r
322 @param[in] Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA\r
323 data structure.\r
324\r
325 @retval EFI_SUCCESS The asynchronous PassThru requests have been aborted.\r
326 @return EFI_DEVICE_ERROR Fail to abort all the asynchronous PassThru requests.\r
327\r
328**/\r
329EFI_STATUS\r
330AbortAsyncPassThruTasks (\r
331 IN NVME_CONTROLLER_PRIVATE_DATA *Private\r
332 )\r
333{\r
334 EFI_PCI_IO_PROTOCOL *PciIo;\r
335 LIST_ENTRY *Link;\r
336 LIST_ENTRY *NextLink;\r
337 NVME_BLKIO2_SUBTASK *Subtask;\r
338 NVME_BLKIO2_REQUEST *BlkIo2Request;\r
339 NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;\r
340 EFI_BLOCK_IO2_TOKEN *Token;\r
341 EFI_TPL OldTpl;\r
342 EFI_STATUS Status;\r
343\r
344 PciIo = Private->PciIo;\r
345 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r
346\r
347 //\r
348 // Cancel the unsubmitted subtasks.\r
349 //\r
350 for (Link = GetFirstNode (&Private->UnsubmittedSubtasks);\r
351 !IsNull (&Private->UnsubmittedSubtasks, Link);\r
352 Link = NextLink) {\r
353 NextLink = GetNextNode (&Private->UnsubmittedSubtasks, Link);\r
354 Subtask = NVME_BLKIO2_SUBTASK_FROM_LINK (Link);\r
355 BlkIo2Request = Subtask->BlockIo2Request;\r
356 Token = BlkIo2Request->Token;\r
357\r
358 BlkIo2Request->UnsubmittedSubtaskNum--;\r
359 if (Subtask->IsLast) {\r
360 BlkIo2Request->LastSubtaskSubmitted = TRUE;\r
361 }\r
362 Token->TransactionStatus = EFI_ABORTED;\r
363\r
364 RemoveEntryList (Link);\r
365 InsertTailList (&BlkIo2Request->SubtasksQueue, Link);\r
366 gBS->SignalEvent (Subtask->Event);\r
367 }\r
368\r
369 //\r
370 // Cleanup the resources for the asynchronous PassThru requests.\r
371 //\r
372 for (Link = GetFirstNode (&Private->AsyncPassThruQueue);\r
373 !IsNull (&Private->AsyncPassThruQueue, Link);\r
374 Link = NextLink) {\r
375 NextLink = GetNextNode (&Private->AsyncPassThruQueue, Link);\r
376 AsyncRequest = NVME_PASS_THRU_ASYNC_REQ_FROM_THIS (Link);\r
377\r
378 if (AsyncRequest->MapData != NULL) {\r
379 PciIo->Unmap (PciIo, AsyncRequest->MapData);\r
380 }\r
381 if (AsyncRequest->MapMeta != NULL) {\r
382 PciIo->Unmap (PciIo, AsyncRequest->MapMeta);\r
383 }\r
384 if (AsyncRequest->MapPrpList != NULL) {\r
385 PciIo->Unmap (PciIo, AsyncRequest->MapPrpList);\r
386 }\r
387 if (AsyncRequest->PrpListHost != NULL) {\r
388 PciIo->FreeBuffer (\r
389 PciIo,\r
390 AsyncRequest->PrpListNo,\r
391 AsyncRequest->PrpListHost\r
392 );\r
393 }\r
394\r
395 RemoveEntryList (Link);\r
396 gBS->SignalEvent (AsyncRequest->CallerEvent);\r
397 FreePool (AsyncRequest);\r
398 }\r
399\r
400 if (IsListEmpty (&Private->AsyncPassThruQueue) &&\r
401 IsListEmpty (&Private->UnsubmittedSubtasks)) {\r
402 Status = EFI_SUCCESS;\r
403 } else {\r
404 Status = EFI_DEVICE_ERROR;\r
405 }\r
406\r
407 gBS->RestoreTPL (OldTpl);\r
408\r
409 return Status;\r
410}\r
411\r
412\r
eb290d02
FT
413/**\r
414 Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports\r
d6c55989 415 both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking\r
eb290d02
FT
416 I/O functionality is optional.\r
417\r
d6c55989
FT
418\r
419 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
420 @param[in] NamespaceId A 32 bit namespace ID as defined in the NVMe specification to which the NVM Express Command\r
421 Packet will be sent. A value of 0 denotes the NVM Express controller, a value of all 0xFF's\r
422 (all bytes are 0xFF) in the namespace ID specifies that the command packet should be sent to\r
423 all valid namespaces.\r
424 @param[in,out] Packet A pointer to the NVM Express Command Packet.\r
425 @param[in] Event If non-blocking I/O is not supported then Event is ignored, and blocking I/O is performed.\r
426 If Event is NULL, then blocking I/O is performed. If Event is not NULL and non-blocking I/O\r
427 is supported, then non-blocking I/O is performed, and Event will be signaled when the NVM\r
eb290d02
FT
428 Express Command Packet completes.\r
429\r
430 @retval EFI_SUCCESS The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred\r
431 to, or from DataBuffer.\r
432 @retval EFI_BAD_BUFFER_SIZE The NVM Express Command Packet was not executed. The number of bytes that could be transferred\r
433 is returned in TransferLength.\r
434 @retval EFI_NOT_READY The NVM Express Command Packet could not be sent because the controller is not ready. The caller\r
435 may retry again later.\r
436 @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the NVM Express Command Packet.\r
d6c55989 437 @retval EFI_INVALID_PARAMETER NamespaceId or the contents of EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM\r
eb290d02 438 Express Command Packet was not sent, so no additional status information is available.\r
d6c55989
FT
439 @retval EFI_UNSUPPORTED The command described by the NVM Express Command Packet is not supported by the NVM Express\r
440 controller. The NVM Express Command Packet was not sent so no additional status information\r
441 is available.\r
eb290d02
FT
442 @retval EFI_TIMEOUT A timeout occurred while waiting for the NVM Express Command Packet to execute.\r
443\r
444**/\r
445EFI_STATUS\r
446EFIAPI\r
447NvmExpressPassThru (\r
d6c55989 448 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
eb290d02 449 IN UINT32 NamespaceId,\r
d6c55989 450 IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,\r
eb290d02
FT
451 IN EFI_EVENT Event OPTIONAL\r
452 )\r
453{\r
3c52deaf
HW
454 NVME_CONTROLLER_PRIVATE_DATA *Private;\r
455 EFI_STATUS Status;\r
9a77210b 456 EFI_STATUS PreviousStatus;\r
3c52deaf
HW
457 EFI_PCI_IO_PROTOCOL *PciIo;\r
458 NVME_SQ *Sq;\r
459 NVME_CQ *Cq;\r
460 UINT16 QueueId;\r
461 UINT32 Bytes;\r
462 UINT16 Offset;\r
463 EFI_EVENT TimerEvent;\r
464 EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r
465 EFI_PHYSICAL_ADDRESS PhyAddr;\r
466 VOID *MapData;\r
467 VOID *MapMeta;\r
468 VOID *MapPrpList;\r
469 UINTN MapLength;\r
470 UINT64 *Prp;\r
471 VOID *PrpListHost;\r
472 UINTN PrpListNo;\r
491f6026 473 UINT32 Attributes;\r
3c52deaf 474 UINT32 IoAlign;\r
b7f82a3a 475 UINT32 MaxTransLen;\r
3c52deaf
HW
476 UINT32 Data;\r
477 NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;\r
478 EFI_TPL OldTpl;\r
eb290d02
FT
479\r
480 //\r
481 // check the data fields in Packet parameter.\r
482 //\r
483 if ((This == NULL) || (Packet == NULL)) {\r
484 return EFI_INVALID_PARAMETER;\r
485 }\r
486\r
d6c55989 487 if ((Packet->NvmeCmd == NULL) || (Packet->NvmeCompletion == NULL)) {\r
eb290d02
FT
488 return EFI_INVALID_PARAMETER;\r
489 }\r
490\r
d6c55989 491 if (Packet->QueueType != NVME_ADMIN_QUEUE && Packet->QueueType != NVME_IO_QUEUE) {\r
eb290d02
FT
492 return EFI_INVALID_PARAMETER;\r
493 }\r
494\r
491f6026
HW
495 //\r
496 // 'Attributes' with neither EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL nor\r
497 // EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL set is an illegal\r
498 // configuration.\r
499 //\r
500 Attributes = This->Mode->Attributes;\r
501 if ((Attributes & (EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL |\r
502 EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL)) == 0) {\r
503 return EFI_INVALID_PARAMETER;\r
504 }\r
505\r
3c52deaf
HW
506 //\r
507 // Buffer alignment check for TransferBuffer & MetadataBuffer.\r
508 //\r
491f6026 509 IoAlign = This->Mode->IoAlign;\r
3c52deaf
HW
510 if (IoAlign > 0 && (((UINTN) Packet->TransferBuffer & (IoAlign - 1)) != 0)) {\r
511 return EFI_INVALID_PARAMETER;\r
512 }\r
513\r
514 if (IoAlign > 0 && (((UINTN) Packet->MetadataBuffer & (IoAlign - 1)) != 0)) {\r
515 return EFI_INVALID_PARAMETER;\r
516 }\r
517\r
eb290d02 518 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r
b7f82a3a
HW
519\r
520 //\r
80b405a6
HW
521 // Check NamespaceId is valid or not.\r
522 //\r
523 if ((NamespaceId > Private->ControllerData->Nn) &&\r
524 (NamespaceId != (UINT32) -1)) {\r
525 return EFI_INVALID_PARAMETER;\r
526 }\r
527\r
528 //\r
b7f82a3a
HW
529 // Check whether TransferLength exceeds the maximum data transfer size.\r
530 //\r
531 if (Private->ControllerData->Mdts != 0) {\r
532 MaxTransLen = (1 << (Private->ControllerData->Mdts)) *\r
533 (1 << (Private->Cap.Mpsmin + 12));\r
534 if (Packet->TransferLength > MaxTransLen) {\r
535 Packet->TransferLength = MaxTransLen;\r
536 return EFI_BAD_BUFFER_SIZE;\r
537 }\r
538 }\r
539\r
eb290d02
FT
540 PciIo = Private->PciIo;\r
541 MapData = NULL;\r
542 MapMeta = NULL;\r
543 MapPrpList = NULL;\r
544 PrpListHost = NULL;\r
545 PrpListNo = 0;\r
546 Prp = NULL;\r
547 TimerEvent = NULL;\r
548 Status = EFI_SUCCESS;\r
549\r
758ea946
HW
550 if (Packet->QueueType == NVME_ADMIN_QUEUE) {\r
551 QueueId = 0;\r
552 } else {\r
553 if (Event == NULL) {\r
554 QueueId = 1;\r
555 } else {\r
556 QueueId = 2;\r
557\r
558 //\r
559 // Submission queue full check.\r
560 //\r
561 if ((Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1) ==\r
562 Private->AsyncSqHead) {\r
563 return EFI_NOT_READY;\r
564 }\r
565 }\r
566 }\r
567 Sq = Private->SqBuffer[QueueId] + Private->SqTdbl[QueueId].Sqt;\r
568 Cq = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;\r
eb290d02
FT
569\r
570 if (Packet->NvmeCmd->Nsid != NamespaceId) {\r
571 return EFI_INVALID_PARAMETER;\r
572 }\r
573\r
574 ZeroMem (Sq, sizeof (NVME_SQ));\r
d6c55989
FT
575 Sq->Opc = (UINT8)Packet->NvmeCmd->Cdw0.Opcode;\r
576 Sq->Fuse = (UINT8)Packet->NvmeCmd->Cdw0.FusedOperation;\r
758ea946 577 Sq->Cid = Private->Cid[QueueId]++;\r
eb290d02
FT
578 Sq->Nsid = Packet->NvmeCmd->Nsid;\r
579\r
580 //\r
581 // Currently we only support PRP for data transfer, SGL is NOT supported.\r
582 //\r
7b8883c6
FT
583 ASSERT (Sq->Psdt == 0);\r
584 if (Sq->Psdt != 0) {\r
eb290d02
FT
585 DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));\r
586 return EFI_UNSUPPORTED;\r
587 }\r
588\r
589 Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;\r
590 //\r
591 // If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.\r
592 // Note here we don't handle data buffer for CreateIOSubmitionQueue and CreateIOCompletionQueue cmds because\r
593 // these two cmds are special which requires their data buffer must support simultaneous access by both the\r
594 // processor and a PCI Bus Master. It's caller's responsbility to ensure this.\r
595 //\r
748cd9a6
HW
596 if (((Sq->Opc & (BIT0 | BIT1)) != 0) &&\r
597 !((Packet->QueueType == NVME_ADMIN_QUEUE) && ((Sq->Opc == NVME_ADMIN_CRIOCQ_CMD) || (Sq->Opc == NVME_ADMIN_CRIOSQ_CMD)))) {\r
b7f82a3a
HW
598 if ((Packet->TransferLength == 0) || (Packet->TransferBuffer == NULL)) {\r
599 return EFI_INVALID_PARAMETER;\r
600 }\r
601\r
eb290d02
FT
602 if ((Sq->Opc & BIT0) != 0) {\r
603 Flag = EfiPciIoOperationBusMasterRead;\r
604 } else {\r
605 Flag = EfiPciIoOperationBusMasterWrite;\r
606 }\r
607\r
608 MapLength = Packet->TransferLength;\r
609 Status = PciIo->Map (\r
610 PciIo,\r
611 Flag,\r
612 Packet->TransferBuffer,\r
613 &MapLength,\r
614 &PhyAddr,\r
615 &MapData\r
616 );\r
617 if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {\r
618 return EFI_OUT_OF_RESOURCES;\r
619 }\r
620\r
621 Sq->Prp[0] = PhyAddr;\r
622 Sq->Prp[1] = 0;\r
623\r
b7f82a3a 624 if((Packet->MetadataLength != 0) && (Packet->MetadataBuffer != NULL)) {\r
eb290d02
FT
625 MapLength = Packet->MetadataLength;\r
626 Status = PciIo->Map (\r
627 PciIo,\r
628 Flag,\r
629 Packet->MetadataBuffer,\r
630 &MapLength,\r
631 &PhyAddr,\r
632 &MapMeta\r
633 );\r
634 if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {\r
635 PciIo->Unmap (\r
636 PciIo,\r
637 MapData\r
638 );\r
639\r
640 return EFI_OUT_OF_RESOURCES;\r
641 }\r
642 Sq->Mptr = PhyAddr;\r
643 }\r
644 }\r
645 //\r
646 // If the buffer size spans more than two memory pages (page size as defined in CC.Mps),\r
647 // then build a PRP list in the second PRP submission queue entry.\r
648 //\r
649 Offset = ((UINT16)Sq->Prp[0]) & (EFI_PAGE_SIZE - 1);\r
650 Bytes = Packet->TransferLength;\r
651\r
652 if ((Offset + Bytes) > (EFI_PAGE_SIZE * 2)) {\r
653 //\r
654 // Create PrpList for remaining data buffer.\r
655 //\r
656 PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r
657 Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);\r
658 if (Prp == NULL) {\r
67d3e63c 659 Status = EFI_OUT_OF_RESOURCES;\r
eb290d02
FT
660 goto EXIT;\r
661 }\r
662\r
663 Sq->Prp[1] = (UINT64)(UINTN)Prp;\r
664 } else if ((Offset + Bytes) > EFI_PAGE_SIZE) {\r
665 Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r
666 }\r
667\r
d6c55989
FT
668 if(Packet->NvmeCmd->Flags & CDW2_VALID) {\r
669 Sq->Rsvd2 = (UINT64)Packet->NvmeCmd->Cdw2;\r
670 }\r
671 if(Packet->NvmeCmd->Flags & CDW3_VALID) {\r
672 Sq->Rsvd2 |= LShiftU64 ((UINT64)Packet->NvmeCmd->Cdw3, 32);\r
673 }\r
eb290d02
FT
674 if(Packet->NvmeCmd->Flags & CDW10_VALID) {\r
675 Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;\r
676 }\r
677 if(Packet->NvmeCmd->Flags & CDW11_VALID) {\r
678 Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;\r
679 }\r
680 if(Packet->NvmeCmd->Flags & CDW12_VALID) {\r
681 Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;\r
682 }\r
683 if(Packet->NvmeCmd->Flags & CDW13_VALID) {\r
684 Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;\r
685 }\r
686 if(Packet->NvmeCmd->Flags & CDW14_VALID) {\r
687 Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;\r
688 }\r
689 if(Packet->NvmeCmd->Flags & CDW15_VALID) {\r
690 Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;\r
691 }\r
692\r
693 //\r
694 // Ring the submission queue doorbell.\r
695 //\r
aec53afb 696 if ((Event != NULL) && (QueueId != 0)) {\r
758ea946
HW
697 Private->SqTdbl[QueueId].Sqt =\r
698 (Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1);\r
699 } else {\r
700 Private->SqTdbl[QueueId].Sqt ^= 1;\r
701 }\r
702 Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[QueueId]);\r
f6b139bd 703 Status = PciIo->Mem.Write (\r
eb290d02
FT
704 PciIo,\r
705 EfiPciIoWidthUint32,\r
706 NVME_BAR,\r
758ea946 707 NVME_SQTDBL_OFFSET(QueueId, Private->Cap.Dstrd),\r
eb290d02 708 1,\r
7b8883c6 709 &Data\r
eb290d02
FT
710 );\r
711\r
f6b139bd
SP
712 if (EFI_ERROR (Status)) {\r
713 goto EXIT;\r
714 }\r
715\r
758ea946
HW
716 //\r
717 // For non-blocking requests, return directly if the command is placed\r
718 // in the submission queue.\r
719 //\r
aec53afb 720 if ((Event != NULL) && (QueueId != 0)) {\r
758ea946
HW
721 AsyncRequest = AllocateZeroPool (sizeof (NVME_PASS_THRU_ASYNC_REQ));\r
722 if (AsyncRequest == NULL) {\r
723 Status = EFI_DEVICE_ERROR;\r
724 goto EXIT;\r
725 }\r
726\r
727 AsyncRequest->Signature = NVME_PASS_THRU_ASYNC_REQ_SIG;\r
728 AsyncRequest->Packet = Packet;\r
729 AsyncRequest->CommandId = Sq->Cid;\r
730 AsyncRequest->CallerEvent = Event;\r
f2333c70
SP
731 AsyncRequest->MapData = MapData;\r
732 AsyncRequest->MapMeta = MapMeta;\r
733 AsyncRequest->MapPrpList = MapPrpList;\r
734 AsyncRequest->PrpListNo = PrpListNo;\r
735 AsyncRequest->PrpListHost = PrpListHost;\r
758ea946
HW
736\r
737 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r
738 InsertTailList (&Private->AsyncPassThruQueue, &AsyncRequest->Link);\r
739 gBS->RestoreTPL (OldTpl);\r
740\r
741 return EFI_SUCCESS;\r
742 }\r
743\r
eb290d02
FT
744 Status = gBS->CreateEvent (\r
745 EVT_TIMER,\r
746 TPL_CALLBACK,\r
747 NULL,\r
748 NULL,\r
749 &TimerEvent\r
750 );\r
751 if (EFI_ERROR (Status)) {\r
752 goto EXIT;\r
753 }\r
754\r
755 Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);\r
756\r
757 if (EFI_ERROR(Status)) {\r
eb290d02
FT
758 goto EXIT;\r
759 }\r
760\r
761 //\r
762 // Wait for completion queue to get filled in.\r
763 //\r
764 Status = EFI_TIMEOUT;\r
eb290d02 765 while (EFI_ERROR (gBS->CheckEvent (TimerEvent))) {\r
758ea946 766 if (Cq->Pt != Private->Pt[QueueId]) {\r
eb290d02 767 Status = EFI_SUCCESS;\r
eb290d02
FT
768 break;\r
769 }\r
770 }\r
771\r
eb290d02 772 //\r
754b489b 773 // Check the NVMe cmd execution result\r
eb290d02 774 //\r
754b489b
TF
775 if (Status != EFI_TIMEOUT) {\r
776 if ((Cq->Sct == 0) && (Cq->Sc == 0)) {\r
777 Status = EFI_SUCCESS;\r
778 } else {\r
779 Status = EFI_DEVICE_ERROR;\r
780 //\r
781 // Copy the Respose Queue entry for this command to the callers response buffer\r
782 //\r
783 CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));\r
784 \r
785 //\r
786 // Dump every completion entry status for debugging.\r
787 //\r
788 DEBUG_CODE_BEGIN();\r
789 NvmeDumpStatus(Cq);\r
790 DEBUG_CODE_END();\r
791 }\r
5f5bba14
HW
792 } else {\r
793 //\r
794 // Timeout occurs for an NVMe command. Reset the controller to abort the\r
795 // outstanding commands.\r
796 //\r
797 DEBUG ((DEBUG_ERROR, "NvmExpressPassThru: Timeout occurs for an NVMe command.\n"));\r
798\r
799 //\r
800 // Disable the timer to trigger the process of async transfers temporarily.\r
801 //\r
802 Status = gBS->SetTimer (Private->TimerEvent, TimerCancel, 0);\r
803 if (EFI_ERROR (Status)) {\r
804 goto EXIT;\r
805 }\r
806\r
807 //\r
808 // Reset the NVMe controller.\r
809 //\r
810 Status = NvmeControllerInit (Private);\r
811 if (!EFI_ERROR (Status)) {\r
812 Status = AbortAsyncPassThruTasks (Private);\r
813 if (!EFI_ERROR (Status)) {\r
814 //\r
815 // Re-enable the timer to trigger the process of async transfers.\r
816 //\r
817 Status = gBS->SetTimer (Private->TimerEvent, TimerPeriodic, NVME_HC_ASYNC_TIMER);\r
818 if (!EFI_ERROR (Status)) {\r
819 //\r
820 // Return EFI_TIMEOUT to indicate a timeout occurs for NVMe PassThru command.\r
821 //\r
822 Status = EFI_TIMEOUT;\r
823 }\r
824 }\r
825 } else {\r
826 Status = EFI_DEVICE_ERROR;\r
827 }\r
828\r
829 goto EXIT;\r
754b489b 830 }\r
eb290d02 831\r
758ea946
HW
832 if ((Private->CqHdbl[QueueId].Cqh ^= 1) == 0) {\r
833 Private->Pt[QueueId] ^= 1;\r
754b489b 834 }\r
eb290d02 835\r
758ea946 836 Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]);\r
9a77210b 837 PreviousStatus = Status;\r
f6b139bd 838 Status = PciIo->Mem.Write (\r
eb290d02
FT
839 PciIo,\r
840 EfiPciIoWidthUint32,\r
841 NVME_BAR,\r
758ea946 842 NVME_CQHDBL_OFFSET(QueueId, Private->Cap.Dstrd),\r
eb290d02 843 1,\r
7b8883c6 844 &Data\r
eb290d02 845 );\r
9a77210b
HG
846 // The return status of PciIo->Mem.Write should not override\r
847 // previous status if previous status contains error.\r
848 Status = EFI_ERROR (PreviousStatus) ? PreviousStatus : Status;\r
eb290d02 849\r
aec53afb
HW
850 //\r
851 // For now, the code does not support the non-blocking feature for admin queue.\r
852 // If Event is not NULL for admin queue, signal the caller's event here.\r
853 //\r
854 if (Event != NULL) {\r
855 ASSERT (QueueId == 0);\r
856 gBS->SignalEvent (Event);\r
857 }\r
858\r
eb290d02
FT
859EXIT:\r
860 if (MapData != NULL) {\r
861 PciIo->Unmap (\r
862 PciIo,\r
863 MapData\r
864 );\r
865 }\r
866\r
867 if (MapMeta != NULL) {\r
868 PciIo->Unmap (\r
869 PciIo,\r
870 MapMeta\r
871 );\r
872 }\r
873\r
874 if (MapPrpList != NULL) {\r
875 PciIo->Unmap (\r
876 PciIo,\r
877 MapPrpList\r
878 );\r
879 }\r
880\r
881 if (Prp != NULL) {\r
882 PciIo->FreeBuffer (PciIo, PrpListNo, PrpListHost);\r
883 }\r
884\r
885 if (TimerEvent != NULL) {\r
886 gBS->CloseEvent (TimerEvent);\r
887 }\r
888 return Status;\r
889}\r
890\r
891/**\r
d6c55989 892 Used to retrieve the next namespace ID for this NVM Express controller.\r
eb290d02 893\r
d6c55989
FT
894 The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves the next valid\r
895 namespace ID on this NVM Express controller.\r
eb290d02 896\r
d6c55989
FT
897 If on input the value pointed to by NamespaceId is 0xFFFFFFFF, then the first valid namespace\r
898 ID defined on the NVM Express controller is returned in the location pointed to by NamespaceId\r
899 and a status of EFI_SUCCESS is returned.\r
eb290d02 900\r
d6c55989
FT
901 If on input the value pointed to by NamespaceId is an invalid namespace ID other than 0xFFFFFFFF,\r
902 then EFI_INVALID_PARAMETER is returned.\r
eb290d02 903\r
d6c55989
FT
904 If on input the value pointed to by NamespaceId is a valid namespace ID, then the next valid\r
905 namespace ID on the NVM Express controller is returned in the location pointed to by NamespaceId,\r
906 and EFI_SUCCESS is returned.\r
eb290d02 907\r
d6c55989
FT
908 If the value pointed to by NamespaceId is the namespace ID of the last namespace on the NVM\r
909 Express controller, then EFI_NOT_FOUND is returned.\r
910\r
911 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
eb290d02
FT
912 @param[in,out] NamespaceId On input, a pointer to a legal NamespaceId for an NVM Express\r
913 namespace present on the NVM Express controller. On output, a\r
914 pointer to the next NamespaceId of an NVM Express namespace on\r
915 an NVM Express controller. An input value of 0xFFFFFFFF retrieves\r
916 the first NamespaceId for an NVM Express namespace present on an\r
917 NVM Express controller.\r
eb290d02 918\r
d6c55989 919 @retval EFI_SUCCESS The Namespace ID of the next Namespace was returned.\r
eb290d02 920 @retval EFI_NOT_FOUND There are no more namespaces defined on this controller.\r
d6c55989 921 @retval EFI_INVALID_PARAMETER NamespaceId is an invalid value other than 0xFFFFFFFF.\r
eb290d02
FT
922\r
923**/\r
924EFI_STATUS\r
925EFIAPI\r
926NvmExpressGetNextNamespace (\r
d6c55989
FT
927 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
928 IN OUT UINT32 *NamespaceId\r
eb290d02
FT
929 )\r
930{\r
931 NVME_CONTROLLER_PRIVATE_DATA *Private;\r
932 NVME_ADMIN_NAMESPACE_DATA *NamespaceData;\r
933 UINT32 NextNamespaceId;\r
934 EFI_STATUS Status;\r
935\r
936 if ((This == NULL) || (NamespaceId == NULL)) {\r
937 return EFI_INVALID_PARAMETER;\r
938 }\r
939\r
940 NamespaceData = NULL;\r
941 Status = EFI_NOT_FOUND;\r
942\r
943 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r
944 //\r
945 // If the NamespaceId input value is 0xFFFFFFFF, then get the first valid namespace ID\r
946 //\r
947 if (*NamespaceId == 0xFFFFFFFF) {\r
948 //\r
949 // Start with the first namespace ID\r
950 //\r
951 NextNamespaceId = 1;\r
952 //\r
953 // Allocate buffer for Identify Namespace data.\r
954 //\r
955 NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r
956\r
957 if (NamespaceData == NULL) {\r
958 return EFI_NOT_FOUND;\r
959 }\r
960\r
961 Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r
962 if (EFI_ERROR(Status)) {\r
963 goto Done;\r
964 }\r
965\r
966 *NamespaceId = NextNamespaceId;\r
eb290d02 967 } else {\r
114358ea 968 if (*NamespaceId > Private->ControllerData->Nn) {\r
eb290d02
FT
969 return EFI_INVALID_PARAMETER;\r
970 }\r
971\r
972 NextNamespaceId = *NamespaceId + 1;\r
114358ea
HW
973 if (NextNamespaceId > Private->ControllerData->Nn) {\r
974 return EFI_NOT_FOUND;\r
975 }\r
976\r
eb290d02
FT
977 //\r
978 // Allocate buffer for Identify Namespace data.\r
979 //\r
980 NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r
981 if (NamespaceData == NULL) {\r
982 return EFI_NOT_FOUND;\r
983 }\r
984\r
985 Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r
986 if (EFI_ERROR(Status)) {\r
987 goto Done;\r
988 }\r
989\r
990 *NamespaceId = NextNamespaceId;\r
eb290d02
FT
991 }\r
992\r
993Done:\r
994 if (NamespaceData != NULL) {\r
995 FreePool(NamespaceData);\r
996 }\r
997\r
998 return Status;\r
999}\r
1000\r
1001/**\r
d6c55989
FT
1002 Used to translate a device path node to a namespace ID.\r
1003\r
1004 The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() function determines the namespace ID associated with the\r
1005 namespace described by DevicePath.\r
eb290d02 1006\r
d6c55989
FT
1007 If DevicePath is a device path node type that the NVM Express Pass Thru driver supports, then the NVM Express\r
1008 Pass Thru driver will attempt to translate the contents DevicePath into a namespace ID.\r
eb290d02 1009\r
d6c55989
FT
1010 If this translation is successful, then that namespace ID is returned in NamespaceId, and EFI_SUCCESS is returned\r
1011\r
1012 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
eb290d02
FT
1013 @param[in] DevicePath A pointer to the device path node that describes an NVM Express namespace on\r
1014 the NVM Express controller.\r
1015 @param[out] NamespaceId The NVM Express namespace ID contained in the device path node.\r
eb290d02 1016\r
d6c55989
FT
1017 @retval EFI_SUCCESS DevicePath was successfully translated to NamespaceId.\r
1018 @retval EFI_INVALID_PARAMETER If DevicePath or NamespaceId are NULL, then EFI_INVALID_PARAMETER is returned.\r
eb290d02
FT
1019 @retval EFI_UNSUPPORTED If DevicePath is not a device path node type that the NVM Express Pass Thru driver\r
1020 supports, then EFI_UNSUPPORTED is returned.\r
d6c55989
FT
1021 @retval EFI_NOT_FOUND If DevicePath is a device path node type that the NVM Express Pass Thru driver\r
1022 supports, but there is not a valid translation from DevicePath to a namespace ID,\r
1023 then EFI_NOT_FOUND is returned.\r
eb290d02
FT
1024**/\r
1025EFI_STATUS\r
1026EFIAPI\r
1027NvmExpressGetNamespace (\r
d6c55989 1028 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
eb290d02 1029 IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
d6c55989 1030 OUT UINT32 *NamespaceId\r
eb290d02
FT
1031 )\r
1032{\r
1033 NVME_NAMESPACE_DEVICE_PATH *Node;\r
284dc9bf 1034 NVME_CONTROLLER_PRIVATE_DATA *Private;\r
eb290d02 1035\r
d6c55989 1036 if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL)) {\r
eb290d02
FT
1037 return EFI_INVALID_PARAMETER;\r
1038 }\r
1039\r
1040 if (DevicePath->Type != MESSAGING_DEVICE_PATH) {\r
1041 return EFI_UNSUPPORTED;\r
1042 }\r
1043\r
284dc9bf
HW
1044 Node = (NVME_NAMESPACE_DEVICE_PATH *)DevicePath;\r
1045 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r
eb290d02
FT
1046\r
1047 if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {\r
1048 if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {\r
1049 return EFI_NOT_FOUND;\r
1050 }\r
1051\r
284dc9bf
HW
1052 //\r
1053 // Check NamespaceId in the device path node is valid or not.\r
1054 //\r
1055 if ((Node->NamespaceId == 0) ||\r
1056 (Node->NamespaceId > Private->ControllerData->Nn)) {\r
1057 return EFI_NOT_FOUND;\r
1058 }\r
1059\r
d6c55989 1060 *NamespaceId = Node->NamespaceId;\r
eb290d02
FT
1061\r
1062 return EFI_SUCCESS;\r
1063 } else {\r
1064 return EFI_UNSUPPORTED;\r
1065 }\r
1066}\r
1067\r
1068/**\r
1069 Used to allocate and build a device path node for an NVM Express namespace on an NVM Express controller.\r
1070\r
d6c55989 1071 The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device\r
eb290d02
FT
1072 path node for the NVM Express namespace specified by NamespaceId.\r
1073\r
d6c55989 1074 If the NamespaceId is not valid, then EFI_NOT_FOUND is returned.\r
eb290d02
FT
1075\r
1076 If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.\r
1077\r
1078 If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.\r
1079\r
1080 Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are\r
1081 initialized to describe the NVM Express namespace specified by NamespaceId, and EFI_SUCCESS is returned.\r
1082\r
d6c55989 1083 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
eb290d02
FT
1084 @param[in] NamespaceId The NVM Express namespace ID for which a device path node is to be\r
1085 allocated and built. Caller must set the NamespaceId to zero if the\r
1086 device path node will contain a valid UUID.\r
eb290d02
FT
1087 @param[in,out] DevicePath A pointer to a single device path node that describes the NVM Express\r
1088 namespace specified by NamespaceId. This function is responsible for\r
1089 allocating the buffer DevicePath with the boot service AllocatePool().\r
1090 It is the caller's responsibility to free DevicePath when the caller\r
1091 is finished with DevicePath.\r
1092 @retval EFI_SUCCESS The device path node that describes the NVM Express namespace specified\r
1093 by NamespaceId was allocated and returned in DevicePath.\r
d6c55989 1094 @retval EFI_NOT_FOUND The NamespaceId is not valid.\r
eb290d02
FT
1095 @retval EFI_INVALID_PARAMETER DevicePath is NULL.\r
1096 @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate the DevicePath node.\r
1097\r
1098**/\r
1099EFI_STATUS\r
1100EFIAPI\r
1101NvmExpressBuildDevicePath (\r
d6c55989 1102 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
eb290d02 1103 IN UINT32 NamespaceId,\r
eb290d02
FT
1104 IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
1105 )\r
1106{\r
eb290d02 1107 NVME_NAMESPACE_DEVICE_PATH *Node;\r
d6c55989
FT
1108 NVME_CONTROLLER_PRIVATE_DATA *Private;\r
1109 EFI_STATUS Status;\r
1110 NVME_ADMIN_NAMESPACE_DATA *NamespaceData;\r
eb290d02
FT
1111\r
1112 //\r
1113 // Validate parameters\r
1114 //\r
1115 if ((This == NULL) || (DevicePath == NULL)) {\r
1116 return EFI_INVALID_PARAMETER;\r
1117 }\r
1118\r
d6c55989
FT
1119 Status = EFI_SUCCESS;\r
1120 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r
eb290d02 1121\r
946f48eb
HW
1122 //\r
1123 // Check NamespaceId is valid or not.\r
1124 //\r
1125 if ((NamespaceId == 0) ||\r
1126 (NamespaceId > Private->ControllerData->Nn)) {\r
1127 return EFI_NOT_FOUND;\r
1128 }\r
1129\r
d6c55989 1130 Node = (NVME_NAMESPACE_DEVICE_PATH *)AllocateZeroPool (sizeof (NVME_NAMESPACE_DEVICE_PATH));\r
eb290d02
FT
1131 if (Node == NULL) {\r
1132 return EFI_OUT_OF_RESOURCES;\r
1133 }\r
1134\r
1135 Node->Header.Type = MESSAGING_DEVICE_PATH;\r
1136 Node->Header.SubType = MSG_NVME_NAMESPACE_DP;\r
1137 SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));\r
1138 Node->NamespaceId = NamespaceId;\r
d6c55989
FT
1139\r
1140 //\r
1141 // Allocate a buffer for Identify Namespace data.\r
1142 //\r
1143 NamespaceData = NULL;\r
1144 NamespaceData = AllocateZeroPool(sizeof (NVME_ADMIN_NAMESPACE_DATA));\r
1145 if(NamespaceData == NULL) {\r
1146 Status = EFI_OUT_OF_RESOURCES;\r
1147 goto Exit;\r
1148 }\r
1149\r
1150 //\r
1151 // Get UUID from specified Identify Namespace data.\r
1152 //\r
1153 Status = NvmeIdentifyNamespace (\r
1154 Private,\r
1155 NamespaceId,\r
1156 (VOID *)NamespaceData\r
1157 );\r
1158\r
1159 if (EFI_ERROR(Status)) {\r
1160 goto Exit;\r
1161 }\r
1162\r
1163 Node->NamespaceUuid = NamespaceData->Eui64;\r
eb290d02
FT
1164\r
1165 *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;\r
d6c55989
FT
1166\r
1167Exit:\r
1168 if(NamespaceData != NULL) {\r
1169 FreePool (NamespaceData);\r
1170 }\r
1171\r
1172 if (EFI_ERROR (Status)) {\r
1173 FreePool (Node);\r
1174 }\r
1175\r
1176 return Status;\r
eb290d02
FT
1177}\r
1178\r