MdeModulePkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressPei / NvmExpressPeiHci.h

/** @file\r
  The NvmExpressPei driver is used to manage non-volatile memory subsystem\r
  which follows NVM Express specification at PEI phase.\r
\r
  Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _NVM_EXPRESS_PEI_HCI_H_\r
#define _NVM_EXPRESS_PEI_HCI_H_\r
\r
//\r
// NVME host controller registers operation definitions\r
//\r
#define NVME_GET_CAP(Private, Cap)             NvmeMmioRead  (Cap, Private->MmioBase + NVME_CAP_OFFSET, sizeof (NVME_CAP))\r
#define NVME_GET_CC(Private, Cc)               NvmeMmioRead  (Cc, Private->MmioBase + NVME_CC_OFFSET, sizeof (NVME_CC))\r
#define NVME_SET_CC(Private, Cc)               NvmeMmioWrite (Private->MmioBase + NVME_CC_OFFSET, Cc, sizeof (NVME_CC))\r
#define NVME_GET_CSTS(Private, Csts)           NvmeMmioRead  (Csts, Private->MmioBase + NVME_CSTS_OFFSET, sizeof (NVME_CSTS))\r
#define NVME_GET_AQA(Private, Aqa)             NvmeMmioRead  (Aqa, Private->MmioBase + NVME_AQA_OFFSET, sizeof (NVME_AQA))\r
#define NVME_SET_AQA(Private, Aqa)             NvmeMmioWrite (Private->MmioBase + NVME_AQA_OFFSET, Aqa, sizeof (NVME_AQA))\r
#define NVME_GET_ASQ(Private, Asq)             NvmeMmioRead  (Asq, Private->MmioBase + NVME_ASQ_OFFSET, sizeof (NVME_ASQ))\r
#define NVME_SET_ASQ(Private, Asq)             NvmeMmioWrite (Private->MmioBase + NVME_ASQ_OFFSET, Asq, sizeof (NVME_ASQ))\r
#define NVME_GET_ACQ(Private, Acq)             NvmeMmioRead  (Acq, Private->MmioBase + NVME_ACQ_OFFSET, sizeof (NVME_ACQ))\r
#define NVME_SET_ACQ(Private, Acq)             NvmeMmioWrite (Private->MmioBase + NVME_ACQ_OFFSET, Acq, sizeof (NVME_ACQ))\r
#define NVME_GET_VER(Private, Ver)             NvmeMmioRead  (Ver, Private->MmioBase + NVME_VER_OFFSET, sizeof (NVME_VER))\r
#define NVME_SET_SQTDBL(Private, Qid, Sqtdbl)  NvmeMmioWrite (Private->MmioBase + NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd), Sqtdbl, sizeof (NVME_SQTDBL))\r
#define NVME_SET_CQHDBL(Private, Qid, Cqhdbl)  NvmeMmioWrite (Private->MmioBase + NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd), Cqhdbl, sizeof (NVME_CQHDBL))\r
\r
//\r
// Base memory address enum types\r
//\r
enum {\r
  BASEMEM_ASQ,\r
  BASEMEM_ACQ,\r
  BASEMEM_SQ,\r
  BASEMEM_CQ,\r
  BASEMEM_PRP,\r
  MAX_BASEMEM_COUNT\r
};\r
\r
//\r
// All of base memories are 4K(0x1000) alignment\r
//\r
#define ALIGN(v, a)                          (UINTN)((((v) - 1) | ((a) - 1)) + 1)\r
#define NVME_MEM_BASE(Private)               ((UINTN)(Private->Buffer))\r
#define NVME_ASQ_BASE(Private)               (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ))                                * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
#define NVME_ACQ_BASE(Private)               (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ))                                * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
#define NVME_SQ_BASE(Private, Index)         (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
#define NVME_CQ_BASE(Private, Index)         (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
#define NVME_PRP_BASE(Private)               (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP))                                * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
\r
\r
/**\r
  Transfer MMIO Data to memory.\r
\r
  @param[in,out] MemBuffer    Destination: Memory address.\r
  @param[in] MmioAddr         Source: MMIO address.\r
  @param[in] Size             Size for read.\r
\r
  @retval EFI_SUCCESS         MMIO read sucessfully.\r
\r
**/\r
EFI_STATUS\r
NvmeMmioRead (\r
  IN OUT VOID *MemBuffer,\r
  IN     UINTN MmioAddr,\r
  IN     UINTN Size\r
  );\r
\r
/**\r
  Transfer memory data to MMIO.\r
\r
  @param[in,out] MmioAddr    Destination: MMIO address.\r
  @param[in] MemBuffer       Source: Memory address.\r
  @param[in] Size            Size for write.\r
\r
  @retval EFI_SUCCESS        MMIO write sucessfully.\r
\r
**/\r
EFI_STATUS\r
NvmeMmioWrite (\r
  IN OUT UINTN MmioAddr,\r
  IN     VOID *MemBuffer,\r
  IN     UINTN Size\r
  );\r
\r
/**\r
  Get the page offset for specific NVME based memory.\r
\r
  @param[in] BaseMemIndex    The Index of BaseMem (0-based).\r
\r
  @retval - The page count for specific BaseMem Index\r
\r
**/\r
UINT32\r
NvmeBaseMemPageOffset (\r
  IN UINTN              BaseMemIndex\r
  );\r
\r
/**\r
  Initialize the Nvm Express controller.\r
\r
  @param[in] Private     The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.\r
\r
  @retval EFI_SUCCESS    The NVM Express Controller is initialized successfully.\r
  @retval Others         A device error occurred while initializing the controller.\r
\r
**/\r
EFI_STATUS\r
NvmeControllerInit (\r
  IN PEI_NVME_CONTROLLER_PRIVATE_DATA    *Private\r
  );\r
\r
/**\r
  Get specified identify namespace data.\r
\r
  @param[in] Private        The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.\r
  @param[in] NamespaceId    The specified namespace identifier.\r
  @param[in] Buffer         The buffer used to store the identify namespace data.\r
\r
  @return EFI_SUCCESS         Successfully get the identify namespace data.\r
  @return EFI_DEVICE_ERROR    Fail to get the identify namespace data.\r
\r
**/\r
EFI_STATUS\r
NvmeIdentifyNamespace (\r
  IN PEI_NVME_CONTROLLER_PRIVATE_DATA    *Private,\r
  IN UINT32                              NamespaceId,\r
  IN VOID                                *Buffer\r
  );\r
\r
/**\r
  Free the DMA resources allocated by an NVME controller.\r
\r
  @param[in] Private     The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.\r
\r
**/\r
VOID\r
NvmeFreeDmaResource (\r
  IN PEI_NVME_CONTROLLER_PRIVATE_DATA    *Private\r
  );\r
\r
#endif\r