[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciBus.h

/** @file\r
  Header files and data structures needed by PCI Bus module.\r
\r
Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
\r
#ifndef _EFI_PCI_BUS_H_\r
#define _EFI_PCI_BUS_H_\r
\r
#include <PiDxe.h>\r
\r
#include <Protocol/LoadedImage.h>\r
#include <Protocol/PciHostBridgeResourceAllocation.h>\r
#include <Protocol/PciIo.h>\r
#include <Protocol/LoadFile2.h>\r
#include <Protocol/PciRootBridgeIo.h>\r
#include <Protocol/PciHotPlugRequest.h>\r
#include <Protocol/DevicePath.h>\r
#include <Protocol/PciPlatform.h>\r
#include <Protocol/PciHotPlugInit.h>\r
#include <Protocol/Decompress.h>\r
#include <Protocol/BusSpecificDriverOverride.h>\r
#include <Protocol/IncompatiblePciDeviceSupport.h>\r
#include <Protocol/PciOverride.h>\r
#include <Protocol/PciEnumerationComplete.h>\r
#include <Protocol/IoMmu.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/UefiDriverEntryPoint.h>\r
#include <Library/BaseLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/ReportStatusCodeLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DevicePathLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PeCoffLib.h>\r
\r
#include <IndustryStandard/Pci.h>\r
#include <IndustryStandard/PeImage.h>\r
#include <IndustryStandard/Acpi.h>\r
\r
typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;\r
typedef struct _PCI_BAR                    PCI_BAR;\r
\r
#define EFI_PCI_RID(Bus, Device, Function)  (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)\r
#define EFI_PCI_BUS_OF_RID(RID)             ((UINT32)RID >> 8)\r
\r
#define     EFI_PCI_IOV_POLICY_ARI           0x0001\r
#define     EFI_PCI_IOV_POLICY_SRIOV         0x0002\r
#define     EFI_PCI_IOV_POLICY_MRIOV         0x0004\r
\r
typedef enum {\r
  PciBarTypeUnknown = 0,\r
  PciBarTypeIo16,\r
  PciBarTypeIo32,\r
  PciBarTypeMem32,\r
  PciBarTypePMem32,\r
  PciBarTypeMem64,\r
  PciBarTypePMem64,\r
  PciBarTypeIo,\r
  PciBarTypeMem,\r
  PciBarTypeMaxType\r
} PCI_BAR_TYPE;\r
\r
#include "ComponentName.h"\r
#include "PciIo.h"\r
#include "PciCommand.h"\r
#include "PciDeviceSupport.h"\r
#include "PciEnumerator.h"\r
#include "PciEnumeratorSupport.h"\r
#include "PciDriverOverride.h"\r
#include "PciRomTable.h"\r
#include "PciOptionRomSupport.h"\r
#include "PciPowerManagement.h"\r
#include "PciHotPlugSupport.h"\r
#include "PciLib.h"\r
\r
#define VGABASE1  0x3B0\r
#define VGALIMIT1 0x3BB\r
\r
#define VGABASE2  0x3C0\r
#define VGALIMIT2 0x3DF\r
\r
#define ISABASE   0x100\r
#define ISALIMIT  0x3FF\r
\r
//\r
// PCI BAR parameters\r
//\r
struct _PCI_BAR {\r
  UINT64        BaseAddress;\r
  UINT64        Length;\r
  UINT64        Alignment;\r
  PCI_BAR_TYPE  BarType;\r
  BOOLEAN       BarTypeFixed;\r
  UINT16        Offset;\r
};\r
\r
//\r
// defined in PCI Card Specification, 8.0\r
//\r
#define PCI_CARD_MEMORY_BASE_0                0x1C\r
#define PCI_CARD_MEMORY_LIMIT_0               0x20\r
#define PCI_CARD_MEMORY_BASE_1                0x24\r
#define PCI_CARD_MEMORY_LIMIT_1               0x28\r
#define PCI_CARD_IO_BASE_0_LOWER              0x2C\r
#define PCI_CARD_IO_BASE_0_UPPER              0x2E\r
#define PCI_CARD_IO_LIMIT_0_LOWER             0x30\r
#define PCI_CARD_IO_LIMIT_0_UPPER             0x32\r
#define PCI_CARD_IO_BASE_1_LOWER              0x34\r
#define PCI_CARD_IO_BASE_1_UPPER              0x36\r
#define PCI_CARD_IO_LIMIT_1_LOWER             0x38\r
#define PCI_CARD_IO_LIMIT_1_UPPER             0x3A\r
#define PCI_CARD_BRIDGE_CONTROL               0x3E\r
\r
#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8\r
#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9\r
\r
#define RB_IO_RANGE                           1\r
#define RB_MEM32_RANGE                        2\r
#define RB_PMEM32_RANGE                       3\r
#define RB_MEM64_RANGE                        4\r
#define RB_PMEM64_RANGE                       5\r
\r
#define PPB_BAR_0                             0\r
#define PPB_BAR_1                             1\r
#define PPB_IO_RANGE                          2\r
#define PPB_MEM32_RANGE                       3\r
#define PPB_PMEM32_RANGE                      4\r
#define PPB_PMEM64_RANGE                      5\r
#define PPB_MEM64_RANGE                       0xFF\r
\r
#define P2C_BAR_0                             0\r
#define P2C_MEM_1                             1\r
#define P2C_MEM_2                             2\r
#define P2C_IO_1                              3\r
#define P2C_IO_2                              4\r
\r
#define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001\r
#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002\r
#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004\r
#define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008\r
#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020\r
#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040\r
\r
#define PCI_MAX_HOST_BRIDGE_NUM               0x0010\r
\r
//\r
// Define option for attribute\r
//\r
#define EFI_SET_SUPPORTS    0\r
#define EFI_SET_ATTRIBUTES  1\r
\r
#define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')\r
\r
struct _PCI_IO_DEVICE {\r
  UINT32                                    Signature;\r
  EFI_HANDLE                                Handle;\r
  EFI_PCI_IO_PROTOCOL                       PciIo;\r
  LIST_ENTRY                                Link;\r
\r
  EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
  EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;\r
  EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;\r
\r
  //\r
  // PCI configuration space header type\r
  //\r
  PCI_TYPE00                                Pci;\r
\r
  //\r
  // Bus number, Device number, Function number\r
  //\r
  UINT8                                     BusNumber;\r
  UINT8                                     DeviceNumber;\r
  UINT8                                     FunctionNumber;\r
\r
  //\r
  // BAR for this PCI Device\r
  //\r
  PCI_BAR                                   PciBar[PCI_MAX_BAR];\r
\r
  //\r
  // The bridge device this pci device is subject to\r
  //\r
  PCI_IO_DEVICE                             *Parent;\r
\r
  //\r
  // A linked list for children Pci Device if it is bridge device\r
  //\r
  LIST_ENTRY                                ChildList;\r
\r
  //\r
  // TRUE if the PCI bus driver creates the handle for this PCI device\r
  //\r
  BOOLEAN                                   Registered;\r
\r
  //\r
  // TRUE if the PCI bus driver successfully allocates the resource required by\r
  // this PCI device\r
  //\r
  BOOLEAN                                   Allocated;\r
\r
  //\r
  // The attribute this PCI device currently set\r
  //\r
  UINT64                                    Attributes;\r
\r
  //\r
  // The attributes this PCI device actually supports\r
  //\r
  UINT64                                    Supports;\r
\r
  //\r
  // The resource decode the bridge supports\r
  //\r
  UINT32                                    Decodes;\r
\r
  //\r
  // TRUE if the ROM image is from the PCI Option ROM BAR\r
  //\r
  BOOLEAN                                   EmbeddedRom;\r
\r
  //\r
  // The OptionRom Size\r
  //\r
  UINT64                                    RomSize;\r
\r
  //\r
  // TRUE if all OpROM (in device or in platform specific position) have been processed\r
  //\r
  BOOLEAN                                   AllOpRomProcessed;\r
\r
  //\r
  // TRUE if there is any EFI driver in the OptionRom\r
  //\r
  BOOLEAN                                   BusOverride;\r
\r
  //\r
  // A list tracking reserved resource on a bridge device\r
  //\r
  LIST_ENTRY                                ReservedResourceList;\r
\r
  //\r
  // A list tracking image handle of platform specific overriding driver\r
  //\r
  LIST_ENTRY                                OptionRomDriverList;\r
\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;\r
  EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;\r
\r
  //\r
  // Bus number ranges for a PCI Root Bridge device\r
  //\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *BusNumberRanges;\r
\r
  BOOLEAN                                   IsPciExp;\r
  //\r
  // For SR-IOV\r
  //\r
  UINT8                                     PciExpressCapabilityOffset;\r
  UINT32                                    AriCapabilityOffset;\r
  UINT32                                    SrIovCapabilityOffset;\r
  UINT32                                    MrIovCapabilityOffset;\r
  PCI_BAR                                   VfPciBar[PCI_MAX_BAR];\r
  UINT32                                    SystemPageSize;\r
  UINT16                                    InitialVFs;\r
  UINT16                                    ReservedBusNum;\r
  //\r
  // Per PCI to PCI Bridge spec, I/O window is 4K aligned,\r
  // but some chipsets support non-standard I/O window alignments less than 4K.\r
  // This field is used to support this case.\r
  //\r
  UINT16                                    BridgeIoAlignment;\r
};\r
\r
#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_LINK(a) \\r
  CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r
\r
\r
\r
//\r
// Global Variables\r
//\r
extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;\r
extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;\r
extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;\r
extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;\r
extern BOOLEAN                                      gFullEnumeration;\r
extern UINTN                                        gPciHostBridgeNumber;\r
extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
extern UINT64                                       gAllOne;\r
extern UINT64                                       gAllZero;\r
extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;\r
extern EFI_PCI_OVERRIDE_PROTOCOL                    *gPciOverrideProtocol;\r
extern BOOLEAN                                      mReserveIsaAliases;\r
extern BOOLEAN                                      mReserveVgaAliases;\r
\r
/**\r
  Macro that checks whether device is a GFX device.\r
\r
  @param  _p      Specified device.\r
\r
  @retval TRUE    Device is a GFX device.\r
  @retval FALSE   Device is not a GFX device.\r
\r
**/\r
#define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
\r
/**\r
  Test to see if this driver supports ControllerHandle. Any ControllerHandle\r
  than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.\r
\r
  @param  This                Protocol instance pointer.\r
  @param  Controller          Handle of device to test.\r
  @param  RemainingDevicePath Optional parameter use to pick a specific child\r
                              device to start.\r
\r
  @retval EFI_SUCCESS         This driver supports this device.\r
  @retval EFI_ALREADY_STARTED This driver is already running on this device.\r
  @retval other               This driver does not support this device.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingSupported (\r
  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
  IN EFI_HANDLE                     Controller,\r
  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
  );\r
\r
/**\r
  Start this driver on ControllerHandle and enumerate Pci bus and start\r
  all device under PCI bus.\r
\r
  @param  This                 Protocol instance pointer.\r
  @param  Controller           Handle of device to bind driver to.\r
  @param  RemainingDevicePath  Optional parameter use to pick a specific child\r
                               device to start.\r
\r
  @retval EFI_SUCCESS          This driver is added to ControllerHandle.\r
  @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.\r
  @retval other                This driver does not support this device.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingStart (\r
  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
  IN EFI_HANDLE                     Controller,\r
  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
  );\r
\r
/**\r
  Stop this driver on ControllerHandle. Support stopping any child handles\r
  created by this driver.\r
\r
  @param  This              Protocol instance pointer.\r
  @param  Controller        Handle of device to stop driver on.\r
  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
                            children is zero stop the entire bus driver.\r
  @param  ChildHandleBuffer List of Child Handles to Stop.\r
\r
  @retval EFI_SUCCESS       This driver is removed ControllerHandle.\r
  @retval other             This driver was not removed from this device.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingStop (\r
  IN  EFI_DRIVER_BINDING_PROTOCOL   *This,\r
  IN  EFI_HANDLE                    Controller,\r
  IN  UINTN                         NumberOfChildren,\r
  IN  EFI_HANDLE                    *ChildHandleBuffer\r
  );\r
\r
#endif\r
Commit	Line	Data
9060e3ec	1	/** @file\r
	2	Header files and data structures needed by PCI Bus module.\r
	3	\r
221c8fd5	4	Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
cd5ebaa0	5	This program and the accompanying materials\r
9060e3ec	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	\r
	16	#ifndef _EFI_PCI_BUS_H_\r
	17	#define _EFI_PCI_BUS_H_\r
	18	\r
	19	#include <PiDxe.h>\r
	20	\r
	21	#include <Protocol/LoadedImage.h>\r
	22	#include <Protocol/PciHostBridgeResourceAllocation.h>\r
	23	#include <Protocol/PciIo.h>\r
	24	#include <Protocol/LoadFile2.h>\r
	25	#include <Protocol/PciRootBridgeIo.h>\r
	26	#include <Protocol/PciHotPlugRequest.h>\r
	27	#include <Protocol/DevicePath.h>\r
	28	#include <Protocol/PciPlatform.h>\r
	29	#include <Protocol/PciHotPlugInit.h>\r
	30	#include <Protocol/Decompress.h>\r
	31	#include <Protocol/BusSpecificDriverOverride.h>\r
	32	#include <Protocol/IncompatiblePciDeviceSupport.h>\r
	33	#include <Protocol/PciOverride.h>\r
	34	#include <Protocol/PciEnumerationComplete.h>\r
11a6cc5b	35	#include <Protocol/IoMmu.h>\r
9060e3ec	36	\r
	37	#include <Library/DebugLib.h>\r
	38	#include <Library/UefiDriverEntryPoint.h>\r
	39	#include <Library/BaseLib.h>\r
	40	#include <Library/UefiLib.h>\r
	41	#include <Library/BaseMemoryLib.h>\r
	42	#include <Library/ReportStatusCodeLib.h>\r
	43	#include <Library/MemoryAllocationLib.h>\r
	44	#include <Library/UefiBootServicesTableLib.h>\r
	45	#include <Library/DevicePathLib.h>\r
	46	#include <Library/PcdLib.h>\r
	47	#include <Library/PeCoffLib.h>\r
	48	\r
	49	#include <IndustryStandard/Pci.h>\r
	50	#include <IndustryStandard/PeImage.h>\r
	51	#include <IndustryStandard/Acpi.h>\r
	52	\r
	53	typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;\r
	54	typedef struct _PCI_BAR PCI_BAR;\r
	55	\r
	56	#define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)\r
	57	#define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)\r
	58	\r
	59	#define EFI_PCI_IOV_POLICY_ARI 0x0001\r
	60	#define EFI_PCI_IOV_POLICY_SRIOV 0x0002\r
	61	#define EFI_PCI_IOV_POLICY_MRIOV 0x0004\r
	62	\r
	63	typedef enum {\r
	64	PciBarTypeUnknown = 0,\r
	65	PciBarTypeIo16,\r
	66	PciBarTypeIo32,\r
	67	PciBarTypeMem32,\r
	68	PciBarTypePMem32,\r
	69	PciBarTypeMem64,\r
	70	PciBarTypePMem64,\r
	71	PciBarTypeIo,\r
	72	PciBarTypeMem,\r
	73	PciBarTypeMaxType\r
	74	} PCI_BAR_TYPE;\r
	75	\r
	76	#include "ComponentName.h"\r
	77	#include "PciIo.h"\r
	78	#include "PciCommand.h"\r
	79	#include "PciDeviceSupport.h"\r
	80	#include "PciEnumerator.h"\r
	81	#include "PciEnumeratorSupport.h"\r
	82	#include "PciDriverOverride.h"\r
	83	#include "PciRomTable.h"\r
	84	#include "PciOptionRomSupport.h"\r
	85	#include "PciPowerManagement.h"\r
	86	#include "PciHotPlugSupport.h"\r
	87	#include "PciLib.h"\r
	88	\r
	89	#define VGABASE1 0x3B0\r
	90	#define VGALIMIT1 0x3BB\r
	91	\r
	92	#define VGABASE2 0x3C0\r
	93	#define VGALIMIT2 0x3DF\r
	94	\r
	95	#define ISABASE 0x100\r
	96	#define ISALIMIT 0x3FF\r
	97	\r
	98	//\r
	99	// PCI BAR parameters\r
100	//\r
101	struct _PCI_BAR {\r
102	UINT64 BaseAddress;\r
103	UINT64 Length;\r
104	UINT64 Alignment;\r
105	PCI_BAR_TYPE BarType;\r
05070c1b	106	BOOLEAN BarTypeFixed;\r
d4048391	107	UINT16 Offset;\r
9060e3ec	108	};\r
	109	\r
	110	//\r
	111	// defined in PCI Card Specification, 8.0\r
	112	//\r
	113	#define PCI_CARD_MEMORY_BASE_0 0x1C\r
	114	#define PCI_CARD_MEMORY_LIMIT_0 0x20\r
	115	#define PCI_CARD_MEMORY_BASE_1 0x24\r
	116	#define PCI_CARD_MEMORY_LIMIT_1 0x28\r
	117	#define PCI_CARD_IO_BASE_0_LOWER 0x2C\r
	118	#define PCI_CARD_IO_BASE_0_UPPER 0x2E\r
	119	#define PCI_CARD_IO_LIMIT_0_LOWER 0x30\r
	120	#define PCI_CARD_IO_LIMIT_0_UPPER 0x32\r
	121	#define PCI_CARD_IO_BASE_1_LOWER 0x34\r
	122	#define PCI_CARD_IO_BASE_1_UPPER 0x36\r
	123	#define PCI_CARD_IO_LIMIT_1_LOWER 0x38\r
	124	#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A\r
	125	#define PCI_CARD_BRIDGE_CONTROL 0x3E\r
	126	\r
	127	#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8\r
	128	#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9\r
	129	\r
8db6a82c RN	130	#define RB_IO_RANGE 1\r
	131	#define RB_MEM32_RANGE 2\r
	132	#define RB_PMEM32_RANGE 3\r
	133	#define RB_MEM64_RANGE 4\r
	134	#define RB_PMEM64_RANGE 5\r
	135	\r
9060e3ec	136	#define PPB_BAR_0 0\r
	137	#define PPB_BAR_1 1\r
	138	#define PPB_IO_RANGE 2\r
	139	#define PPB_MEM32_RANGE 3\r
	140	#define PPB_PMEM32_RANGE 4\r
	141	#define PPB_PMEM64_RANGE 5\r
	142	#define PPB_MEM64_RANGE 0xFF\r
	143	\r
	144	#define P2C_BAR_0 0\r
	145	#define P2C_MEM_1 1\r
	146	#define P2C_MEM_2 2\r
	147	#define P2C_IO_1 3\r
	148	#define P2C_IO_2 4\r
	149	\r
	150	#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r
	151	#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r
	152	#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r
	153	#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r
	154	#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
	155	#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r
	156	#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r
	157	\r
	158	#define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r
	159	\r
	160	//\r
	161	// Define option for attribute\r
	162	//\r
	163	#define EFI_SET_SUPPORTS 0\r
	164	#define EFI_SET_ATTRIBUTES 1\r
	165	\r
	166	#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')\r
	167	\r
	168	struct _PCI_IO_DEVICE {\r
	169	UINT32 Signature;\r
	170	EFI_HANDLE Handle;\r
	171	EFI_PCI_IO_PROTOCOL PciIo;\r
	172	LIST_ENTRY Link;\r
	173	\r
	174	EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
	175	EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
	176	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
	177	EFI_LOAD_FILE2_PROTOCOL LoadFile2;\r
	178	\r
	179	//\r
	180	// PCI configuration space header type\r
	181	//\r
	182	PCI_TYPE00 Pci;\r
	183	\r
	184	//\r
	185	// Bus number, Device number, Function number\r
	186	//\r
	187	UINT8 BusNumber;\r
	188	UINT8 DeviceNumber;\r
	189	UINT8 FunctionNumber;\r
	190	\r
	191	//\r
	192	// BAR for this PCI Device\r
	193	//\r
	194	PCI_BAR PciBar[PCI_MAX_BAR];\r
	195	\r
	196	//\r
	197	// The bridge device this pci device is subject to\r
	198	//\r
	199	PCI_IO_DEVICE *Parent;\r
200	\r
201	//\r
202	// A linked list for children Pci Device if it is bridge device\r
203	//\r
204	LIST_ENTRY ChildList;\r
205	\r
206	//\r
ed356b9e	207	// TRUE if the PCI bus driver creates the handle for this PCI device\r
9060e3ec	208	//\r
	209	BOOLEAN Registered;\r
	210	\r
	211	//\r
	212	// TRUE if the PCI bus driver successfully allocates the resource required by\r
	213	// this PCI device\r
	214	//\r
	215	BOOLEAN Allocated;\r
	216	\r
	217	//\r
	218	// The attribute this PCI device currently set\r
	219	//\r
	220	UINT64 Attributes;\r
	221	\r
	222	//\r
	223	// The attributes this PCI device actually supports\r
	224	//\r
	225	UINT64 Supports;\r
	226	\r
	227	//\r
	228	// The resource decode the bridge supports\r
	229	//\r
	230	UINT32 Decodes;\r
	231	\r
4ed4e19c	232	//\r
	233	// TRUE if the ROM image is from the PCI Option ROM BAR\r
	234	//\r
	235	BOOLEAN EmbeddedRom;\r
	236	\r
9060e3ec	237	//\r
	238	// The OptionRom Size\r
	239	//\r
	240	UINT64 RomSize;\r
	241	\r
9060e3ec	242	//\r
	243	// TRUE if all OpROM (in device or in platform specific position) have been processed\r
	244	//\r
	245	BOOLEAN AllOpRomProcessed;\r
	246	\r
	247	//\r
	248	// TRUE if there is any EFI driver in the OptionRom\r
	249	//\r
	250	BOOLEAN BusOverride;\r
	251	\r
	252	//\r
	253	// A list tracking reserved resource on a bridge device\r
	254	//\r
	255	LIST_ENTRY ReservedResourceList;\r
	256	\r
	257	//\r
	258	// A list tracking image handle of platform specific overriding driver\r
	259	//\r
	260	LIST_ENTRY OptionRomDriverList;\r
	261	\r
	262	EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r
	263	EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r
	264	\r
306bbe82	265	//\r
	266	// Bus number ranges for a PCI Root Bridge device\r
	267	//\r
	268	EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;\r
	269	\r
9060e3ec	270	BOOLEAN IsPciExp;\r
	271	//\r
	272	// For SR-IOV\r
	273	//\r
	274	UINT8 PciExpressCapabilityOffset;\r
	275	UINT32 AriCapabilityOffset;\r
	276	UINT32 SrIovCapabilityOffset;\r
	277	UINT32 MrIovCapabilityOffset;\r
	278	PCI_BAR VfPciBar[PCI_MAX_BAR];\r
	279	UINT32 SystemPageSize;\r
	280	UINT16 InitialVFs;\r
	281	UINT16 ReservedBusNum;\r
1ef26783	282	//\r
1ef26783	283	// Per PCI to PCI Bridge spec, I/O window is 4K aligned,\r
ed356b9e	284	// but some chipsets support non-standard I/O window alignments less than 4K.\r
1ef26783	285	// This field is used to support this case.\r
	286	//\r
	287	UINT16 BridgeIoAlignment;\r
9060e3ec	288	};\r
	289	\r
	290	#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
	291	CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
	292	\r
	293	#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
	294	CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
	295	\r
	296	#define PCI_IO_DEVICE_FROM_LINK(a) \\r
	297	CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
	298	\r
	299	#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r
	300	CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r
	301	\r
	302	\r
	303	\r
	304	//\r
	305	// Global Variables\r
	306	//\r
ea669c1b	307	extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;\r
9060e3ec	308	extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r
	309	extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r
	310	extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;\r
	311	extern BOOLEAN gFullEnumeration;\r
	312	extern UINTN gPciHostBridgeNumber;\r
	313	extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
	314	extern UINT64 gAllOne;\r
	315	extern UINT64 gAllZero;\r
	316	extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r
	317	extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;\r
e0ee9d93	318	extern BOOLEAN mReserveIsaAliases;\r
e0ee9d93	319	extern BOOLEAN mReserveVgaAliases;\r
9060e3ec	320	\r
	321	/**\r
	322	Macro that checks whether device is a GFX device.\r
	323	\r
	324	@param _p Specified device.\r
	325	\r
ed356b9e GL	326	@retval TRUE Device is a GFX device.\r
ed356b9e GL	327	@retval FALSE Device is not a GFX device.\r
9060e3ec	328	\r
	329	**/\r
	330	#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
	331	\r
	332	/**\r
	333	Test to see if this driver supports ControllerHandle. Any ControllerHandle\r
	334	than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.\r
	335	\r
	336	@param This Protocol instance pointer.\r
	337	@param Controller Handle of device to test.\r
ed356b9e	338	@param RemainingDevicePath Optional parameter use to pick a specific child\r
9060e3ec	339	device to start.\r
	340	\r
	341	@retval EFI_SUCCESS This driver supports this device.\r
	342	@retval EFI_ALREADY_STARTED This driver is already running on this device.\r
	343	@retval other This driver does not support this device.\r
	344	\r
	345	**/\r
	346	EFI_STATUS\r
	347	EFIAPI\r
	348	PciBusDriverBindingSupported (\r
	349	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
	350	IN EFI_HANDLE Controller,\r
	351	IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
	352	);\r
	353	\r
	354	/**\r
	355	Start this driver on ControllerHandle and enumerate Pci bus and start\r
	356	all device under PCI bus.\r
	357	\r
	358	@param This Protocol instance pointer.\r
	359	@param Controller Handle of device to bind driver to.\r
ed356b9e	360	@param RemainingDevicePath Optional parameter use to pick a specific child\r
9060e3ec	361	device to start.\r
	362	\r
	363	@retval EFI_SUCCESS This driver is added to ControllerHandle.\r
	364	@retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.\r
	365	@retval other This driver does not support this device.\r
	366	\r
	367	**/\r
	368	EFI_STATUS\r
	369	EFIAPI\r
	370	PciBusDriverBindingStart (\r
	371	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
	372	IN EFI_HANDLE Controller,\r
	373	IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
	374	);\r
	375	\r
	376	/**\r
ed356b9e	377	Stop this driver on ControllerHandle. Support stopping any child handles\r
9060e3ec	378	created by this driver.\r
	379	\r
	380	@param This Protocol instance pointer.\r
	381	@param Controller Handle of device to stop driver on.\r
	382	@param NumberOfChildren Number of Handles in ChildHandleBuffer. If number of\r
	383	children is zero stop the entire bus driver.\r
	384	@param ChildHandleBuffer List of Child Handles to Stop.\r
	385	\r
	386	@retval EFI_SUCCESS This driver is removed ControllerHandle.\r
	387	@retval other This driver was not removed from this device.\r
	388	\r
	389	**/\r
	390	EFI_STATUS\r
	391	EFIAPI\r
	392	PciBusDriverBindingStop (\r
	393	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
	394	IN EFI_HANDLE Controller,\r
	395	IN UINTN NumberOfChildren,\r
	396	IN EFI_HANDLE *ChildHandleBuffer\r
	397	);\r
	398	\r
	399	#endif\r