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MdeModulePkg/PciBusDxe: reference gFullEnumeration in one file
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciEnumerator.c
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9060e3ec 1/** @file\r
2 PCI eunmeration implementation on entire PCI bus system for PCI Bus module.\r
3\r
26329817 4Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
25a26646 5(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
cd5ebaa0 6This program and the accompanying materials\r
9060e3ec 7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include "PciBus.h"\r
17\r
18/**\r
19 This routine is used to enumerate entire pci bus system\r
20 in a given platform.\r
21\r
26329817
RN		 22 @param Controller Parent controller handle.\r
23 @param HostBridgeHandle Host bridge handle.\r
9060e3ec 24\r
25 @retval EFI_SUCCESS PCI enumeration finished successfully.\r
26 @retval other Some error occurred when enumerating the pci bus system.\r
27\r
28**/\r
29EFI_STATUS\r
30PciEnumerator (\r
26329817
RN		 31 IN EFI_HANDLE Controller,\r
32 IN EFI_HANDLE HostBridgeHandle\r
9060e3ec 33 )\r
34{\r
9060e3ec 35 EFI_STATUS Status;\r
36 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc;\r
9060e3ec 37\r
38 //\r
39 // Get the pci host bridge resource allocation protocol\r
40 //\r
41 Status = gBS->OpenProtocol (\r
42 HostBridgeHandle,\r
43 &gEfiPciHostBridgeResourceAllocationProtocolGuid,\r
44 (VOID **) &PciResAlloc,\r
45 gPciBusDriverBinding.DriverBindingHandle,\r
46 Controller,\r
47 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
48 );\r
49\r
50 if (EFI_ERROR (Status)) {\r
51 return Status;\r
52 }\r
53\r
54 //\r
55 // Notify the pci bus enumeration is about to begin\r
56 //\r
ea8d98fa
OM		 57 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginEnumeration);\r
58\r
59 if (EFI_ERROR (Status)) {\r
60 return Status;\r
61 }\r
9060e3ec 62\r
63 //\r
64 // Start the bus allocation phase\r
65 //\r
66 Status = PciHostBridgeEnumerator (PciResAlloc);\r
67\r
68 if (EFI_ERROR (Status)) {\r
69 return Status;\r
70 }\r
71\r
72 //\r
73 // Submit the resource request\r
74 //\r
75 Status = PciHostBridgeResourceAllocator (PciResAlloc);\r
76\r
77 if (EFI_ERROR (Status)) {\r
78 return Status;\r
79 }\r
80\r
81 //\r
82 // Notify the pci bus enumeration is about to complete\r
83 //\r
ea8d98fa
OM		 84 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeEndEnumeration);\r
85\r
86 if (EFI_ERROR (Status)) {\r
87 return Status;\r
88 }\r
9060e3ec 89\r
90 //\r
91 // Process P2C\r
92 //\r
93 Status = PciHostBridgeP2CProcess (PciResAlloc);\r
94\r
95 if (EFI_ERROR (Status)) {\r
96 return Status;\r
97 }\r
98\r
99 //\r
100 // Process attributes for devices on this host bridge\r
101 //\r
102 Status = PciHostBridgeDeviceAttribute (PciResAlloc);\r
103 if (EFI_ERROR (Status)) {\r
104 return Status;\r
105 }\r
106\r
9060e3ec 107 Status = gBS->InstallProtocolInterface (\r
d838c744 108 &HostBridgeHandle,\r
9060e3ec 109 &gEfiPciEnumerationCompleteProtocolGuid,\r
110 EFI_NATIVE_INTERFACE,\r
111 NULL\r
112 );\r
113 if (EFI_ERROR (Status)) {\r
114 return Status;\r
115 }\r
116\r
117 return EFI_SUCCESS;\r
118}\r
119\r
120/**\r
121 Enumerate PCI root bridge.\r
122\r
123 @param PciResAlloc Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
124 @param RootBridgeDev Instance of root bridge device.\r
125\r
126 @retval EFI_SUCCESS Successfully enumerated root bridge.\r
127 @retval other Failed to enumerate root bridge.\r
128\r
129**/\r
130EFI_STATUS\r
131PciRootBridgeEnumerator (\r
132 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r
133 IN PCI_IO_DEVICE *RootBridgeDev\r
134 )\r
135{\r
136 EFI_STATUS Status;\r
137 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
306bbe82 138 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration1;\r
139 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration2;\r
140 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration3;\r
9060e3ec 141 UINT8 SubBusNumber;\r
142 UINT8 StartBusNumber;\r
143 UINT8 PaddedBusRange;\r
144 EFI_HANDLE RootBridgeHandle;\r
306bbe82 145 UINT8 Desc;\r
146 UINT64 AddrLen;\r
147 UINT64 AddrRangeMin;\r
9060e3ec 148\r
149 SubBusNumber = 0;\r
150 StartBusNumber = 0;\r
151 PaddedBusRange = 0;\r
152\r
153 //\r
154 // Get the root bridge handle\r
155 //\r
156 RootBridgeHandle = RootBridgeDev->Handle;\r
157\r
158 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
159 EFI_PROGRESS_CODE,\r
fe91c992 160 EFI_IO_BUS_PCI | EFI_IOB_PCI_BUS_ENUM,\r
9060e3ec 161 RootBridgeDev->DevicePath\r
162 );\r
163\r
164 //\r
165 // Get the Bus information\r
166 //\r
167 Status = PciResAlloc->StartBusEnumeration (\r
168 PciResAlloc,\r
169 RootBridgeHandle,\r
170 (VOID **) &Configuration\r
171 );\r
172\r
173 if (EFI_ERROR (Status)) {\r
174 return Status;\r
175 }\r
176\r
306bbe82 177 if (Configuration == NULL || Configuration->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
178 return EFI_INVALID_PARAMETER;\r
179 }\r
180 RootBridgeDev->BusNumberRanges = Configuration;\r
181\r
182 //\r
183 // Sort the descriptors in ascending order\r
184 //\r
185 for (Configuration1 = Configuration; Configuration1->Desc != ACPI_END_TAG_DESCRIPTOR; Configuration1++) {\r
186 Configuration2 = Configuration1;\r
187 for (Configuration3 = Configuration1 + 1; Configuration3->Desc != ACPI_END_TAG_DESCRIPTOR; Configuration3++) {\r
188 if (Configuration2->AddrRangeMin > Configuration3->AddrRangeMin) {\r
189 Configuration2 = Configuration3;\r
190 }\r
191 }\r
192 //\r
193 // All other fields other than AddrRangeMin and AddrLen are ignored in a descriptor,\r
194 // so only need to swap these two fields.\r
195 //\r
196 if (Configuration2 != Configuration1) {\r
197 AddrRangeMin = Configuration1->AddrRangeMin;\r
198 Configuration1->AddrRangeMin = Configuration2->AddrRangeMin;\r
199 Configuration2->AddrRangeMin = AddrRangeMin;\r
200 \r
201 AddrLen = Configuration1->AddrLen;\r
202 Configuration1->AddrLen = Configuration2->AddrLen;\r
203 Configuration2->AddrLen = AddrLen;\r
204 }\r
205 }\r
206\r
9060e3ec 207 //\r
208 // Get the bus number to start with\r
209 //\r
210 StartBusNumber = (UINT8) (Configuration->AddrRangeMin);\r
9060e3ec 211\r
212 //\r
213 // Initialize the subordinate bus number\r
214 //\r
215 SubBusNumber = StartBusNumber;\r
216\r
217 //\r
218 // Reset all assigned PCI bus number\r
219 //\r
220 ResetAllPpbBusNumber (\r
221 RootBridgeDev,\r
222 StartBusNumber\r
223 );\r
224\r
225 //\r
226 // Assign bus number\r
227 //\r
228 Status = PciScanBus (\r
229 RootBridgeDev,\r
306bbe82 230 StartBusNumber,\r
9060e3ec 231 &SubBusNumber,\r
232 &PaddedBusRange\r
233 );\r
234\r
235 if (EFI_ERROR (Status)) {\r
236 return Status;\r
237 }\r
238\r
239\r
240 //\r
241 // Assign max bus number scanned\r
242 //\r
9060e3ec 243\r
306bbe82 244 Status = PciAllocateBusNumber (RootBridgeDev, SubBusNumber, PaddedBusRange, &SubBusNumber);\r
245 if (EFI_ERROR (Status)) {\r
246 return Status;\r
247 } \r
248\r
249 //\r
250 // Find the bus range which contains the higest bus number, then returns the number of buses\r
251 // that should be decoded.\r
252 //\r
253 while (Configuration->AddrRangeMin + Configuration->AddrLen - 1 < SubBusNumber) {\r
254 Configuration++;\r
255 }\r
256 AddrLen = Configuration->AddrLen;\r
257 Configuration->AddrLen = SubBusNumber - Configuration->AddrRangeMin + 1;\r
258\r
259 //\r
260 // Save the Desc field of the next descriptor. Mark the next descriptor as an END descriptor.\r
261 //\r
262 Configuration++;\r
263 Desc = Configuration->Desc;\r
264 Configuration->Desc = ACPI_END_TAG_DESCRIPTOR;\r
265 \r
9060e3ec 266 //\r
267 // Set bus number\r
268 //\r
269 Status = PciResAlloc->SetBusNumbers (\r
270 PciResAlloc,\r
271 RootBridgeHandle,\r
306bbe82 272 RootBridgeDev->BusNumberRanges\r
9060e3ec 273 );\r
274\r
306bbe82 275 //\r
276 // Restore changed fields\r
277 //\r
278 Configuration->Desc = Desc;\r
279 (Configuration - 1)->AddrLen = AddrLen;\r
280 \r
281 return Status;\r
9060e3ec 282}\r
283\r
284/**\r
285 This routine is used to process all PCI devices' Option Rom\r
286 on a certain root bridge.\r
287\r
288 @param Bridge Given parent's root bridge.\r
289 @param RomBase Base address of ROM driver loaded from.\r
290 @param MaxLength Maximum rom size.\r
291\r
292**/\r
293VOID\r
294ProcessOptionRom (\r
295 IN PCI_IO_DEVICE *Bridge,\r
296 IN UINT64 RomBase,\r
297 IN UINT64 MaxLength\r
298 )\r
299{\r
300 LIST_ENTRY *CurrentLink;\r
301 PCI_IO_DEVICE *Temp;\r
302\r
303 //\r
304 // Go through bridges to reach all devices\r
305 //\r
306 CurrentLink = Bridge->ChildList.ForwardLink;\r
307 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
308 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
309 if (!IsListEmpty (&Temp->ChildList)) {\r
310\r
311 //\r
312 // Go further to process the option rom under this bridge\r
313 //\r
314 ProcessOptionRom (Temp, RomBase, MaxLength);\r
315 }\r
316\r
317 if (Temp->RomSize != 0 && Temp->RomSize <= MaxLength) {\r
318\r
319 //\r
320 // Load and process the option rom\r
321 //\r
322 LoadOpRomImage (Temp, RomBase);\r
323 }\r
324\r
325 CurrentLink = CurrentLink->ForwardLink;\r
326 }\r
327}\r
328\r
329/**\r
330 This routine is used to assign bus number to the given PCI bus system\r
331\r
332 @param Bridge Parent root bridge instance.\r
333 @param StartBusNumber Number of beginning.\r
334 @param SubBusNumber The number of sub bus.\r
335\r
336 @retval EFI_SUCCESS Successfully assigned bus number.\r
337 @retval EFI_DEVICE_ERROR Failed to assign bus number.\r
338\r
339**/\r
340EFI_STATUS\r
341PciAssignBusNumber (\r
342 IN PCI_IO_DEVICE *Bridge,\r
343 IN UINT8 StartBusNumber,\r
344 OUT UINT8 *SubBusNumber\r
345 )\r
346{\r
347 EFI_STATUS Status;\r
348 PCI_TYPE00 Pci;\r
349 UINT8 Device;\r
350 UINT8 Func;\r
351 UINT64 Address;\r
352 UINTN SecondBus;\r
353 UINT16 Register;\r
354 UINT8 Register8;\r
355 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
356\r
357 PciRootBridgeIo = Bridge->PciRootBridgeIo;\r
358\r
359 SecondBus = 0;\r
360 Register = 0;\r
361\r
362 *SubBusNumber = StartBusNumber;\r
363\r
364 //\r
365 // First check to see whether the parent is ppb\r
366 //\r
367 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
368 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
369\r
370 //\r
371 // Check to see whether a pci device is present\r
372 //\r
373 Status = PciDevicePresent (\r
374 PciRootBridgeIo,\r
375 &Pci,\r
376 StartBusNumber,\r
377 Device,\r
378 Func\r
379 );\r
380\r
25a26646
JS		 381 if (EFI_ERROR (Status) && Func == 0) {\r
382 //\r
383 // go to next device if there is no Function 0\r
384 //\r
385 break;\r
386 }\r
387\r
9060e3ec 388 if (!EFI_ERROR (Status) &&\r
389 (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {\r
390\r
391 //\r
392 // Reserved one bus for cardbus bridge\r
393 //\r
306bbe82 394 Status = PciAllocateBusNumber (Bridge, *SubBusNumber, 1, SubBusNumber);\r
395 if (EFI_ERROR (Status)) {\r
396 return Status;\r
397 }\r
398 SecondBus = *SubBusNumber;\r
9060e3ec 399\r
400 Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);\r
401\r
402 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
403\r
404 Status = PciRootBridgeIo->Pci.Write (\r
405 PciRootBridgeIo,\r
406 EfiPciWidthUint16,\r
407 Address,\r
408 1,\r
409 &Register\r
410 );\r
411\r
412 //\r
413 // Initialize SubBusNumber to SecondBus\r
414 //\r
415 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
416 Status = PciRootBridgeIo->Pci.Write (\r
417 PciRootBridgeIo,\r
418 EfiPciWidthUint8,\r
419 Address,\r
420 1,\r
421 SubBusNumber\r
422 );\r
423 //\r
424 // If it is PPB, resursively search down this bridge\r
425 //\r
426 if (IS_PCI_BRIDGE (&Pci)) {\r
427\r
428 Register8 = 0xFF;\r
429 Status = PciRootBridgeIo->Pci.Write (\r
430 PciRootBridgeIo,\r
431 EfiPciWidthUint8,\r
432 Address,\r
433 1,\r
434 &Register8\r
435 );\r
436\r
437 Status = PciAssignBusNumber (\r
438 Bridge,\r
439 (UINT8) (SecondBus),\r
440 SubBusNumber\r
441 );\r
442\r
443 if (EFI_ERROR (Status)) {\r
444 return EFI_DEVICE_ERROR;\r
445 }\r
446 }\r
447\r
448 //\r
449 // Set the current maximum bus number under the PPB\r
450 //\r
451 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
452\r
453 Status = PciRootBridgeIo->Pci.Write (\r
454 PciRootBridgeIo,\r
455 EfiPciWidthUint8,\r
456 Address,\r
457 1,\r
458 SubBusNumber\r
459 );\r
460\r
461 }\r
462\r
463 if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
464\r
465 //\r
466 // Skip sub functions, this is not a multi function device\r
467 //\r
468 Func = PCI_MAX_FUNC;\r
469 }\r
470 }\r
471 }\r
472\r
473 return EFI_SUCCESS;\r
474}\r
475\r
476/**\r
477 This routine is used to determine the root bridge attribute by interfacing\r
478 the host bridge resource allocation protocol.\r
479\r
480 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
481 @param RootBridgeDev Root bridge instance\r
482\r
483 @retval EFI_SUCCESS Successfully got root bridge's attribute.\r
484 @retval other Failed to get attribute.\r
485\r
486**/\r
487EFI_STATUS\r
488DetermineRootBridgeAttributes (\r
489 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r
490 IN PCI_IO_DEVICE *RootBridgeDev\r
491 )\r
492{\r
493 UINT64 Attributes;\r
494 EFI_STATUS Status;\r
495 EFI_HANDLE RootBridgeHandle;\r
496\r
497 Attributes = 0;\r
498 RootBridgeHandle = RootBridgeDev->Handle;\r
499\r
500 //\r
501 // Get root bridge attribute by calling into pci host bridge resource allocation protocol\r
502 //\r
503 Status = PciResAlloc->GetAllocAttributes (\r
504 PciResAlloc,\r
505 RootBridgeHandle,\r
506 &Attributes\r
507 );\r
508\r
509 if (EFI_ERROR (Status)) {\r
510 return Status;\r
511 }\r
512\r
513 //\r
514 // Here is the point where PCI bus driver calls HOST bridge allocation protocol\r
515 // Currently we hardcoded for ea815\r
516 //\r
517 if ((Attributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {\r
518 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED;\r
519 }\r
520\r
521 if ((Attributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0) {\r
60516202 522 RootBridgeDev->Decodes |= EFI_BRIDGE_MEM64_DECODE_SUPPORTED;\r
9060e3ec 523 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED;\r
524 }\r
525\r
526 RootBridgeDev->Decodes |= EFI_BRIDGE_MEM32_DECODE_SUPPORTED;\r
527 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;\r
528 RootBridgeDev->Decodes |= EFI_BRIDGE_IO16_DECODE_SUPPORTED;\r
529\r
530 return EFI_SUCCESS;\r
531}\r
532\r
533/**\r
534 Get Max Option Rom size on specified bridge.\r
535\r
536 @param Bridge Given bridge device instance.\r
537\r
538 @return Max size of option rom needed.\r
539\r
540**/\r
541UINT64\r
542GetMaxOptionRomSize (\r
543 IN PCI_IO_DEVICE *Bridge\r
544 )\r
545{\r
546 LIST_ENTRY *CurrentLink;\r
547 PCI_IO_DEVICE *Temp;\r
548 UINT64 MaxOptionRomSize;\r
549 UINT64 TempOptionRomSize;\r
550\r
551 MaxOptionRomSize = 0;\r
552\r
553 //\r
554 // Go through bridges to reach all devices\r
555 //\r
556 CurrentLink = Bridge->ChildList.ForwardLink;\r
557 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
558 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
559 if (!IsListEmpty (&Temp->ChildList)) {\r
560\r
561 //\r
562 // Get max option rom size under this bridge\r
563 //\r
564 TempOptionRomSize = GetMaxOptionRomSize (Temp);\r
565\r
566 //\r
567 // Compare with the option rom size of the bridge\r
568 // Get the larger one\r
569 //\r
570 if (Temp->RomSize > TempOptionRomSize) {\r
571 TempOptionRomSize = Temp->RomSize;\r
572 }\r
573\r
574 } else {\r
575\r
576 //\r
577 // For devices get the rom size directly\r
578 //\r
579 TempOptionRomSize = Temp->RomSize;\r
580 }\r
581\r
582 //\r
583 // Get the largest rom size on this bridge\r
584 //\r
585 if (TempOptionRomSize > MaxOptionRomSize) {\r
586 MaxOptionRomSize = TempOptionRomSize;\r
587 }\r
588\r
589 CurrentLink = CurrentLink->ForwardLink;\r
590 }\r
591\r
592 return MaxOptionRomSize;\r
593}\r
594\r
595/**\r
596 Process attributes of devices on this host bridge\r
597\r
598 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
599\r
600 @retval EFI_SUCCESS Successfully process attribute.\r
601 @retval EFI_NOT_FOUND Can not find the specific root bridge device.\r
602 @retval other Failed to determine the root bridge device's attribute.\r
603\r
604**/\r
605EFI_STATUS\r
606PciHostBridgeDeviceAttribute (\r
607 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
608 )\r
609{\r
610 EFI_HANDLE RootBridgeHandle;\r
611 PCI_IO_DEVICE *RootBridgeDev;\r
612 EFI_STATUS Status;\r
613\r
614 RootBridgeHandle = NULL;\r
615\r
616 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
617\r
618 //\r
619 // Get RootBridg Device by handle\r
620 //\r
621 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
622\r
623 if (RootBridgeDev == NULL) {\r
624 return EFI_NOT_FOUND;\r
625 }\r
626\r
627 //\r
628 // Set the attributes for devcies behind the Root Bridge\r
629 //\r
630 Status = DetermineDeviceAttribute (RootBridgeDev);\r
631 if (EFI_ERROR (Status)) {\r
632 return Status;\r
633 }\r
634\r
635 }\r
636\r
637 return EFI_SUCCESS;\r
638}\r
639\r
640/**\r
641 Get resource allocation status from the ACPI resource descriptor.\r
642\r
643 @param AcpiConfig Point to Acpi configuration table.\r
644 @param IoResStatus Return the status of I/O resource.\r
645 @param Mem32ResStatus Return the status of 32-bit Memory resource.\r
646 @param PMem32ResStatus Return the status of 32-bit Prefetchable Memory resource.\r
647 @param Mem64ResStatus Return the status of 64-bit Memory resource.\r
648 @param PMem64ResStatus Return the status of 64-bit Prefetchable Memory resource.\r
649\r
650**/\r
651VOID\r
652GetResourceAllocationStatus (\r
653 VOID *AcpiConfig,\r
654 OUT UINT64 *IoResStatus,\r
655 OUT UINT64 *Mem32ResStatus,\r
656 OUT UINT64 *PMem32ResStatus,\r
657 OUT UINT64 *Mem64ResStatus,\r
658 OUT UINT64 *PMem64ResStatus\r
659 )\r
660{\r
661 UINT8 *Temp;\r
662 UINT64 ResStatus;\r
663 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ACPIAddressDesc;\r
664\r
665 Temp = (UINT8 *) AcpiConfig;\r
666\r
667 while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
668\r
669 ACPIAddressDesc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
670 ResStatus = ACPIAddressDesc->AddrTranslationOffset;\r
671\r
672 switch (ACPIAddressDesc->ResType) {\r
673 case 0:\r
674 if (ACPIAddressDesc->AddrSpaceGranularity == 32) {\r
675 if (ACPIAddressDesc->SpecificFlag == 0x06) {\r
676 //\r
677 // Pmem32\r
678 //\r
679 *PMem32ResStatus = ResStatus;\r
680 } else {\r
681 //\r
682 // Mem32\r
683 //\r
684 *Mem32ResStatus = ResStatus;\r
685 }\r
686 }\r
687\r
688 if (ACPIAddressDesc->AddrSpaceGranularity == 64) {\r
689 if (ACPIAddressDesc->SpecificFlag == 0x06) {\r
690 //\r
691 // PMem64\r
692 //\r
693 *PMem64ResStatus = ResStatus;\r
694 } else {\r
695 //\r
696 // Mem64\r
697 //\r
698 *Mem64ResStatus = ResStatus;\r
699 }\r
700 }\r
701\r
702 break;\r
703\r
704 case 1:\r
705 //\r
706 // Io\r
707 //\r
708 *IoResStatus = ResStatus;\r
709 break;\r
710\r
711 default:\r
712 break;\r
713 }\r
714\r
715 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
716 }\r
717}\r
718\r
719/**\r
720 Remove a PCI device from device pool and mark its bar.\r
721\r
722 @param PciDevice Instance of Pci device.\r
723\r
724 @retval EFI_SUCCESS Successfully remove the PCI device.\r
725 @retval EFI_ABORTED Pci device is a root bridge or a PCI-PCI bridge.\r
726\r
727**/\r
728EFI_STATUS\r
729RejectPciDevice (\r
730 IN PCI_IO_DEVICE *PciDevice\r
731 )\r
732{\r
733 PCI_IO_DEVICE *Bridge;\r
734 PCI_IO_DEVICE *Temp;\r
735 LIST_ENTRY *CurrentLink;\r
736\r
737 //\r
738 // Remove the padding resource from a bridge\r
739 //\r
740 if ( IS_PCI_BRIDGE(&PciDevice->Pci) &&\r
741 PciDevice->ResourcePaddingDescriptors != NULL ) {\r
742 FreePool (PciDevice->ResourcePaddingDescriptors);\r
743 PciDevice->ResourcePaddingDescriptors = NULL;\r
744 return EFI_SUCCESS;\r
745 }\r
746\r
747 //\r
748 // Skip RB and PPB\r
749 //\r
750 if (IS_PCI_BRIDGE (&PciDevice->Pci) || (PciDevice->Parent == NULL)) {\r
751 return EFI_ABORTED;\r
752 }\r
753\r
754 if (IS_CARDBUS_BRIDGE (&PciDevice->Pci)) {\r
755 //\r
756 // Get the root bridge device\r
757 //\r
758 Bridge = PciDevice;\r
759 while (Bridge->Parent != NULL) {\r
760 Bridge = Bridge->Parent;\r
761 }\r
762\r
763 RemoveAllPciDeviceOnBridge (Bridge->Handle, PciDevice);\r
764\r
765 //\r
766 // Mark its bar\r
767 //\r
768 InitializeP2C (PciDevice);\r
769 }\r
770\r
771 //\r
772 // Remove the device\r
773 //\r
774 Bridge = PciDevice->Parent;\r
775 CurrentLink = Bridge->ChildList.ForwardLink;\r
776 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
777 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
778 if (Temp == PciDevice) {\r
779 InitializePciDevice (Temp);\r
780 RemoveEntryList (CurrentLink);\r
9060e3ec 781 return EFI_SUCCESS;\r
782 }\r
783\r
784 CurrentLink = CurrentLink->ForwardLink;\r
785 }\r
786\r
787 return EFI_ABORTED;\r
788}\r
789\r
790/**\r
791 Determine whethter a PCI device can be rejected.\r
792\r
793 @param PciResNode Pointer to Pci resource node instance.\r
794\r
795 @retval TRUE The PCI device can be rejected.\r
796 @retval TRUE The PCI device cannot be rejected.\r
797\r
798**/\r
799BOOLEAN\r
800IsRejectiveDevice (\r
801 IN PCI_RESOURCE_NODE *PciResNode\r
802 )\r
803{\r
804 PCI_IO_DEVICE *Temp;\r
805\r
806 Temp = PciResNode->PciDev;\r
807\r
808 //\r
809 // Ensure the device is present\r
810 //\r
811 if (Temp == NULL) {\r
812 return FALSE;\r
813 }\r
814\r
815 //\r
816 // PPB and RB should go ahead\r
817 //\r
818 if (IS_PCI_BRIDGE (&Temp->Pci) || (Temp->Parent == NULL)) {\r
819 return TRUE;\r
820 }\r
821\r
822 //\r
823 // Skip device on Bus0\r
824 //\r
825 if ((Temp->Parent != NULL) && (Temp->BusNumber == 0)) {\r
826 return FALSE;\r
827 }\r
828\r
829 //\r
830 // Skip VGA\r
831 //\r
832 if (IS_PCI_VGA (&Temp->Pci)) {\r
833 return FALSE;\r
834 }\r
835\r
836 return TRUE;\r
837}\r
838\r
839/**\r
840 Compare two resource nodes and get the larger resource consumer.\r
841\r
842 @param PciResNode1 resource node 1 want to be compared\r
843 @param PciResNode2 resource node 2 want to be compared\r
844\r
845 @return Larger resource node.\r
846\r
847**/\r
848PCI_RESOURCE_NODE *\r
849GetLargerConsumerDevice (\r
850 IN PCI_RESOURCE_NODE *PciResNode1,\r
851 IN PCI_RESOURCE_NODE *PciResNode2\r
852 )\r
853{\r
854 if (PciResNode2 == NULL) {\r
855 return PciResNode1;\r
856 }\r
857\r
858 if ((IS_PCI_BRIDGE(&(PciResNode2->PciDev->Pci)) || (PciResNode2->PciDev->Parent == NULL)) \\r
859 && (PciResNode2->ResourceUsage != PciResUsagePadding) )\r
860 {\r
861 return PciResNode1;\r
862 }\r
863\r
864 if (PciResNode1 == NULL) {\r
865 return PciResNode2;\r
866 }\r
867\r
868 if ((PciResNode1->Length) > (PciResNode2->Length)) {\r
869 return PciResNode1;\r
870 }\r
871\r
872 return PciResNode2;\r
873}\r
874\r
875\r
876/**\r
877 Get the max resource consumer in the host resource pool.\r
878\r
879 @param ResPool Pointer to resource pool node.\r
880\r
881 @return The max resource consumer in the host resource pool.\r
882\r
883**/\r
884PCI_RESOURCE_NODE *\r
885GetMaxResourceConsumerDevice (\r
886 IN PCI_RESOURCE_NODE *ResPool\r
887 )\r
888{\r
889 PCI_RESOURCE_NODE *Temp;\r
890 LIST_ENTRY *CurrentLink;\r
891 PCI_RESOURCE_NODE *PciResNode;\r
892 PCI_RESOURCE_NODE *PPBResNode;\r
893\r
894 PciResNode = NULL;\r
895\r
896 CurrentLink = ResPool->ChildList.ForwardLink;\r
897 while (CurrentLink != NULL && CurrentLink != &ResPool->ChildList) {\r
898\r
899 Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
900\r
901 if (!IsRejectiveDevice (Temp)) {\r
902 CurrentLink = CurrentLink->ForwardLink;\r
903 continue;\r
904 }\r
905\r
906 if ((IS_PCI_BRIDGE (&(Temp->PciDev->Pci)) || (Temp->PciDev->Parent == NULL)) \\r
907 && (Temp->ResourceUsage != PciResUsagePadding))\r
908 {\r
909 PPBResNode = GetMaxResourceConsumerDevice (Temp);\r
910 PciResNode = GetLargerConsumerDevice (PciResNode, PPBResNode);\r
911 } else {\r
912 PciResNode = GetLargerConsumerDevice (PciResNode, Temp);\r
913 }\r
914\r
915 CurrentLink = CurrentLink->ForwardLink;\r
916 }\r
917\r
918 return PciResNode;\r
919}\r
920\r
921/**\r
922 Adjust host bridge allocation so as to reduce resource requirement\r
923\r
924 @param IoPool Pointer to instance of I/O resource Node.\r
925 @param Mem32Pool Pointer to instance of 32-bit memory resource Node.\r
926 @param PMem32Pool Pointer to instance of 32-bit Prefetchable memory resource node.\r
927 @param Mem64Pool Pointer to instance of 64-bit memory resource node.\r
928 @param PMem64Pool Pointer to instance of 64-bit Prefetchable memory resource node.\r
929 @param IoResStatus Status of I/O resource Node.\r
930 @param Mem32ResStatus Status of 32-bit memory resource Node.\r
931 @param PMem32ResStatus Status of 32-bit Prefetchable memory resource node.\r
932 @param Mem64ResStatus Status of 64-bit memory resource node.\r
933 @param PMem64ResStatus Status of 64-bit Prefetchable memory resource node.\r
934\r
2048c585 935 @retval EFI_SUCCESS Successfully adjusted resource on host bridge.\r
9060e3ec 936 @retval EFI_ABORTED Host bridge hasn't this resource type or no resource be adjusted.\r
937\r
938**/\r
939EFI_STATUS\r
940PciHostBridgeAdjustAllocation (\r
941 IN PCI_RESOURCE_NODE *IoPool,\r
942 IN PCI_RESOURCE_NODE *Mem32Pool,\r
943 IN PCI_RESOURCE_NODE *PMem32Pool,\r
944 IN PCI_RESOURCE_NODE *Mem64Pool,\r
945 IN PCI_RESOURCE_NODE *PMem64Pool,\r
946 IN UINT64 IoResStatus,\r
947 IN UINT64 Mem32ResStatus,\r
948 IN UINT64 PMem32ResStatus,\r
949 IN UINT64 Mem64ResStatus,\r
950 IN UINT64 PMem64ResStatus\r
951 )\r
952{\r
953 BOOLEAN AllocationAjusted;\r
954 PCI_RESOURCE_NODE *PciResNode;\r
955 PCI_RESOURCE_NODE *ResPool[5];\r
956 PCI_IO_DEVICE *RemovedPciDev[5];\r
957 UINT64 ResStatus[5];\r
958 UINTN RemovedPciDevNum;\r
959 UINTN DevIndex;\r
960 UINTN ResType;\r
961 EFI_STATUS Status;\r
962 EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;\r
963\r
964 PciResNode = NULL;\r
965 ZeroMem (RemovedPciDev, 5 * sizeof (PCI_IO_DEVICE *));\r
966 RemovedPciDevNum = 0;\r
967\r
968 ResPool[0] = IoPool;\r
969 ResPool[1] = Mem32Pool;\r
970 ResPool[2] = PMem32Pool;\r
971 ResPool[3] = Mem64Pool;\r
972 ResPool[4] = PMem64Pool;\r
973\r
974 ResStatus[0] = IoResStatus;\r
975 ResStatus[1] = Mem32ResStatus;\r
976 ResStatus[2] = PMem32ResStatus;\r
977 ResStatus[3] = Mem64ResStatus;\r
978 ResStatus[4] = PMem64ResStatus;\r
979\r
980 AllocationAjusted = FALSE;\r
981\r
982 for (ResType = 0; ResType < 5; ResType++) {\r
983\r
984 if (ResStatus[ResType] == EFI_RESOURCE_SATISFIED) {\r
985 continue;\r
986 }\r
987\r
988 if (ResStatus[ResType] == EFI_RESOURCE_NOT_SATISFIED) {\r
989 //\r
990 // Host bridge hasn't this resource type\r
991 //\r
992 return EFI_ABORTED;\r
993 }\r
994\r
995 //\r
996 // Hostbridge hasn't enough resource\r
997 //\r
998 PciResNode = GetMaxResourceConsumerDevice (ResPool[ResType]);\r
999 if (PciResNode == NULL) {\r
1000 continue;\r
1001 }\r
1002\r
1003 //\r
1004 // Check if the device has been removed before\r
1005 //\r
1006 for (DevIndex = 0; DevIndex < RemovedPciDevNum; DevIndex++) {\r
1007 if (PciResNode->PciDev == RemovedPciDev[DevIndex]) {\r
1008 break;\r
1009 }\r
1010 }\r
1011\r
1012 if (DevIndex != RemovedPciDevNum) {\r
1013 continue;\r
1014 }\r
1015\r
1016 //\r
1017 // Remove the device if it isn't in the array\r
1018 //\r
1019 Status = RejectPciDevice (PciResNode->PciDev);\r
1020 if (Status == EFI_SUCCESS) {\r
724f26a9
RN		 1021 DEBUG ((\r
1022 EFI_D_ERROR,\r
1023 "PciBus: [%02x|%02x|%02x] was rejected due to resource confliction.\n",\r
1024 PciResNode->PciDev->BusNumber, PciResNode->PciDev->DeviceNumber, PciResNode->PciDev->FunctionNumber\r
1025 ));\r
9060e3ec 1026\r
1027 //\r
1028 // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code\r
1029 //\r
1030 //\r
1031 // Have no way to get ReqRes, AllocRes & Bar here\r
1032 //\r
1033 ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));\r
c9325700 1034 AllocFailExtendedData.DevicePathSize = (UINT16) sizeof (EFI_DEVICE_PATH_PROTOCOL);\r
9060e3ec 1035 AllocFailExtendedData.DevicePath = (UINT8 *) PciResNode->PciDev->DevicePath;\r
1036 AllocFailExtendedData.Bar = PciResNode->Bar;\r
1037\r
1038 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
1039 EFI_PROGRESS_CODE,\r
1040 EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,\r
1041 (VOID *) &AllocFailExtendedData,\r
1042 sizeof (AllocFailExtendedData)\r
1043 );\r
1044\r
1045 //\r
1046 // Add it to the array and indicate at least a device has been rejected\r
1047 //\r
1048 RemovedPciDev[RemovedPciDevNum++] = PciResNode->PciDev;\r
1049 AllocationAjusted = TRUE;\r
1050 }\r
1051 }\r
1052 //\r
1053 // End for\r
1054 //\r
1055\r
1056 if (AllocationAjusted) {\r
1057 return EFI_SUCCESS;\r
1058 } else {\r
1059 return EFI_ABORTED;\r
1060 }\r
1061}\r
1062\r
1063/**\r
2048c585 1064 Summary requests for all resource type, and construct ACPI resource\r
9060e3ec 1065 requestor instance.\r
1066\r
1067 @param Bridge detecting bridge\r
1068 @param IoNode Pointer to instance of I/O resource Node\r
1069 @param Mem32Node Pointer to instance of 32-bit memory resource Node\r
1070 @param PMem32Node Pointer to instance of 32-bit Pmemory resource node\r
1071 @param Mem64Node Pointer to instance of 64-bit memory resource node\r
1072 @param PMem64Node Pointer to instance of 64-bit Pmemory resource node\r
1073 @param Config Output buffer holding new constructed APCI resource requestor\r
1074\r
1075 @retval EFI_SUCCESS Successfully constructed ACPI resource.\r
2048c585 1076 @retval EFI_OUT_OF_RESOURCES No memory available.\r
9060e3ec 1077\r
1078**/\r
1079EFI_STATUS\r
1080ConstructAcpiResourceRequestor (\r
1081 IN PCI_IO_DEVICE *Bridge,\r
1082 IN PCI_RESOURCE_NODE *IoNode,\r
1083 IN PCI_RESOURCE_NODE *Mem32Node,\r
1084 IN PCI_RESOURCE_NODE *PMem32Node,\r
1085 IN PCI_RESOURCE_NODE *Mem64Node,\r
1086 IN PCI_RESOURCE_NODE *PMem64Node,\r
1087 OUT VOID **Config\r
1088 )\r
1089{\r
1090 UINT8 NumConfig;\r
1091 UINT8 Aperture;\r
1092 UINT8 *Configuration;\r
1093 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
1094 EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;\r
1095\r
1096 NumConfig = 0;\r
1097 Aperture = 0;\r
1098\r
1099 *Config = NULL;\r
1100\r
1101 //\r
1102 // if there is io request, add to the io aperture\r
1103 //\r
1104 if (ResourceRequestExisted (IoNode)) {\r
1105 NumConfig++;\r
1106 Aperture |= 0x01;\r
1107 }\r
1108\r
1109 //\r
1110 // if there is mem32 request, add to the mem32 aperture\r
1111 //\r
1112 if (ResourceRequestExisted (Mem32Node)) {\r
1113 NumConfig++;\r
1114 Aperture |= 0x02;\r
1115 }\r
1116\r
1117 //\r
1118 // if there is pmem32 request, add to the pmem32 aperture\r
1119 //\r
1120 if (ResourceRequestExisted (PMem32Node)) {\r
1121 NumConfig++;\r
1122 Aperture |= 0x04;\r
1123 }\r
1124\r
1125 //\r
1126 // if there is mem64 request, add to the mem64 aperture\r
1127 //\r
1128 if (ResourceRequestExisted (Mem64Node)) {\r
1129 NumConfig++;\r
1130 Aperture |= 0x08;\r
1131 }\r
1132\r
1133 //\r
1134 // if there is pmem64 request, add to the pmem64 aperture\r
1135 //\r
1136 if (ResourceRequestExisted (PMem64Node)) {\r
1137 NumConfig++;\r
1138 Aperture |= 0x10;\r
1139 }\r
1140\r
1141 if (NumConfig != 0) {\r
1142\r
1143 //\r
1144 // If there is at least one type of resource request,\r
1145 // allocate a acpi resource node\r
1146 //\r
1147 Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
1148 if (Configuration == NULL) {\r
1149 return EFI_OUT_OF_RESOURCES;\r
1150 }\r
1151\r
1152 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
1153\r
1154 //\r
1155 // Deal with io aperture\r
1156 //\r
1157 if ((Aperture & 0x01) != 0) {\r
1158 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
c9325700 1159 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1160 //\r
1161 // Io\r
1162 //\r
1163 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
1164 //\r
1165 // non ISA range\r
1166 //\r
1167 Ptr->SpecificFlag = 1;\r
1168 Ptr->AddrLen = IoNode->Length;\r
1169 Ptr->AddrRangeMax = IoNode->Alignment;\r
1170\r
1171 Ptr++;\r
1172 }\r
1173 //\r
1174 // Deal with mem32 aperture\r
1175 //\r
1176 if ((Aperture & 0x02) != 0) {\r
1177 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
cd7bfc2c 1178 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1179 //\r
1180 // Mem\r
1181 //\r
1182 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1183 //\r
1184 // Nonprefechable\r
1185 //\r
1186 Ptr->SpecificFlag = 0;\r
1187 //\r
1188 // 32 bit\r
1189 //\r
1190 Ptr->AddrSpaceGranularity = 32;\r
1191 Ptr->AddrLen = Mem32Node->Length;\r
1192 Ptr->AddrRangeMax = Mem32Node->Alignment;\r
1193\r
1194 Ptr++;\r
1195 }\r
1196\r
1197 //\r
1198 // Deal with Pmem32 aperture\r
1199 //\r
1200 if ((Aperture & 0x04) != 0) {\r
1201 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
cd7bfc2c 1202 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1203 //\r
1204 // Mem\r
1205 //\r
1206 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1207 //\r
1208 // prefechable\r
1209 //\r
1210 Ptr->SpecificFlag = 0x6;\r
1211 //\r
1212 // 32 bit\r
1213 //\r
1214 Ptr->AddrSpaceGranularity = 32;\r
1215 Ptr->AddrLen = PMem32Node->Length;\r
1216 Ptr->AddrRangeMax = PMem32Node->Alignment;\r
1217\r
1218 Ptr++;\r
1219 }\r
1220 //\r
1221 // Deal with mem64 aperture\r
1222 //\r
1223 if ((Aperture & 0x08) != 0) {\r
1224 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
cd7bfc2c 1225 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1226 //\r
1227 // Mem\r
1228 //\r
1229 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1230 //\r
1231 // nonprefechable\r
1232 //\r
1233 Ptr->SpecificFlag = 0;\r
1234 //\r
1235 // 64 bit\r
1236 //\r
1237 Ptr->AddrSpaceGranularity = 64;\r
1238 Ptr->AddrLen = Mem64Node->Length;\r
1239 Ptr->AddrRangeMax = Mem64Node->Alignment;\r
1240\r
1241 Ptr++;\r
1242 }\r
1243 //\r
1244 // Deal with Pmem64 aperture\r
1245 //\r
1246 if ((Aperture & 0x10) != 0) {\r
1247 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
cd7bfc2c 1248 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1249 //\r
1250 // Mem\r
1251 //\r
1252 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1253 //\r
1254 // prefechable\r
1255 //\r
1256 Ptr->SpecificFlag = 0x06;\r
1257 //\r
1258 // 64 bit\r
1259 //\r
1260 Ptr->AddrSpaceGranularity = 64;\r
1261 Ptr->AddrLen = PMem64Node->Length;\r
1262 Ptr->AddrRangeMax = PMem64Node->Alignment;\r
1263\r
1264 Ptr++;\r
1265 }\r
1266\r
1267 //\r
1268 // put the checksum\r
1269 //\r
1270 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) Ptr;\r
1271\r
1272 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
1273 PtrEnd->Checksum = 0;\r
1274\r
1275 } else {\r
1276\r
1277 //\r
1278 // If there is no resource request\r
1279 //\r
b59e2427 1280 Configuration = AllocateZeroPool (sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
9060e3ec 1281 if (Configuration == NULL) {\r
1282 return EFI_OUT_OF_RESOURCES;\r
1283 }\r
1284\r
b59e2427 1285 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Configuration);\r
9060e3ec 1286 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
1287 PtrEnd->Checksum = 0;\r
1288 }\r
1289\r
1290 *Config = Configuration;\r
1291\r
1292 return EFI_SUCCESS;\r
1293}\r
1294\r
1295/**\r
1296 Get resource base from an acpi configuration descriptor.\r
1297\r
1298 @param Config An acpi configuration descriptor.\r
1299 @param IoBase Output of I/O resource base address.\r
1300 @param Mem32Base Output of 32-bit memory base address.\r
1301 @param PMem32Base Output of 32-bit prefetchable memory base address.\r
1302 @param Mem64Base Output of 64-bit memory base address.\r
1303 @param PMem64Base Output of 64-bit prefetchable memory base address.\r
1304\r
1305**/\r
1306VOID\r
1307GetResourceBase (\r
1308 IN VOID *Config,\r
1309 OUT UINT64 *IoBase,\r
1310 OUT UINT64 *Mem32Base,\r
1311 OUT UINT64 *PMem32Base,\r
1312 OUT UINT64 *Mem64Base,\r
1313 OUT UINT64 *PMem64Base\r
1314 )\r
1315{\r
1316 UINT8 *Temp;\r
1317 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
1318 UINT64 ResStatus;\r
1319\r
1320 ASSERT (Config != NULL);\r
1321\r
1322 *IoBase = 0xFFFFFFFFFFFFFFFFULL;\r
1323 *Mem32Base = 0xFFFFFFFFFFFFFFFFULL;\r
1324 *PMem32Base = 0xFFFFFFFFFFFFFFFFULL;\r
1325 *Mem64Base = 0xFFFFFFFFFFFFFFFFULL;\r
1326 *PMem64Base = 0xFFFFFFFFFFFFFFFFULL;\r
1327\r
1328 Temp = (UINT8 *) Config;\r
1329\r
1330 while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
1331\r
1332 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
1333 ResStatus = Ptr->AddrTranslationOffset;\r
1334\r
1335 if (ResStatus == EFI_RESOURCE_SATISFIED) {\r
1336\r
1337 switch (Ptr->ResType) {\r
1338\r
1339 //\r
1340 // Memory type aperture\r
1341 //\r
1342 case 0:\r
1343\r
1344 //\r
1345 // Check to see the granularity\r
1346 //\r
1347 if (Ptr->AddrSpaceGranularity == 32) {\r
1348 if ((Ptr->SpecificFlag & 0x06) != 0) {\r
1349 *PMem32Base = Ptr->AddrRangeMin;\r
1350 } else {\r
1351 *Mem32Base = Ptr->AddrRangeMin;\r
1352 }\r
1353 }\r
1354\r
1355 if (Ptr->AddrSpaceGranularity == 64) {\r
1356 if ((Ptr->SpecificFlag & 0x06) != 0) {\r
1357 *PMem64Base = Ptr->AddrRangeMin;\r
1358 } else {\r
1359 *Mem64Base = Ptr->AddrRangeMin;\r
1360 }\r
1361 }\r
1362 break;\r
1363\r
1364 case 1:\r
1365\r
1366 //\r
1367 // Io type aperture\r
1368 //\r
1369 *IoBase = Ptr->AddrRangeMin;\r
1370 break;\r
1371\r
1372 default:\r
1373 break;\r
1374\r
1375 }\r
1376 //\r
1377 // End switch\r
1378 //\r
1379 }\r
1380 //\r
1381 // End for\r
1382 //\r
1383 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
1384 }\r
1385}\r
1386\r
1387/**\r
1388 Enumerate pci bridge, allocate resource and determine attribute\r
1389 for devices on this bridge.\r
1390\r
1391 @param BridgeDev Pointer to instance of bridge device.\r
1392\r
1393 @retval EFI_SUCCESS Successfully enumerated PCI bridge.\r
1394 @retval other Failed to enumerate.\r
1395\r
1396**/\r
1397EFI_STATUS\r
1398PciBridgeEnumerator (\r
1399 IN PCI_IO_DEVICE *BridgeDev\r
1400 )\r
1401{\r
1402 UINT8 SubBusNumber;\r
1403 UINT8 StartBusNumber;\r
1404 EFI_PCI_IO_PROTOCOL *PciIo;\r
1405 EFI_STATUS Status;\r
1406\r
1407 SubBusNumber = 0;\r
1408 StartBusNumber = 0;\r
1409 PciIo = &(BridgeDev->PciIo);\r
1410 Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);\r
1411\r
1412 if (EFI_ERROR (Status)) {\r
1413 return Status;\r
1414 }\r
1415\r
1416 Status = PciAssignBusNumber (\r
1417 BridgeDev,\r
1418 StartBusNumber,\r
1419 &SubBusNumber\r
1420 );\r
1421\r
1422 if (EFI_ERROR (Status)) {\r
1423 return Status;\r
1424 }\r
1425\r
1426 Status = PciPciDeviceInfoCollector (BridgeDev, StartBusNumber);\r
1427\r
1428 if (EFI_ERROR (Status)) {\r
1429 return Status;\r
1430 }\r
1431\r
1432 Status = PciBridgeResourceAllocator (BridgeDev);\r
1433\r
1434 if (EFI_ERROR (Status)) {\r
1435 return Status;\r
1436 }\r
1437\r
1438 Status = DetermineDeviceAttribute (BridgeDev);\r
1439\r
1440 if (EFI_ERROR (Status)) {\r
1441 return Status;\r
1442 }\r
1443\r
1444 return EFI_SUCCESS;\r
1445\r
1446}\r
1447\r
1448/**\r
1449 Allocate all kinds of resource for PCI bridge.\r
1450\r
1451 @param Bridge Pointer to bridge instance.\r
1452\r
1453 @retval EFI_SUCCESS Successfully allocated resource for PCI bridge.\r
1454 @retval other Failed to allocate resource for bridge.\r
1455\r
1456**/\r
1457EFI_STATUS\r
1458PciBridgeResourceAllocator (\r
1459 IN PCI_IO_DEVICE *Bridge\r
1460 )\r
1461{\r
1462 PCI_RESOURCE_NODE *IoBridge;\r
1463 PCI_RESOURCE_NODE *Mem32Bridge;\r
1464 PCI_RESOURCE_NODE *PMem32Bridge;\r
1465 PCI_RESOURCE_NODE *Mem64Bridge;\r
1466 PCI_RESOURCE_NODE *PMem64Bridge;\r
1467 UINT64 IoBase;\r
1468 UINT64 Mem32Base;\r
1469 UINT64 PMem32Base;\r
1470 UINT64 Mem64Base;\r
1471 UINT64 PMem64Base;\r
1472 EFI_STATUS Status;\r
1473\r
1474 IoBridge = CreateResourceNode (\r
1475 Bridge,\r
1476 0,\r
1ef26783 1477 Bridge->BridgeIoAlignment,\r
9060e3ec 1478 0,\r
1479 PciBarTypeIo16,\r
1480 PciResUsageTypical\r
1481 );\r
1482\r
1483 Mem32Bridge = CreateResourceNode (\r
1484 Bridge,\r
1485 0,\r
1486 0xFFFFF,\r
1487 0,\r
1488 PciBarTypeMem32,\r
1489 PciResUsageTypical\r
1490 );\r
1491\r
1492 PMem32Bridge = CreateResourceNode (\r
1493 Bridge,\r
1494 0,\r
1495 0xFFFFF,\r
1496 0,\r
1497 PciBarTypePMem32,\r
1498 PciResUsageTypical\r
1499 );\r
1500\r
1501 Mem64Bridge = CreateResourceNode (\r
1502 Bridge,\r
1503 0,\r
1504 0xFFFFF,\r
1505 0,\r
1506 PciBarTypeMem64,\r
1507 PciResUsageTypical\r
1508 );\r
1509\r
1510 PMem64Bridge = CreateResourceNode (\r
1511 Bridge,\r
1512 0,\r
1513 0xFFFFF,\r
1514 0,\r
1515 PciBarTypePMem64,\r
1516 PciResUsageTypical\r
1517 );\r
1518\r
1519 //\r
1520 // Create resourcemap by going through all the devices subject to this root bridge\r
1521 //\r
1522 CreateResourceMap (\r
1523 Bridge,\r
1524 IoBridge,\r
1525 Mem32Bridge,\r
1526 PMem32Bridge,\r
1527 Mem64Bridge,\r
1528 PMem64Bridge\r
1529 );\r
1530\r
1531 Status = GetResourceBaseFromBridge (\r
1532 Bridge,\r
1533 &IoBase,\r
1534 &Mem32Base,\r
1535 &PMem32Base,\r
1536 &Mem64Base,\r
1537 &PMem64Base\r
1538 );\r
1539\r
1540 if (EFI_ERROR (Status)) {\r
1541 return Status;\r
1542 }\r
1543\r
1544 //\r
1545 // Program IO resources\r
1546 //\r
1547 ProgramResource (\r
1548 IoBase,\r
1549 IoBridge\r
1550 );\r
1551\r
1552 //\r
1553 // Program Mem32 resources\r
1554 //\r
1555 ProgramResource (\r
1556 Mem32Base,\r
1557 Mem32Bridge\r
1558 );\r
1559\r
1560 //\r
1561 // Program PMem32 resources\r
1562 //\r
1563 ProgramResource (\r
1564 PMem32Base,\r
1565 PMem32Bridge\r
1566 );\r
1567\r
1568 //\r
1569 // Program Mem64 resources\r
1570 //\r
1571 ProgramResource (\r
1572 Mem64Base,\r
1573 Mem64Bridge\r
1574 );\r
1575\r
1576 //\r
1577 // Program PMem64 resources\r
1578 //\r
1579 ProgramResource (\r
1580 PMem64Base,\r
1581 PMem64Bridge\r
1582 );\r
1583\r
1584 DestroyResourceTree (IoBridge);\r
1585 DestroyResourceTree (Mem32Bridge);\r
1586 DestroyResourceTree (PMem32Bridge);\r
1587 DestroyResourceTree (PMem64Bridge);\r
1588 DestroyResourceTree (Mem64Bridge);\r
1589\r
1590 gBS->FreePool (IoBridge);\r
1591 gBS->FreePool (Mem32Bridge);\r
1592 gBS->FreePool (PMem32Bridge);\r
1593 gBS->FreePool (PMem64Bridge);\r
1594 gBS->FreePool (Mem64Bridge);\r
1595\r
1596 return EFI_SUCCESS;\r
1597}\r
1598\r
1599/**\r
1600 Get resource base address for a pci bridge device.\r
1601\r
1602 @param Bridge Given Pci driver instance.\r
1603 @param IoBase Output for base address of I/O type resource.\r
1604 @param Mem32Base Output for base address of 32-bit memory type resource.\r
1605 @param PMem32Base Ooutput for base address of 32-bit Pmemory type resource.\r
1606 @param Mem64Base Output for base address of 64-bit memory type resource.\r
1607 @param PMem64Base Output for base address of 64-bit Pmemory type resource.\r
1608\r
1609 @retval EFI_SUCCESS Successfully got resource base address.\r
1610 @retval EFI_OUT_OF_RESOURCES PCI bridge is not available.\r
1611\r
1612**/\r
1613EFI_STATUS\r
1614GetResourceBaseFromBridge (\r
1615 IN PCI_IO_DEVICE *Bridge,\r
1616 OUT UINT64 *IoBase,\r
1617 OUT UINT64 *Mem32Base,\r
1618 OUT UINT64 *PMem32Base,\r
1619 OUT UINT64 *Mem64Base,\r
1620 OUT UINT64 *PMem64Base\r
1621 )\r
1622{\r
1623 if (!Bridge->Allocated) {\r
1624 return EFI_OUT_OF_RESOURCES;\r
1625 }\r
1626\r
1627 *IoBase = gAllOne;\r
1628 *Mem32Base = gAllOne;\r
1629 *PMem32Base = gAllOne;\r
1630 *Mem64Base = gAllOne;\r
1631 *PMem64Base = gAllOne;\r
1632\r
1633 if (IS_PCI_BRIDGE (&Bridge->Pci)) {\r
1634\r
1635 if (Bridge->PciBar[PPB_IO_RANGE].Length > 0) {\r
1636 *IoBase = Bridge->PciBar[PPB_IO_RANGE].BaseAddress;\r
1637 }\r
1638\r
1639 if (Bridge->PciBar[PPB_MEM32_RANGE].Length > 0) {\r
1640 *Mem32Base = Bridge->PciBar[PPB_MEM32_RANGE].BaseAddress;\r
1641 }\r
1642\r
1643 if (Bridge->PciBar[PPB_PMEM32_RANGE].Length > 0) {\r
1644 *PMem32Base = Bridge->PciBar[PPB_PMEM32_RANGE].BaseAddress;\r
1645 }\r
1646\r
1647 if (Bridge->PciBar[PPB_PMEM64_RANGE].Length > 0) {\r
1648 *PMem64Base = Bridge->PciBar[PPB_PMEM64_RANGE].BaseAddress;\r
1649 } else {\r
1650 *PMem64Base = gAllOne;\r
1651 }\r
1652\r
1653 }\r
1654\r
1655 if (IS_CARDBUS_BRIDGE (&Bridge->Pci)) {\r
1656 if (Bridge->PciBar[P2C_IO_1].Length > 0) {\r
1657 *IoBase = Bridge->PciBar[P2C_IO_1].BaseAddress;\r
1658 } else {\r
1659 if (Bridge->PciBar[P2C_IO_2].Length > 0) {\r
1660 *IoBase = Bridge->PciBar[P2C_IO_2].BaseAddress;\r
1661 }\r
1662 }\r
1663\r
1664 if (Bridge->PciBar[P2C_MEM_1].Length > 0) {\r
1665 if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypePMem32) {\r
1666 *PMem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;\r
1667 }\r
1668\r
1669 if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypeMem32) {\r
1670 *Mem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;\r
1671 }\r
1672 }\r
1673\r
1674 if (Bridge->PciBar[P2C_MEM_2].Length > 0) {\r
1675 if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypePMem32) {\r
1676 *PMem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;\r
1677 }\r
1678\r
1679 if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypeMem32) {\r
1680 *Mem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;\r
1681 }\r
1682 }\r
1683 }\r
1684\r
1685 return EFI_SUCCESS;\r
1686}\r
1687\r
1688/**\r
1689 These are the notifications from the PCI bus driver that it is about to enter a certain\r
1690 phase of the PCI enumeration process.\r
1691\r
1692 This member function can be used to notify the host bridge driver to perform specific actions,\r
1693 including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r
1694 Eight notification points are defined at this time. See belows:\r
1695 EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data\r
1696 structures. The PCI enumerator should issue this notification\r
1697 before starting a fresh enumeration process. Enumeration cannot\r
1698 be restarted after sending any other notification such as\r
1699 EfiPciHostBridgeBeginBusAllocation.\r
1700 EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is\r
1701 required here. This notification can be used to perform any\r
1702 chipset-specific programming.\r
1703 EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No\r
1704 specific action is required here. This notification can be used to\r
1705 perform any chipset-specific programming.\r
1706 EfiPciHostBridgeBeginResourceAllocation\r
1707 The resource allocation phase is about to begin. No specific\r
1708 action is required here. This notification can be used to perform\r
1709 any chipset-specific programming.\r
1710 EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI\r
1711 root bridges. These resource settings are returned on the next call to\r
1712 GetProposedResources(). Before calling NotifyPhase() with a Phase of\r
1713 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r
1714 for gathering I/O and memory requests for\r
1715 all the PCI root bridges and submitting these requests using\r
1716 SubmitResources(). This function pads the resource amount\r
1717 to suit the root bridge hardware, takes care of dependencies between\r
1718 the PCI root bridges, and calls the Global Coherency Domain (GCD)\r
1719 with the allocation request. In the case of padding, the allocated range\r
1720 could be bigger than what was requested.\r
1721 EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated\r
1722 resources (proposed resources) for all the PCI root bridges. After the\r
1723 hardware is programmed, reassigning resources will not be supported.\r
1724 The bus settings are not affected.\r
1725 EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI\r
1726 root bridges and resets the I/O and memory apertures to their initial\r
1727 state. The bus settings are not affected. If the request to allocate\r
1728 resources fails, the PCI enumerator can use this notification to\r
1729 deallocate previous resources, adjust the requests, and retry\r
1730 allocation.\r
1731 EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is\r
1732 required here. This notification can be used to perform any chipsetspecific\r
1733 programming.\r
1734\r
1735 @param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
1736 @param[in] Phase The phase during enumeration\r
1737\r
1738 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r
1739 is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
1740 SubmitResources() has not been called for one or more\r
1741 PCI root bridges before this call\r
1742 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid\r
1743 for a Phase of EfiPciHostBridgeSetResources.\r
1744 @retval EFI_INVALID_PARAMETER Invalid phase parameter\r
1745 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
1746 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the\r
1747 previously submitted resource requests cannot be fulfilled or\r
1748 were only partially fulfilled.\r
1749 @retval EFI_SUCCESS The notification was accepted without any errors.\r
1750\r
1751**/\r
1752EFI_STATUS\r
1753NotifyPhase (\r
1754 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r
1755 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
1756 )\r
1757{\r
1758 EFI_HANDLE HostBridgeHandle;\r
1759 EFI_HANDLE RootBridgeHandle;\r
1760 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
1761 EFI_STATUS Status;\r
1762\r
1763 HostBridgeHandle = NULL;\r
1764 RootBridgeHandle = NULL;\r
1765 if (gPciPlatformProtocol != NULL) {\r
1766 //\r
1767 // Get Host Bridge Handle.\r
1768 //\r
1769 PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle);\r
1770\r
1771 //\r
1772 // Get the rootbridge Io protocol to find the host bridge handle\r
1773 //\r
1774 Status = gBS->HandleProtocol (\r
1775 RootBridgeHandle,\r
1776 &gEfiPciRootBridgeIoProtocolGuid,\r
1777 (VOID **) &PciRootBridgeIo\r
1778 );\r
1779\r
1780 if (EFI_ERROR (Status)) {\r
1781 return EFI_NOT_FOUND;\r
1782 }\r
1783\r
1784 HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
1785\r
1786 //\r
1787 // Call PlatformPci::PlatformNotify() if the protocol is present.\r
1788 //\r
1789 gPciPlatformProtocol->PlatformNotify (\r
1790 gPciPlatformProtocol,\r
1791 HostBridgeHandle,\r
1792 Phase,\r
1793 ChipsetEntry\r
1794 );\r
1795 } else if (gPciOverrideProtocol != NULL){\r
1796 //\r
1797 // Get Host Bridge Handle.\r
1798 //\r
1799 PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle);\r
1800\r
1801 //\r
1802 // Get the rootbridge Io protocol to find the host bridge handle\r
1803 //\r
1804 Status = gBS->HandleProtocol (\r
1805 RootBridgeHandle,\r
1806 &gEfiPciRootBridgeIoProtocolGuid,\r
1807 (VOID **) &PciRootBridgeIo\r
1808 );\r
1809\r
1810 if (EFI_ERROR (Status)) {\r
1811 return EFI_NOT_FOUND;\r
1812 }\r
1813\r
1814 HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
1815\r
1816 //\r
1817 // Call PlatformPci::PhaseNotify() if the protocol is present.\r
1818 //\r
1819 gPciOverrideProtocol->PlatformNotify (\r
1820 gPciOverrideProtocol,\r
1821 HostBridgeHandle,\r
1822 Phase,\r
1823 ChipsetEntry\r
1824 );\r
1825 } \r
1826\r
1827 Status = PciResAlloc->NotifyPhase (\r
1828 PciResAlloc,\r
1829 Phase\r
1830 );\r
1831\r
1832 if (gPciPlatformProtocol != NULL) {\r
1833 //\r
1834 // Call PlatformPci::PlatformNotify() if the protocol is present.\r
1835 //\r
1836 gPciPlatformProtocol->PlatformNotify (\r
1837 gPciPlatformProtocol,\r
1838 HostBridgeHandle,\r
1839 Phase,\r
1840 ChipsetExit\r
1841 );\r
1842\r
1843 } else if (gPciOverrideProtocol != NULL) {\r
1844 //\r
1845 // Call PlatformPci::PhaseNotify() if the protocol is present.\r
1846 //\r
1847 gPciOverrideProtocol->PlatformNotify (\r
1848 gPciOverrideProtocol,\r
1849 HostBridgeHandle,\r
1850 Phase,\r
1851 ChipsetExit\r
1852 );\r
1853 }\r
1854\r
724f26a9 1855 return Status;\r
9060e3ec 1856}\r
1857\r
1858/**\r
1859 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
1860 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
1861 PCI controllers before enumeration.\r
1862\r
1863 This function is called during the PCI enumeration process. No specific action is expected from this\r
1864 member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
1865 enumeration.\r
1866\r
1867 @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
1868 @param Bus The bus number of the pci device.\r
1869 @param Device The device number of the pci device.\r
1870 @param Func The function number of the pci device.\r
1871 @param Phase The phase of the PCI device enumeration.\r
1872\r
1873 @retval EFI_SUCCESS The requested parameters were returned.\r
1874 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
1875 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
1876 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
1877 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
1878 not enumerate this device, including its child devices if it is a PCI-to-PCI\r
1879 bridge.\r
1880\r
1881**/\r
1882EFI_STATUS\r
1883PreprocessController (\r
1884 IN PCI_IO_DEVICE *Bridge,\r
1885 IN UINT8 Bus,\r
1886 IN UINT8 Device,\r
1887 IN UINT8 Func,\r
1888 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
1889 )\r
1890{\r
1891 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS RootBridgePciAddress;\r
1892 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc;\r
1893 EFI_HANDLE RootBridgeHandle;\r
1894 EFI_HANDLE HostBridgeHandle;\r
1895 EFI_STATUS Status;\r
1896\r
1897 //\r
1898 // Get the host bridge handle\r
1899 //\r
1900 HostBridgeHandle = Bridge->PciRootBridgeIo->ParentHandle;\r
1901\r
1902 //\r
1903 // Get the pci host bridge resource allocation protocol\r
1904 //\r
1905 Status = gBS->OpenProtocol (\r
1906 HostBridgeHandle,\r
1907 &gEfiPciHostBridgeResourceAllocationProtocolGuid,\r
1908 (VOID **) &PciResAlloc,\r
1909 NULL,\r
1910 NULL,\r
1911 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
1912 );\r
1913\r
1914 if (EFI_ERROR (Status)) {\r
1915 return EFI_UNSUPPORTED;\r
1916 }\r
1917\r
1918 //\r
1919 // Get Root Brige Handle\r
1920 //\r
1921 while (Bridge->Parent != NULL) {\r
1922 Bridge = Bridge->Parent;\r
1923 }\r
1924\r
1925 RootBridgeHandle = Bridge->Handle;\r
1926\r
1927 RootBridgePciAddress.Register = 0;\r
1928 RootBridgePciAddress.Function = Func;\r
1929 RootBridgePciAddress.Device = Device;\r
1930 RootBridgePciAddress.Bus = Bus;\r
1931 RootBridgePciAddress.ExtendedRegister = 0;\r
1932\r
1933 if (gPciPlatformProtocol != NULL) {\r
1934 //\r
1935 // Call PlatformPci::PrepController() if the protocol is present.\r
1936 //\r
1937 gPciPlatformProtocol->PlatformPrepController (\r
1938 gPciPlatformProtocol,\r
1939 HostBridgeHandle,\r
1940 RootBridgeHandle,\r
1941 RootBridgePciAddress,\r
1942 Phase,\r
1943 ChipsetEntry\r
1944 );\r
1945 } else if (gPciOverrideProtocol != NULL) {\r
1946 //\r
1947 // Call PlatformPci::PrepController() if the protocol is present.\r
1948 //\r
1949 gPciOverrideProtocol->PlatformPrepController (\r
1950 gPciOverrideProtocol,\r
1951 HostBridgeHandle,\r
1952 RootBridgeHandle,\r
1953 RootBridgePciAddress,\r
1954 Phase,\r
1955 ChipsetEntry\r
1956 );\r
1957 }\r
1958\r
1959 Status = PciResAlloc->PreprocessController (\r
1960 PciResAlloc,\r
1961 RootBridgeHandle,\r
1962 RootBridgePciAddress,\r
1963 Phase\r
1964 );\r
1965\r
1966 if (gPciPlatformProtocol != NULL) {\r
1967 //\r
1968 // Call PlatformPci::PrepController() if the protocol is present.\r
1969 //\r
1970 gPciPlatformProtocol->PlatformPrepController (\r
1971 gPciPlatformProtocol,\r
1972 HostBridgeHandle,\r
1973 RootBridgeHandle,\r
1974 RootBridgePciAddress,\r
1975 Phase,\r
1976 ChipsetExit\r
1977 );\r
1978 } else if (gPciOverrideProtocol != NULL) {\r
1979 //\r
1980 // Call PlatformPci::PrepController() if the protocol is present.\r
1981 //\r
1982 gPciOverrideProtocol->PlatformPrepController (\r
1983 gPciOverrideProtocol,\r
1984 HostBridgeHandle,\r
1985 RootBridgeHandle,\r
1986 RootBridgePciAddress,\r
1987 Phase,\r
1988 ChipsetExit\r
1989 );\r
1990 }\r
1991\r
1992 return EFI_SUCCESS;\r
1993}\r
1994\r
1995/**\r
1996 This function allows the PCI bus driver to be notified to act as requested when a hot-plug event has\r
1997 happened on the hot-plug controller. Currently, the operations include add operation and remove operation..\r
1998\r
1999 @param This A pointer to the hot plug request protocol.\r
2000 @param Operation The operation the PCI bus driver is requested to make.\r
2001 @param Controller The handle of the hot-plug controller.\r
2002 @param RemainingDevicePath The remaining device path for the PCI-like hot-plug device.\r
2003 @param NumberOfChildren The number of child handles.\r
2004 For a add operation, it is an output parameter.\r
2005 For a remove operation, it's an input parameter.\r
2006 @param ChildHandleBuffer The buffer which contains the child handles.\r
2007\r
2008 @retval EFI_INVALID_PARAMETER Operation is not a legal value.\r
2009 Controller is NULL or not a valid handle.\r
2010 NumberOfChildren is NULL.\r
2011 ChildHandleBuffer is NULL while Operation is add.\r
2012 @retval EFI_OUT_OF_RESOURCES There are no enough resources to start the devices.\r
2013 @retval EFI_NOT_FOUND Can not find bridge according to controller handle.\r
2014 @retval EFI_SUCCESS The handles for the specified device have been created or destroyed\r
2015 as requested, and for an add operation, the new handles are\r
2016 returned in ChildHandleBuffer.\r
2017**/\r
2018EFI_STATUS\r
2019EFIAPI\r
2020PciHotPlugRequestNotify (\r
2021 IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL * This,\r
2022 IN EFI_PCI_HOTPLUG_OPERATION Operation,\r
2023 IN EFI_HANDLE Controller,\r
2024 IN EFI_DEVICE_PATH_PROTOCOL * RemainingDevicePath OPTIONAL,\r
2025 IN OUT UINT8 *NumberOfChildren,\r
2026 IN OUT EFI_HANDLE * ChildHandleBuffer\r
2027 )\r
2028{\r
2029 PCI_IO_DEVICE *Bridge;\r
2030 PCI_IO_DEVICE *Temp;\r
2031 EFI_PCI_IO_PROTOCOL *PciIo;\r
2032 UINTN Index;\r
2033 EFI_HANDLE RootBridgeHandle;\r
2034 EFI_STATUS Status;\r
2035\r
2036 //\r
2037 // Check input parameter validity\r
2038 //\r
2039 if ((Controller == NULL) || (NumberOfChildren == NULL)){\r
2040 return EFI_INVALID_PARAMETER;\r
2041 }\r
2042\r
2043 if ((Operation != EfiPciHotPlugRequestAdd) && (Operation != EfiPciHotplugRequestRemove)) {\r
2044 return EFI_INVALID_PARAMETER;\r
2045 }\r
2046\r
2047 if (Operation == EfiPciHotPlugRequestAdd){\r
2048 if (ChildHandleBuffer == NULL) {\r
2049 return EFI_INVALID_PARAMETER;\r
2050 }\r
2051 } else if ((Operation == EfiPciHotplugRequestRemove) && (*NumberOfChildren != 0)) {\r
2052 if (ChildHandleBuffer == NULL) {\r
2053 return EFI_INVALID_PARAMETER;\r
2054 }\r
2055 }\r
2056 \r
2057 Status = gBS->OpenProtocol (\r
2058 Controller,\r
2059 &gEfiPciIoProtocolGuid,\r
2060 (VOID **) &PciIo,\r
2061 gPciBusDriverBinding.DriverBindingHandle,\r
2062 Controller,\r
2063 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
2064 );\r
2065\r
2066 if (EFI_ERROR (Status)) {\r
2067 return EFI_NOT_FOUND;\r
2068 }\r
2069\r
2070 Bridge = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);\r
2071\r
2072 //\r
2073 // Get root bridge handle\r
2074 //\r
2075 Temp = Bridge;\r
2076 while (Temp->Parent != NULL) {\r
2077 Temp = Temp->Parent;\r
2078 }\r
2079\r
2080 RootBridgeHandle = Temp->Handle;\r
2081\r
2082 if (Operation == EfiPciHotPlugRequestAdd) {\r
37623a5c 2083 //\r
2084 // Report Status Code to indicate hot plug happens\r
2085 //\r
2086 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
2087 EFI_PROGRESS_CODE,\r
2088 (EFI_IO_BUS_PCI | EFI_IOB_PC_HOTPLUG),\r
2089 Temp->DevicePath\r
2090 );\r
9060e3ec 2091\r
2092 if (NumberOfChildren != NULL) {\r
2093 *NumberOfChildren = 0;\r
2094 }\r
2095\r
2096 if (IsListEmpty (&Bridge->ChildList)) {\r
2097\r
2098 Status = PciBridgeEnumerator (Bridge);\r
2099\r
2100 if (EFI_ERROR (Status)) {\r
2101 return Status;\r
2102 }\r
2103 }\r
2104\r
2105 Status = StartPciDevicesOnBridge (\r
2106 RootBridgeHandle,\r
2107 Bridge,\r
2108 RemainingDevicePath,\r
2109 NumberOfChildren,\r
2110 ChildHandleBuffer\r
2111 );\r
2112\r
2113 return Status;\r
2114 }\r
2115\r
2116 if (Operation == EfiPciHotplugRequestRemove) {\r
2117\r
2118 if (*NumberOfChildren == 0) {\r
2119 //\r
2120 // Remove all devices on the bridge\r
2121 //\r
2122 RemoveAllPciDeviceOnBridge (RootBridgeHandle, Bridge);\r
2123 return EFI_SUCCESS;\r
2124\r
2125 }\r
2126\r
2127 for (Index = 0; Index < *NumberOfChildren; Index++) {\r
2128 //\r
2129 // De register all the pci device\r
2130 //\r
2131 Status = DeRegisterPciDevice (RootBridgeHandle, ChildHandleBuffer[Index]);\r
2132\r
2133 if (EFI_ERROR (Status)) {\r
2134 return Status;\r
2135 }\r
2136\r
2137 }\r
2138 //\r
2139 // End for\r
2140 //\r
2141 return EFI_SUCCESS;\r
2142 }\r
2143\r
2144 return EFI_SUCCESS;\r
2145}\r
2146\r
2147/**\r
2148 Search hostbridge according to given handle\r
2149\r
2150 @param RootBridgeHandle Host bridge handle.\r
2151\r
2152 @retval TRUE Found host bridge handle.\r
2153 @retval FALSE Not found hot bridge handle.\r
2154\r
2155**/\r
2156BOOLEAN\r
2157SearchHostBridgeHandle (\r
2158 IN EFI_HANDLE RootBridgeHandle\r
2159 )\r
2160{\r
2161 EFI_HANDLE HostBridgeHandle;\r
2162 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
2163 UINTN Index;\r
2164 EFI_STATUS Status;\r
2165\r
2166 //\r
2167 // Get the rootbridge Io protocol to find the host bridge handle\r
2168 //\r
2169 Status = gBS->OpenProtocol (\r
2170 RootBridgeHandle,\r
2171 &gEfiPciRootBridgeIoProtocolGuid,\r
2172 (VOID **) &PciRootBridgeIo,\r
2173 gPciBusDriverBinding.DriverBindingHandle,\r
2174 RootBridgeHandle,\r
2175 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
2176 );\r
2177\r
2178 if (EFI_ERROR (Status)) {\r
2179 return FALSE;\r
2180 }\r
2181\r
2182 HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
2183 for (Index = 0; Index < gPciHostBridgeNumber; Index++) {\r
2184 if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {\r
2185 return TRUE;\r
2186 }\r
2187 }\r
2188\r
2189 return FALSE;\r
2190}\r
2191\r
2192/**\r
2193 Add host bridge handle to global variable for enumerating.\r
2194\r
2195 @param HostBridgeHandle Host bridge handle.\r
2196\r
2197 @retval EFI_SUCCESS Successfully added host bridge.\r
2198 @retval EFI_ABORTED Host bridge is NULL, or given host bridge\r
2199 has been in host bridge list.\r
2200\r
2201**/\r
2202EFI_STATUS\r
2203AddHostBridgeEnumerator (\r
2204 IN EFI_HANDLE HostBridgeHandle\r
2205 )\r
2206{\r
2207 UINTN Index;\r
2208\r
2209 if (HostBridgeHandle == NULL) {\r
2210 return EFI_ABORTED;\r
2211 }\r
2212\r
2213 for (Index = 0; Index < gPciHostBridgeNumber; Index++) {\r
2214 if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {\r
2215 return EFI_ABORTED;\r
2216 }\r
2217 }\r
2218\r
2219 if (Index < PCI_MAX_HOST_BRIDGE_NUM) {\r
2220 gPciHostBrigeHandles[Index] = HostBridgeHandle;\r
2221 gPciHostBridgeNumber++;\r
2222 }\r
2223\r
2224 return EFI_SUCCESS;\r
2225}\r
2226\r
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