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Add missing status code in several modules.
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciEnumerator.c
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9060e3ec 1/** @file\r
2 PCI eunmeration implementation on entire PCI bus system for PCI Bus module.\r
3\r
fe91c992 4Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
cd5ebaa0 5This program and the accompanying materials\r
9060e3ec 6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include "PciBus.h"\r
16\r
17/**\r
18 This routine is used to enumerate entire pci bus system\r
19 in a given platform.\r
20\r
21 @param Controller Parent controller handle.\r
22\r
23 @retval EFI_SUCCESS PCI enumeration finished successfully.\r
24 @retval other Some error occurred when enumerating the pci bus system.\r
25\r
26**/\r
27EFI_STATUS\r
28PciEnumerator (\r
29 IN EFI_HANDLE Controller\r
30 )\r
31{\r
32 EFI_HANDLE Handle;\r
33 EFI_HANDLE HostBridgeHandle;\r
34 EFI_STATUS Status;\r
35 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc;\r
36 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
37\r
38 //\r
39 // If PCI bus has already done the full enumeration, never do it again\r
40 //\r
41 if (!gFullEnumeration) {\r
42 return PciEnumeratorLight (Controller);\r
43 }\r
44\r
45 //\r
46 // Get the rootbridge Io protocol to find the host bridge handle\r
47 //\r
48 Status = gBS->OpenProtocol (\r
49 Controller,\r
50 &gEfiPciRootBridgeIoProtocolGuid,\r
51 (VOID **) &PciRootBridgeIo,\r
52 gPciBusDriverBinding.DriverBindingHandle,\r
53 Controller,\r
54 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
55 );\r
56\r
57 if (EFI_ERROR (Status)) {\r
58 return Status;\r
59 }\r
60\r
61 //\r
62 // Get the host bridge handle\r
63 //\r
64 HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
65\r
66 //\r
67 // Get the pci host bridge resource allocation protocol\r
68 //\r
69 Status = gBS->OpenProtocol (\r
70 HostBridgeHandle,\r
71 &gEfiPciHostBridgeResourceAllocationProtocolGuid,\r
72 (VOID **) &PciResAlloc,\r
73 gPciBusDriverBinding.DriverBindingHandle,\r
74 Controller,\r
75 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
76 );\r
77\r
78 if (EFI_ERROR (Status)) {\r
79 return Status;\r
80 }\r
81\r
82 //\r
83 // Notify the pci bus enumeration is about to begin\r
84 //\r
85 NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginEnumeration);\r
86\r
87 //\r
88 // Start the bus allocation phase\r
89 //\r
90 Status = PciHostBridgeEnumerator (PciResAlloc);\r
91\r
92 if (EFI_ERROR (Status)) {\r
93 return Status;\r
94 }\r
95\r
96 //\r
97 // Submit the resource request\r
98 //\r
99 Status = PciHostBridgeResourceAllocator (PciResAlloc);\r
100\r
101 if (EFI_ERROR (Status)) {\r
102 return Status;\r
103 }\r
104\r
105 //\r
106 // Notify the pci bus enumeration is about to complete\r
107 //\r
108 NotifyPhase (PciResAlloc, EfiPciHostBridgeEndEnumeration);\r
109\r
110 //\r
111 // Process P2C\r
112 //\r
113 Status = PciHostBridgeP2CProcess (PciResAlloc);\r
114\r
115 if (EFI_ERROR (Status)) {\r
116 return Status;\r
117 }\r
118\r
119 //\r
120 // Process attributes for devices on this host bridge\r
121 //\r
122 Status = PciHostBridgeDeviceAttribute (PciResAlloc);\r
123 if (EFI_ERROR (Status)) {\r
124 return Status;\r
125 }\r
126\r
127 gFullEnumeration = FALSE;\r
128\r
0ce94f38 129 Handle = NULL;\r
9060e3ec 130 Status = gBS->InstallProtocolInterface (\r
131 &Handle,\r
132 &gEfiPciEnumerationCompleteProtocolGuid,\r
133 EFI_NATIVE_INTERFACE,\r
134 NULL\r
135 );\r
136 if (EFI_ERROR (Status)) {\r
137 return Status;\r
138 }\r
139\r
140 return EFI_SUCCESS;\r
141}\r
142\r
143/**\r
144 Enumerate PCI root bridge.\r
145\r
146 @param PciResAlloc Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
147 @param RootBridgeDev Instance of root bridge device.\r
148\r
149 @retval EFI_SUCCESS Successfully enumerated root bridge.\r
150 @retval other Failed to enumerate root bridge.\r
151\r
152**/\r
153EFI_STATUS\r
154PciRootBridgeEnumerator (\r
155 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r
156 IN PCI_IO_DEVICE *RootBridgeDev\r
157 )\r
158{\r
159 EFI_STATUS Status;\r
160 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
306bbe82 161 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration1;\r
162 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration2;\r
163 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration3;\r
9060e3ec 164 UINT8 SubBusNumber;\r
165 UINT8 StartBusNumber;\r
166 UINT8 PaddedBusRange;\r
167 EFI_HANDLE RootBridgeHandle;\r
306bbe82 168 UINT8 Desc;\r
169 UINT64 AddrLen;\r
170 UINT64 AddrRangeMin;\r
9060e3ec 171\r
172 SubBusNumber = 0;\r
173 StartBusNumber = 0;\r
174 PaddedBusRange = 0;\r
175\r
176 //\r
177 // Get the root bridge handle\r
178 //\r
179 RootBridgeHandle = RootBridgeDev->Handle;\r
180\r
181 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
182 EFI_PROGRESS_CODE,\r
fe91c992 183 EFI_IO_BUS_PCI | EFI_IOB_PCI_BUS_ENUM,\r
9060e3ec 184 RootBridgeDev->DevicePath\r
185 );\r
186\r
187 //\r
188 // Get the Bus information\r
189 //\r
190 Status = PciResAlloc->StartBusEnumeration (\r
191 PciResAlloc,\r
192 RootBridgeHandle,\r
193 (VOID **) &Configuration\r
194 );\r
195\r
196 if (EFI_ERROR (Status)) {\r
197 return Status;\r
198 }\r
199\r
306bbe82 200 if (Configuration == NULL || Configuration->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
201 return EFI_INVALID_PARAMETER;\r
202 }\r
203 RootBridgeDev->BusNumberRanges = Configuration;\r
204\r
205 //\r
206 // Sort the descriptors in ascending order\r
207 //\r
208 for (Configuration1 = Configuration; Configuration1->Desc != ACPI_END_TAG_DESCRIPTOR; Configuration1++) {\r
209 Configuration2 = Configuration1;\r
210 for (Configuration3 = Configuration1 + 1; Configuration3->Desc != ACPI_END_TAG_DESCRIPTOR; Configuration3++) {\r
211 if (Configuration2->AddrRangeMin > Configuration3->AddrRangeMin) {\r
212 Configuration2 = Configuration3;\r
213 }\r
214 }\r
215 //\r
216 // All other fields other than AddrRangeMin and AddrLen are ignored in a descriptor,\r
217 // so only need to swap these two fields.\r
218 //\r
219 if (Configuration2 != Configuration1) {\r
220 AddrRangeMin = Configuration1->AddrRangeMin;\r
221 Configuration1->AddrRangeMin = Configuration2->AddrRangeMin;\r
222 Configuration2->AddrRangeMin = AddrRangeMin;\r
223 \r
224 AddrLen = Configuration1->AddrLen;\r
225 Configuration1->AddrLen = Configuration2->AddrLen;\r
226 Configuration2->AddrLen = AddrLen;\r
227 }\r
228 }\r
229\r
9060e3ec 230 //\r
231 // Get the bus number to start with\r
232 //\r
233 StartBusNumber = (UINT8) (Configuration->AddrRangeMin);\r
9060e3ec 234\r
235 //\r
236 // Initialize the subordinate bus number\r
237 //\r
238 SubBusNumber = StartBusNumber;\r
239\r
240 //\r
241 // Reset all assigned PCI bus number\r
242 //\r
243 ResetAllPpbBusNumber (\r
244 RootBridgeDev,\r
245 StartBusNumber\r
246 );\r
247\r
248 //\r
249 // Assign bus number\r
250 //\r
251 Status = PciScanBus (\r
252 RootBridgeDev,\r
306bbe82 253 StartBusNumber,\r
9060e3ec 254 &SubBusNumber,\r
255 &PaddedBusRange\r
256 );\r
257\r
258 if (EFI_ERROR (Status)) {\r
259 return Status;\r
260 }\r
261\r
262\r
263 //\r
264 // Assign max bus number scanned\r
265 //\r
9060e3ec 266\r
306bbe82 267 Status = PciAllocateBusNumber (RootBridgeDev, SubBusNumber, PaddedBusRange, &SubBusNumber);\r
268 if (EFI_ERROR (Status)) {\r
269 return Status;\r
270 } \r
271\r
272 //\r
273 // Find the bus range which contains the higest bus number, then returns the number of buses\r
274 // that should be decoded.\r
275 //\r
276 while (Configuration->AddrRangeMin + Configuration->AddrLen - 1 < SubBusNumber) {\r
277 Configuration++;\r
278 }\r
279 AddrLen = Configuration->AddrLen;\r
280 Configuration->AddrLen = SubBusNumber - Configuration->AddrRangeMin + 1;\r
281\r
282 //\r
283 // Save the Desc field of the next descriptor. Mark the next descriptor as an END descriptor.\r
284 //\r
285 Configuration++;\r
286 Desc = Configuration->Desc;\r
287 Configuration->Desc = ACPI_END_TAG_DESCRIPTOR;\r
288 \r
9060e3ec 289 //\r
290 // Set bus number\r
291 //\r
292 Status = PciResAlloc->SetBusNumbers (\r
293 PciResAlloc,\r
294 RootBridgeHandle,\r
306bbe82 295 RootBridgeDev->BusNumberRanges\r
9060e3ec 296 );\r
297\r
306bbe82 298 //\r
299 // Restore changed fields\r
300 //\r
301 Configuration->Desc = Desc;\r
302 (Configuration - 1)->AddrLen = AddrLen;\r
303 \r
304 return Status;\r
9060e3ec 305}\r
306\r
307/**\r
308 This routine is used to process all PCI devices' Option Rom\r
309 on a certain root bridge.\r
310\r
311 @param Bridge Given parent's root bridge.\r
312 @param RomBase Base address of ROM driver loaded from.\r
313 @param MaxLength Maximum rom size.\r
314\r
315**/\r
316VOID\r
317ProcessOptionRom (\r
318 IN PCI_IO_DEVICE *Bridge,\r
319 IN UINT64 RomBase,\r
320 IN UINT64 MaxLength\r
321 )\r
322{\r
323 LIST_ENTRY *CurrentLink;\r
324 PCI_IO_DEVICE *Temp;\r
325\r
326 //\r
327 // Go through bridges to reach all devices\r
328 //\r
329 CurrentLink = Bridge->ChildList.ForwardLink;\r
330 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
331 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
332 if (!IsListEmpty (&Temp->ChildList)) {\r
333\r
334 //\r
335 // Go further to process the option rom under this bridge\r
336 //\r
337 ProcessOptionRom (Temp, RomBase, MaxLength);\r
338 }\r
339\r
340 if (Temp->RomSize != 0 && Temp->RomSize <= MaxLength) {\r
341\r
342 //\r
343 // Load and process the option rom\r
344 //\r
345 LoadOpRomImage (Temp, RomBase);\r
346 }\r
347\r
348 CurrentLink = CurrentLink->ForwardLink;\r
349 }\r
350}\r
351\r
352/**\r
353 This routine is used to assign bus number to the given PCI bus system\r
354\r
355 @param Bridge Parent root bridge instance.\r
356 @param StartBusNumber Number of beginning.\r
357 @param SubBusNumber The number of sub bus.\r
358\r
359 @retval EFI_SUCCESS Successfully assigned bus number.\r
360 @retval EFI_DEVICE_ERROR Failed to assign bus number.\r
361\r
362**/\r
363EFI_STATUS\r
364PciAssignBusNumber (\r
365 IN PCI_IO_DEVICE *Bridge,\r
366 IN UINT8 StartBusNumber,\r
367 OUT UINT8 *SubBusNumber\r
368 )\r
369{\r
370 EFI_STATUS Status;\r
371 PCI_TYPE00 Pci;\r
372 UINT8 Device;\r
373 UINT8 Func;\r
374 UINT64 Address;\r
375 UINTN SecondBus;\r
376 UINT16 Register;\r
377 UINT8 Register8;\r
378 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
379\r
380 PciRootBridgeIo = Bridge->PciRootBridgeIo;\r
381\r
382 SecondBus = 0;\r
383 Register = 0;\r
384\r
385 *SubBusNumber = StartBusNumber;\r
386\r
387 //\r
388 // First check to see whether the parent is ppb\r
389 //\r
390 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
391 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
392\r
393 //\r
394 // Check to see whether a pci device is present\r
395 //\r
396 Status = PciDevicePresent (\r
397 PciRootBridgeIo,\r
398 &Pci,\r
399 StartBusNumber,\r
400 Device,\r
401 Func\r
402 );\r
403\r
404 if (!EFI_ERROR (Status) &&\r
405 (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {\r
406\r
407 //\r
408 // Reserved one bus for cardbus bridge\r
409 //\r
306bbe82 410 Status = PciAllocateBusNumber (Bridge, *SubBusNumber, 1, SubBusNumber);\r
411 if (EFI_ERROR (Status)) {\r
412 return Status;\r
413 }\r
414 SecondBus = *SubBusNumber;\r
9060e3ec 415\r
416 Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);\r
417\r
418 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
419\r
420 Status = PciRootBridgeIo->Pci.Write (\r
421 PciRootBridgeIo,\r
422 EfiPciWidthUint16,\r
423 Address,\r
424 1,\r
425 &Register\r
426 );\r
427\r
428 //\r
429 // Initialize SubBusNumber to SecondBus\r
430 //\r
431 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
432 Status = PciRootBridgeIo->Pci.Write (\r
433 PciRootBridgeIo,\r
434 EfiPciWidthUint8,\r
435 Address,\r
436 1,\r
437 SubBusNumber\r
438 );\r
439 //\r
440 // If it is PPB, resursively search down this bridge\r
441 //\r
442 if (IS_PCI_BRIDGE (&Pci)) {\r
443\r
444 Register8 = 0xFF;\r
445 Status = PciRootBridgeIo->Pci.Write (\r
446 PciRootBridgeIo,\r
447 EfiPciWidthUint8,\r
448 Address,\r
449 1,\r
450 &Register8\r
451 );\r
452\r
453 Status = PciAssignBusNumber (\r
454 Bridge,\r
455 (UINT8) (SecondBus),\r
456 SubBusNumber\r
457 );\r
458\r
459 if (EFI_ERROR (Status)) {\r
460 return EFI_DEVICE_ERROR;\r
461 }\r
462 }\r
463\r
464 //\r
465 // Set the current maximum bus number under the PPB\r
466 //\r
467 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
468\r
469 Status = PciRootBridgeIo->Pci.Write (\r
470 PciRootBridgeIo,\r
471 EfiPciWidthUint8,\r
472 Address,\r
473 1,\r
474 SubBusNumber\r
475 );\r
476\r
477 }\r
478\r
479 if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
480\r
481 //\r
482 // Skip sub functions, this is not a multi function device\r
483 //\r
484 Func = PCI_MAX_FUNC;\r
485 }\r
486 }\r
487 }\r
488\r
489 return EFI_SUCCESS;\r
490}\r
491\r
492/**\r
493 This routine is used to determine the root bridge attribute by interfacing\r
494 the host bridge resource allocation protocol.\r
495\r
496 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
497 @param RootBridgeDev Root bridge instance\r
498\r
499 @retval EFI_SUCCESS Successfully got root bridge's attribute.\r
500 @retval other Failed to get attribute.\r
501\r
502**/\r
503EFI_STATUS\r
504DetermineRootBridgeAttributes (\r
505 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r
506 IN PCI_IO_DEVICE *RootBridgeDev\r
507 )\r
508{\r
509 UINT64 Attributes;\r
510 EFI_STATUS Status;\r
511 EFI_HANDLE RootBridgeHandle;\r
512\r
513 Attributes = 0;\r
514 RootBridgeHandle = RootBridgeDev->Handle;\r
515\r
516 //\r
517 // Get root bridge attribute by calling into pci host bridge resource allocation protocol\r
518 //\r
519 Status = PciResAlloc->GetAllocAttributes (\r
520 PciResAlloc,\r
521 RootBridgeHandle,\r
522 &Attributes\r
523 );\r
524\r
525 if (EFI_ERROR (Status)) {\r
526 return Status;\r
527 }\r
528\r
529 //\r
530 // Here is the point where PCI bus driver calls HOST bridge allocation protocol\r
531 // Currently we hardcoded for ea815\r
532 //\r
533 if ((Attributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {\r
534 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED;\r
535 }\r
536\r
537 if ((Attributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0) {\r
60516202 538 RootBridgeDev->Decodes |= EFI_BRIDGE_MEM64_DECODE_SUPPORTED;\r
9060e3ec 539 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED;\r
540 }\r
541\r
542 RootBridgeDev->Decodes |= EFI_BRIDGE_MEM32_DECODE_SUPPORTED;\r
543 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;\r
544 RootBridgeDev->Decodes |= EFI_BRIDGE_IO16_DECODE_SUPPORTED;\r
545\r
546 return EFI_SUCCESS;\r
547}\r
548\r
549/**\r
550 Get Max Option Rom size on specified bridge.\r
551\r
552 @param Bridge Given bridge device instance.\r
553\r
554 @return Max size of option rom needed.\r
555\r
556**/\r
557UINT64\r
558GetMaxOptionRomSize (\r
559 IN PCI_IO_DEVICE *Bridge\r
560 )\r
561{\r
562 LIST_ENTRY *CurrentLink;\r
563 PCI_IO_DEVICE *Temp;\r
564 UINT64 MaxOptionRomSize;\r
565 UINT64 TempOptionRomSize;\r
566\r
567 MaxOptionRomSize = 0;\r
568\r
569 //\r
570 // Go through bridges to reach all devices\r
571 //\r
572 CurrentLink = Bridge->ChildList.ForwardLink;\r
573 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
574 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
575 if (!IsListEmpty (&Temp->ChildList)) {\r
576\r
577 //\r
578 // Get max option rom size under this bridge\r
579 //\r
580 TempOptionRomSize = GetMaxOptionRomSize (Temp);\r
581\r
582 //\r
583 // Compare with the option rom size of the bridge\r
584 // Get the larger one\r
585 //\r
586 if (Temp->RomSize > TempOptionRomSize) {\r
587 TempOptionRomSize = Temp->RomSize;\r
588 }\r
589\r
590 } else {\r
591\r
592 //\r
593 // For devices get the rom size directly\r
594 //\r
595 TempOptionRomSize = Temp->RomSize;\r
596 }\r
597\r
598 //\r
599 // Get the largest rom size on this bridge\r
600 //\r
601 if (TempOptionRomSize > MaxOptionRomSize) {\r
602 MaxOptionRomSize = TempOptionRomSize;\r
603 }\r
604\r
605 CurrentLink = CurrentLink->ForwardLink;\r
606 }\r
607\r
608 return MaxOptionRomSize;\r
609}\r
610\r
611/**\r
612 Process attributes of devices on this host bridge\r
613\r
614 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
615\r
616 @retval EFI_SUCCESS Successfully process attribute.\r
617 @retval EFI_NOT_FOUND Can not find the specific root bridge device.\r
618 @retval other Failed to determine the root bridge device's attribute.\r
619\r
620**/\r
621EFI_STATUS\r
622PciHostBridgeDeviceAttribute (\r
623 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
624 )\r
625{\r
626 EFI_HANDLE RootBridgeHandle;\r
627 PCI_IO_DEVICE *RootBridgeDev;\r
628 EFI_STATUS Status;\r
629\r
630 RootBridgeHandle = NULL;\r
631\r
632 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
633\r
634 //\r
635 // Get RootBridg Device by handle\r
636 //\r
637 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
638\r
639 if (RootBridgeDev == NULL) {\r
640 return EFI_NOT_FOUND;\r
641 }\r
642\r
643 //\r
644 // Set the attributes for devcies behind the Root Bridge\r
645 //\r
646 Status = DetermineDeviceAttribute (RootBridgeDev);\r
647 if (EFI_ERROR (Status)) {\r
648 return Status;\r
649 }\r
650\r
651 }\r
652\r
653 return EFI_SUCCESS;\r
654}\r
655\r
656/**\r
657 Get resource allocation status from the ACPI resource descriptor.\r
658\r
659 @param AcpiConfig Point to Acpi configuration table.\r
660 @param IoResStatus Return the status of I/O resource.\r
661 @param Mem32ResStatus Return the status of 32-bit Memory resource.\r
662 @param PMem32ResStatus Return the status of 32-bit Prefetchable Memory resource.\r
663 @param Mem64ResStatus Return the status of 64-bit Memory resource.\r
664 @param PMem64ResStatus Return the status of 64-bit Prefetchable Memory resource.\r
665\r
666**/\r
667VOID\r
668GetResourceAllocationStatus (\r
669 VOID *AcpiConfig,\r
670 OUT UINT64 *IoResStatus,\r
671 OUT UINT64 *Mem32ResStatus,\r
672 OUT UINT64 *PMem32ResStatus,\r
673 OUT UINT64 *Mem64ResStatus,\r
674 OUT UINT64 *PMem64ResStatus\r
675 )\r
676{\r
677 UINT8 *Temp;\r
678 UINT64 ResStatus;\r
679 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ACPIAddressDesc;\r
680\r
681 Temp = (UINT8 *) AcpiConfig;\r
682\r
683 while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
684\r
685 ACPIAddressDesc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
686 ResStatus = ACPIAddressDesc->AddrTranslationOffset;\r
687\r
688 switch (ACPIAddressDesc->ResType) {\r
689 case 0:\r
690 if (ACPIAddressDesc->AddrSpaceGranularity == 32) {\r
691 if (ACPIAddressDesc->SpecificFlag == 0x06) {\r
692 //\r
693 // Pmem32\r
694 //\r
695 *PMem32ResStatus = ResStatus;\r
696 } else {\r
697 //\r
698 // Mem32\r
699 //\r
700 *Mem32ResStatus = ResStatus;\r
701 }\r
702 }\r
703\r
704 if (ACPIAddressDesc->AddrSpaceGranularity == 64) {\r
705 if (ACPIAddressDesc->SpecificFlag == 0x06) {\r
706 //\r
707 // PMem64\r
708 //\r
709 *PMem64ResStatus = ResStatus;\r
710 } else {\r
711 //\r
712 // Mem64\r
713 //\r
714 *Mem64ResStatus = ResStatus;\r
715 }\r
716 }\r
717\r
718 break;\r
719\r
720 case 1:\r
721 //\r
722 // Io\r
723 //\r
724 *IoResStatus = ResStatus;\r
725 break;\r
726\r
727 default:\r
728 break;\r
729 }\r
730\r
731 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
732 }\r
733}\r
734\r
735/**\r
736 Remove a PCI device from device pool and mark its bar.\r
737\r
738 @param PciDevice Instance of Pci device.\r
739\r
740 @retval EFI_SUCCESS Successfully remove the PCI device.\r
741 @retval EFI_ABORTED Pci device is a root bridge or a PCI-PCI bridge.\r
742\r
743**/\r
744EFI_STATUS\r
745RejectPciDevice (\r
746 IN PCI_IO_DEVICE *PciDevice\r
747 )\r
748{\r
749 PCI_IO_DEVICE *Bridge;\r
750 PCI_IO_DEVICE *Temp;\r
751 LIST_ENTRY *CurrentLink;\r
752\r
753 //\r
754 // Remove the padding resource from a bridge\r
755 //\r
756 if ( IS_PCI_BRIDGE(&PciDevice->Pci) &&\r
757 PciDevice->ResourcePaddingDescriptors != NULL ) {\r
758 FreePool (PciDevice->ResourcePaddingDescriptors);\r
759 PciDevice->ResourcePaddingDescriptors = NULL;\r
760 return EFI_SUCCESS;\r
761 }\r
762\r
763 //\r
764 // Skip RB and PPB\r
765 //\r
766 if (IS_PCI_BRIDGE (&PciDevice->Pci) || (PciDevice->Parent == NULL)) {\r
767 return EFI_ABORTED;\r
768 }\r
769\r
770 if (IS_CARDBUS_BRIDGE (&PciDevice->Pci)) {\r
771 //\r
772 // Get the root bridge device\r
773 //\r
774 Bridge = PciDevice;\r
775 while (Bridge->Parent != NULL) {\r
776 Bridge = Bridge->Parent;\r
777 }\r
778\r
779 RemoveAllPciDeviceOnBridge (Bridge->Handle, PciDevice);\r
780\r
781 //\r
782 // Mark its bar\r
783 //\r
784 InitializeP2C (PciDevice);\r
785 }\r
786\r
787 //\r
788 // Remove the device\r
789 //\r
790 Bridge = PciDevice->Parent;\r
791 CurrentLink = Bridge->ChildList.ForwardLink;\r
792 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
793 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
794 if (Temp == PciDevice) {\r
795 InitializePciDevice (Temp);\r
796 RemoveEntryList (CurrentLink);\r
797 FreePciDevice (Temp);\r
798 return EFI_SUCCESS;\r
799 }\r
800\r
801 CurrentLink = CurrentLink->ForwardLink;\r
802 }\r
803\r
804 return EFI_ABORTED;\r
805}\r
806\r
807/**\r
808 Determine whethter a PCI device can be rejected.\r
809\r
810 @param PciResNode Pointer to Pci resource node instance.\r
811\r
812 @retval TRUE The PCI device can be rejected.\r
813 @retval TRUE The PCI device cannot be rejected.\r
814\r
815**/\r
816BOOLEAN\r
817IsRejectiveDevice (\r
818 IN PCI_RESOURCE_NODE *PciResNode\r
819 )\r
820{\r
821 PCI_IO_DEVICE *Temp;\r
822\r
823 Temp = PciResNode->PciDev;\r
824\r
825 //\r
826 // Ensure the device is present\r
827 //\r
828 if (Temp == NULL) {\r
829 return FALSE;\r
830 }\r
831\r
832 //\r
833 // PPB and RB should go ahead\r
834 //\r
835 if (IS_PCI_BRIDGE (&Temp->Pci) || (Temp->Parent == NULL)) {\r
836 return TRUE;\r
837 }\r
838\r
839 //\r
840 // Skip device on Bus0\r
841 //\r
842 if ((Temp->Parent != NULL) && (Temp->BusNumber == 0)) {\r
843 return FALSE;\r
844 }\r
845\r
846 //\r
847 // Skip VGA\r
848 //\r
849 if (IS_PCI_VGA (&Temp->Pci)) {\r
850 return FALSE;\r
851 }\r
852\r
853 return TRUE;\r
854}\r
855\r
856/**\r
857 Compare two resource nodes and get the larger resource consumer.\r
858\r
859 @param PciResNode1 resource node 1 want to be compared\r
860 @param PciResNode2 resource node 2 want to be compared\r
861\r
862 @return Larger resource node.\r
863\r
864**/\r
865PCI_RESOURCE_NODE *\r
866GetLargerConsumerDevice (\r
867 IN PCI_RESOURCE_NODE *PciResNode1,\r
868 IN PCI_RESOURCE_NODE *PciResNode2\r
869 )\r
870{\r
871 if (PciResNode2 == NULL) {\r
872 return PciResNode1;\r
873 }\r
874\r
875 if ((IS_PCI_BRIDGE(&(PciResNode2->PciDev->Pci)) || (PciResNode2->PciDev->Parent == NULL)) \\r
876 && (PciResNode2->ResourceUsage != PciResUsagePadding) )\r
877 {\r
878 return PciResNode1;\r
879 }\r
880\r
881 if (PciResNode1 == NULL) {\r
882 return PciResNode2;\r
883 }\r
884\r
885 if ((PciResNode1->Length) > (PciResNode2->Length)) {\r
886 return PciResNode1;\r
887 }\r
888\r
889 return PciResNode2;\r
890}\r
891\r
892\r
893/**\r
894 Get the max resource consumer in the host resource pool.\r
895\r
896 @param ResPool Pointer to resource pool node.\r
897\r
898 @return The max resource consumer in the host resource pool.\r
899\r
900**/\r
901PCI_RESOURCE_NODE *\r
902GetMaxResourceConsumerDevice (\r
903 IN PCI_RESOURCE_NODE *ResPool\r
904 )\r
905{\r
906 PCI_RESOURCE_NODE *Temp;\r
907 LIST_ENTRY *CurrentLink;\r
908 PCI_RESOURCE_NODE *PciResNode;\r
909 PCI_RESOURCE_NODE *PPBResNode;\r
910\r
911 PciResNode = NULL;\r
912\r
913 CurrentLink = ResPool->ChildList.ForwardLink;\r
914 while (CurrentLink != NULL && CurrentLink != &ResPool->ChildList) {\r
915\r
916 Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
917\r
918 if (!IsRejectiveDevice (Temp)) {\r
919 CurrentLink = CurrentLink->ForwardLink;\r
920 continue;\r
921 }\r
922\r
923 if ((IS_PCI_BRIDGE (&(Temp->PciDev->Pci)) || (Temp->PciDev->Parent == NULL)) \\r
924 && (Temp->ResourceUsage != PciResUsagePadding))\r
925 {\r
926 PPBResNode = GetMaxResourceConsumerDevice (Temp);\r
927 PciResNode = GetLargerConsumerDevice (PciResNode, PPBResNode);\r
928 } else {\r
929 PciResNode = GetLargerConsumerDevice (PciResNode, Temp);\r
930 }\r
931\r
932 CurrentLink = CurrentLink->ForwardLink;\r
933 }\r
934\r
935 return PciResNode;\r
936}\r
937\r
938/**\r
939 Adjust host bridge allocation so as to reduce resource requirement\r
940\r
941 @param IoPool Pointer to instance of I/O resource Node.\r
942 @param Mem32Pool Pointer to instance of 32-bit memory resource Node.\r
943 @param PMem32Pool Pointer to instance of 32-bit Prefetchable memory resource node.\r
944 @param Mem64Pool Pointer to instance of 64-bit memory resource node.\r
945 @param PMem64Pool Pointer to instance of 64-bit Prefetchable memory resource node.\r
946 @param IoResStatus Status of I/O resource Node.\r
947 @param Mem32ResStatus Status of 32-bit memory resource Node.\r
948 @param PMem32ResStatus Status of 32-bit Prefetchable memory resource node.\r
949 @param Mem64ResStatus Status of 64-bit memory resource node.\r
950 @param PMem64ResStatus Status of 64-bit Prefetchable memory resource node.\r
951\r
952 @retval EFI_SUCCESS Successfully adjusted resoruce on host bridge.\r
953 @retval EFI_ABORTED Host bridge hasn't this resource type or no resource be adjusted.\r
954\r
955**/\r
956EFI_STATUS\r
957PciHostBridgeAdjustAllocation (\r
958 IN PCI_RESOURCE_NODE *IoPool,\r
959 IN PCI_RESOURCE_NODE *Mem32Pool,\r
960 IN PCI_RESOURCE_NODE *PMem32Pool,\r
961 IN PCI_RESOURCE_NODE *Mem64Pool,\r
962 IN PCI_RESOURCE_NODE *PMem64Pool,\r
963 IN UINT64 IoResStatus,\r
964 IN UINT64 Mem32ResStatus,\r
965 IN UINT64 PMem32ResStatus,\r
966 IN UINT64 Mem64ResStatus,\r
967 IN UINT64 PMem64ResStatus\r
968 )\r
969{\r
970 BOOLEAN AllocationAjusted;\r
971 PCI_RESOURCE_NODE *PciResNode;\r
972 PCI_RESOURCE_NODE *ResPool[5];\r
973 PCI_IO_DEVICE *RemovedPciDev[5];\r
974 UINT64 ResStatus[5];\r
975 UINTN RemovedPciDevNum;\r
976 UINTN DevIndex;\r
977 UINTN ResType;\r
978 EFI_STATUS Status;\r
979 EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;\r
980\r
981 PciResNode = NULL;\r
982 ZeroMem (RemovedPciDev, 5 * sizeof (PCI_IO_DEVICE *));\r
983 RemovedPciDevNum = 0;\r
984\r
985 ResPool[0] = IoPool;\r
986 ResPool[1] = Mem32Pool;\r
987 ResPool[2] = PMem32Pool;\r
988 ResPool[3] = Mem64Pool;\r
989 ResPool[4] = PMem64Pool;\r
990\r
991 ResStatus[0] = IoResStatus;\r
992 ResStatus[1] = Mem32ResStatus;\r
993 ResStatus[2] = PMem32ResStatus;\r
994 ResStatus[3] = Mem64ResStatus;\r
995 ResStatus[4] = PMem64ResStatus;\r
996\r
997 AllocationAjusted = FALSE;\r
998\r
999 for (ResType = 0; ResType < 5; ResType++) {\r
1000\r
1001 if (ResStatus[ResType] == EFI_RESOURCE_SATISFIED) {\r
1002 continue;\r
1003 }\r
1004\r
1005 if (ResStatus[ResType] == EFI_RESOURCE_NOT_SATISFIED) {\r
1006 //\r
1007 // Host bridge hasn't this resource type\r
1008 //\r
1009 return EFI_ABORTED;\r
1010 }\r
1011\r
1012 //\r
1013 // Hostbridge hasn't enough resource\r
1014 //\r
1015 PciResNode = GetMaxResourceConsumerDevice (ResPool[ResType]);\r
1016 if (PciResNode == NULL) {\r
1017 continue;\r
1018 }\r
1019\r
1020 //\r
1021 // Check if the device has been removed before\r
1022 //\r
1023 for (DevIndex = 0; DevIndex < RemovedPciDevNum; DevIndex++) {\r
1024 if (PciResNode->PciDev == RemovedPciDev[DevIndex]) {\r
1025 break;\r
1026 }\r
1027 }\r
1028\r
1029 if (DevIndex != RemovedPciDevNum) {\r
1030 continue;\r
1031 }\r
1032\r
1033 //\r
1034 // Remove the device if it isn't in the array\r
1035 //\r
1036 Status = RejectPciDevice (PciResNode->PciDev);\r
1037 if (Status == EFI_SUCCESS) {\r
1038\r
1039 //\r
1040 // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code\r
1041 //\r
1042 //\r
1043 // Have no way to get ReqRes, AllocRes & Bar here\r
1044 //\r
1045 ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));\r
c9325700 1046 AllocFailExtendedData.DevicePathSize = (UINT16) sizeof (EFI_DEVICE_PATH_PROTOCOL);\r
9060e3ec 1047 AllocFailExtendedData.DevicePath = (UINT8 *) PciResNode->PciDev->DevicePath;\r
1048 AllocFailExtendedData.Bar = PciResNode->Bar;\r
1049\r
1050 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
1051 EFI_PROGRESS_CODE,\r
1052 EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,\r
1053 (VOID *) &AllocFailExtendedData,\r
1054 sizeof (AllocFailExtendedData)\r
1055 );\r
1056\r
1057 //\r
1058 // Add it to the array and indicate at least a device has been rejected\r
1059 //\r
1060 RemovedPciDev[RemovedPciDevNum++] = PciResNode->PciDev;\r
1061 AllocationAjusted = TRUE;\r
1062 }\r
1063 }\r
1064 //\r
1065 // End for\r
1066 //\r
1067\r
1068 if (AllocationAjusted) {\r
1069 return EFI_SUCCESS;\r
1070 } else {\r
1071 return EFI_ABORTED;\r
1072 }\r
1073}\r
1074\r
1075/**\r
1076 Summary requests for all resource type, and contruct ACPI resource\r
1077 requestor instance.\r
1078\r
1079 @param Bridge detecting bridge\r
1080 @param IoNode Pointer to instance of I/O resource Node\r
1081 @param Mem32Node Pointer to instance of 32-bit memory resource Node\r
1082 @param PMem32Node Pointer to instance of 32-bit Pmemory resource node\r
1083 @param Mem64Node Pointer to instance of 64-bit memory resource node\r
1084 @param PMem64Node Pointer to instance of 64-bit Pmemory resource node\r
1085 @param Config Output buffer holding new constructed APCI resource requestor\r
1086\r
1087 @retval EFI_SUCCESS Successfully constructed ACPI resource.\r
1088 @retval EFI_OUT_OF_RESOURCES No memory availabe.\r
1089\r
1090**/\r
1091EFI_STATUS\r
1092ConstructAcpiResourceRequestor (\r
1093 IN PCI_IO_DEVICE *Bridge,\r
1094 IN PCI_RESOURCE_NODE *IoNode,\r
1095 IN PCI_RESOURCE_NODE *Mem32Node,\r
1096 IN PCI_RESOURCE_NODE *PMem32Node,\r
1097 IN PCI_RESOURCE_NODE *Mem64Node,\r
1098 IN PCI_RESOURCE_NODE *PMem64Node,\r
1099 OUT VOID **Config\r
1100 )\r
1101{\r
1102 UINT8 NumConfig;\r
1103 UINT8 Aperture;\r
1104 UINT8 *Configuration;\r
1105 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
1106 EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;\r
1107\r
1108 NumConfig = 0;\r
1109 Aperture = 0;\r
1110\r
1111 *Config = NULL;\r
1112\r
1113 //\r
1114 // if there is io request, add to the io aperture\r
1115 //\r
1116 if (ResourceRequestExisted (IoNode)) {\r
1117 NumConfig++;\r
1118 Aperture |= 0x01;\r
1119 }\r
1120\r
1121 //\r
1122 // if there is mem32 request, add to the mem32 aperture\r
1123 //\r
1124 if (ResourceRequestExisted (Mem32Node)) {\r
1125 NumConfig++;\r
1126 Aperture |= 0x02;\r
1127 }\r
1128\r
1129 //\r
1130 // if there is pmem32 request, add to the pmem32 aperture\r
1131 //\r
1132 if (ResourceRequestExisted (PMem32Node)) {\r
1133 NumConfig++;\r
1134 Aperture |= 0x04;\r
1135 }\r
1136\r
1137 //\r
1138 // if there is mem64 request, add to the mem64 aperture\r
1139 //\r
1140 if (ResourceRequestExisted (Mem64Node)) {\r
1141 NumConfig++;\r
1142 Aperture |= 0x08;\r
1143 }\r
1144\r
1145 //\r
1146 // if there is pmem64 request, add to the pmem64 aperture\r
1147 //\r
1148 if (ResourceRequestExisted (PMem64Node)) {\r
1149 NumConfig++;\r
1150 Aperture |= 0x10;\r
1151 }\r
1152\r
1153 if (NumConfig != 0) {\r
1154\r
1155 //\r
1156 // If there is at least one type of resource request,\r
1157 // allocate a acpi resource node\r
1158 //\r
1159 Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
1160 if (Configuration == NULL) {\r
1161 return EFI_OUT_OF_RESOURCES;\r
1162 }\r
1163\r
1164 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
1165\r
1166 //\r
1167 // Deal with io aperture\r
1168 //\r
1169 if ((Aperture & 0x01) != 0) {\r
1170 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
c9325700 1171 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1172 //\r
1173 // Io\r
1174 //\r
1175 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
1176 //\r
1177 // non ISA range\r
1178 //\r
1179 Ptr->SpecificFlag = 1;\r
1180 Ptr->AddrLen = IoNode->Length;\r
1181 Ptr->AddrRangeMax = IoNode->Alignment;\r
1182\r
1183 Ptr++;\r
1184 }\r
1185 //\r
1186 // Deal with mem32 aperture\r
1187 //\r
1188 if ((Aperture & 0x02) != 0) {\r
1189 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
cd7bfc2c 1190 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1191 //\r
1192 // Mem\r
1193 //\r
1194 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1195 //\r
1196 // Nonprefechable\r
1197 //\r
1198 Ptr->SpecificFlag = 0;\r
1199 //\r
1200 // 32 bit\r
1201 //\r
1202 Ptr->AddrSpaceGranularity = 32;\r
1203 Ptr->AddrLen = Mem32Node->Length;\r
1204 Ptr->AddrRangeMax = Mem32Node->Alignment;\r
1205\r
1206 Ptr++;\r
1207 }\r
1208\r
1209 //\r
1210 // Deal with Pmem32 aperture\r
1211 //\r
1212 if ((Aperture & 0x04) != 0) {\r
1213 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
cd7bfc2c 1214 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1215 //\r
1216 // Mem\r
1217 //\r
1218 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1219 //\r
1220 // prefechable\r
1221 //\r
1222 Ptr->SpecificFlag = 0x6;\r
1223 //\r
1224 // 32 bit\r
1225 //\r
1226 Ptr->AddrSpaceGranularity = 32;\r
1227 Ptr->AddrLen = PMem32Node->Length;\r
1228 Ptr->AddrRangeMax = PMem32Node->Alignment;\r
1229\r
1230 Ptr++;\r
1231 }\r
1232 //\r
1233 // Deal with mem64 aperture\r
1234 //\r
1235 if ((Aperture & 0x08) != 0) {\r
1236 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
cd7bfc2c 1237 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1238 //\r
1239 // Mem\r
1240 //\r
1241 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1242 //\r
1243 // nonprefechable\r
1244 //\r
1245 Ptr->SpecificFlag = 0;\r
1246 //\r
1247 // 64 bit\r
1248 //\r
1249 Ptr->AddrSpaceGranularity = 64;\r
1250 Ptr->AddrLen = Mem64Node->Length;\r
1251 Ptr->AddrRangeMax = Mem64Node->Alignment;\r
1252\r
1253 Ptr++;\r
1254 }\r
1255 //\r
1256 // Deal with Pmem64 aperture\r
1257 //\r
1258 if ((Aperture & 0x10) != 0) {\r
1259 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
cd7bfc2c 1260 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1261 //\r
1262 // Mem\r
1263 //\r
1264 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1265 //\r
1266 // prefechable\r
1267 //\r
1268 Ptr->SpecificFlag = 0x06;\r
1269 //\r
1270 // 64 bit\r
1271 //\r
1272 Ptr->AddrSpaceGranularity = 64;\r
1273 Ptr->AddrLen = PMem64Node->Length;\r
1274 Ptr->AddrRangeMax = PMem64Node->Alignment;\r
1275\r
1276 Ptr++;\r
1277 }\r
1278\r
1279 //\r
1280 // put the checksum\r
1281 //\r
1282 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) Ptr;\r
1283\r
1284 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
1285 PtrEnd->Checksum = 0;\r
1286\r
1287 } else {\r
1288\r
1289 //\r
1290 // If there is no resource request\r
1291 //\r
1292 Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
1293 if (Configuration == NULL) {\r
1294 return EFI_OUT_OF_RESOURCES;\r
1295 }\r
1296\r
1297 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (Configuration);\r
1298 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
1299\r
1300 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Ptr + 1);\r
1301 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
1302 PtrEnd->Checksum = 0;\r
1303 }\r
1304\r
1305 *Config = Configuration;\r
1306\r
1307 return EFI_SUCCESS;\r
1308}\r
1309\r
1310/**\r
1311 Get resource base from an acpi configuration descriptor.\r
1312\r
1313 @param Config An acpi configuration descriptor.\r
1314 @param IoBase Output of I/O resource base address.\r
1315 @param Mem32Base Output of 32-bit memory base address.\r
1316 @param PMem32Base Output of 32-bit prefetchable memory base address.\r
1317 @param Mem64Base Output of 64-bit memory base address.\r
1318 @param PMem64Base Output of 64-bit prefetchable memory base address.\r
1319\r
1320**/\r
1321VOID\r
1322GetResourceBase (\r
1323 IN VOID *Config,\r
1324 OUT UINT64 *IoBase,\r
1325 OUT UINT64 *Mem32Base,\r
1326 OUT UINT64 *PMem32Base,\r
1327 OUT UINT64 *Mem64Base,\r
1328 OUT UINT64 *PMem64Base\r
1329 )\r
1330{\r
1331 UINT8 *Temp;\r
1332 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
1333 UINT64 ResStatus;\r
1334\r
1335 ASSERT (Config != NULL);\r
1336\r
1337 *IoBase = 0xFFFFFFFFFFFFFFFFULL;\r
1338 *Mem32Base = 0xFFFFFFFFFFFFFFFFULL;\r
1339 *PMem32Base = 0xFFFFFFFFFFFFFFFFULL;\r
1340 *Mem64Base = 0xFFFFFFFFFFFFFFFFULL;\r
1341 *PMem64Base = 0xFFFFFFFFFFFFFFFFULL;\r
1342\r
1343 Temp = (UINT8 *) Config;\r
1344\r
1345 while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
1346\r
1347 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
1348 ResStatus = Ptr->AddrTranslationOffset;\r
1349\r
1350 if (ResStatus == EFI_RESOURCE_SATISFIED) {\r
1351\r
1352 switch (Ptr->ResType) {\r
1353\r
1354 //\r
1355 // Memory type aperture\r
1356 //\r
1357 case 0:\r
1358\r
1359 //\r
1360 // Check to see the granularity\r
1361 //\r
1362 if (Ptr->AddrSpaceGranularity == 32) {\r
1363 if ((Ptr->SpecificFlag & 0x06) != 0) {\r
1364 *PMem32Base = Ptr->AddrRangeMin;\r
1365 } else {\r
1366 *Mem32Base = Ptr->AddrRangeMin;\r
1367 }\r
1368 }\r
1369\r
1370 if (Ptr->AddrSpaceGranularity == 64) {\r
1371 if ((Ptr->SpecificFlag & 0x06) != 0) {\r
1372 *PMem64Base = Ptr->AddrRangeMin;\r
1373 } else {\r
1374 *Mem64Base = Ptr->AddrRangeMin;\r
1375 }\r
1376 }\r
1377 break;\r
1378\r
1379 case 1:\r
1380\r
1381 //\r
1382 // Io type aperture\r
1383 //\r
1384 *IoBase = Ptr->AddrRangeMin;\r
1385 break;\r
1386\r
1387 default:\r
1388 break;\r
1389\r
1390 }\r
1391 //\r
1392 // End switch\r
1393 //\r
1394 }\r
1395 //\r
1396 // End for\r
1397 //\r
1398 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
1399 }\r
1400}\r
1401\r
1402/**\r
1403 Enumerate pci bridge, allocate resource and determine attribute\r
1404 for devices on this bridge.\r
1405\r
1406 @param BridgeDev Pointer to instance of bridge device.\r
1407\r
1408 @retval EFI_SUCCESS Successfully enumerated PCI bridge.\r
1409 @retval other Failed to enumerate.\r
1410\r
1411**/\r
1412EFI_STATUS\r
1413PciBridgeEnumerator (\r
1414 IN PCI_IO_DEVICE *BridgeDev\r
1415 )\r
1416{\r
1417 UINT8 SubBusNumber;\r
1418 UINT8 StartBusNumber;\r
1419 EFI_PCI_IO_PROTOCOL *PciIo;\r
1420 EFI_STATUS Status;\r
1421\r
1422 SubBusNumber = 0;\r
1423 StartBusNumber = 0;\r
1424 PciIo = &(BridgeDev->PciIo);\r
1425 Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);\r
1426\r
1427 if (EFI_ERROR (Status)) {\r
1428 return Status;\r
1429 }\r
1430\r
1431 Status = PciAssignBusNumber (\r
1432 BridgeDev,\r
1433 StartBusNumber,\r
1434 &SubBusNumber\r
1435 );\r
1436\r
1437 if (EFI_ERROR (Status)) {\r
1438 return Status;\r
1439 }\r
1440\r
1441 Status = PciPciDeviceInfoCollector (BridgeDev, StartBusNumber);\r
1442\r
1443 if (EFI_ERROR (Status)) {\r
1444 return Status;\r
1445 }\r
1446\r
1447 Status = PciBridgeResourceAllocator (BridgeDev);\r
1448\r
1449 if (EFI_ERROR (Status)) {\r
1450 return Status;\r
1451 }\r
1452\r
1453 Status = DetermineDeviceAttribute (BridgeDev);\r
1454\r
1455 if (EFI_ERROR (Status)) {\r
1456 return Status;\r
1457 }\r
1458\r
1459 return EFI_SUCCESS;\r
1460\r
1461}\r
1462\r
1463/**\r
1464 Allocate all kinds of resource for PCI bridge.\r
1465\r
1466 @param Bridge Pointer to bridge instance.\r
1467\r
1468 @retval EFI_SUCCESS Successfully allocated resource for PCI bridge.\r
1469 @retval other Failed to allocate resource for bridge.\r
1470\r
1471**/\r
1472EFI_STATUS\r
1473PciBridgeResourceAllocator (\r
1474 IN PCI_IO_DEVICE *Bridge\r
1475 )\r
1476{\r
1477 PCI_RESOURCE_NODE *IoBridge;\r
1478 PCI_RESOURCE_NODE *Mem32Bridge;\r
1479 PCI_RESOURCE_NODE *PMem32Bridge;\r
1480 PCI_RESOURCE_NODE *Mem64Bridge;\r
1481 PCI_RESOURCE_NODE *PMem64Bridge;\r
1482 UINT64 IoBase;\r
1483 UINT64 Mem32Base;\r
1484 UINT64 PMem32Base;\r
1485 UINT64 Mem64Base;\r
1486 UINT64 PMem64Base;\r
1487 EFI_STATUS Status;\r
1488\r
1489 IoBridge = CreateResourceNode (\r
1490 Bridge,\r
1491 0,\r
1ef26783 1492 Bridge->BridgeIoAlignment,\r
9060e3ec 1493 0,\r
1494 PciBarTypeIo16,\r
1495 PciResUsageTypical\r
1496 );\r
1497\r
1498 Mem32Bridge = CreateResourceNode (\r
1499 Bridge,\r
1500 0,\r
1501 0xFFFFF,\r
1502 0,\r
1503 PciBarTypeMem32,\r
1504 PciResUsageTypical\r
1505 );\r
1506\r
1507 PMem32Bridge = CreateResourceNode (\r
1508 Bridge,\r
1509 0,\r
1510 0xFFFFF,\r
1511 0,\r
1512 PciBarTypePMem32,\r
1513 PciResUsageTypical\r
1514 );\r
1515\r
1516 Mem64Bridge = CreateResourceNode (\r
1517 Bridge,\r
1518 0,\r
1519 0xFFFFF,\r
1520 0,\r
1521 PciBarTypeMem64,\r
1522 PciResUsageTypical\r
1523 );\r
1524\r
1525 PMem64Bridge = CreateResourceNode (\r
1526 Bridge,\r
1527 0,\r
1528 0xFFFFF,\r
1529 0,\r
1530 PciBarTypePMem64,\r
1531 PciResUsageTypical\r
1532 );\r
1533\r
1534 //\r
1535 // Create resourcemap by going through all the devices subject to this root bridge\r
1536 //\r
1537 CreateResourceMap (\r
1538 Bridge,\r
1539 IoBridge,\r
1540 Mem32Bridge,\r
1541 PMem32Bridge,\r
1542 Mem64Bridge,\r
1543 PMem64Bridge\r
1544 );\r
1545\r
1546 Status = GetResourceBaseFromBridge (\r
1547 Bridge,\r
1548 &IoBase,\r
1549 &Mem32Base,\r
1550 &PMem32Base,\r
1551 &Mem64Base,\r
1552 &PMem64Base\r
1553 );\r
1554\r
1555 if (EFI_ERROR (Status)) {\r
1556 return Status;\r
1557 }\r
1558\r
1559 //\r
1560 // Program IO resources\r
1561 //\r
1562 ProgramResource (\r
1563 IoBase,\r
1564 IoBridge\r
1565 );\r
1566\r
1567 //\r
1568 // Program Mem32 resources\r
1569 //\r
1570 ProgramResource (\r
1571 Mem32Base,\r
1572 Mem32Bridge\r
1573 );\r
1574\r
1575 //\r
1576 // Program PMem32 resources\r
1577 //\r
1578 ProgramResource (\r
1579 PMem32Base,\r
1580 PMem32Bridge\r
1581 );\r
1582\r
1583 //\r
1584 // Program Mem64 resources\r
1585 //\r
1586 ProgramResource (\r
1587 Mem64Base,\r
1588 Mem64Bridge\r
1589 );\r
1590\r
1591 //\r
1592 // Program PMem64 resources\r
1593 //\r
1594 ProgramResource (\r
1595 PMem64Base,\r
1596 PMem64Bridge\r
1597 );\r
1598\r
1599 DestroyResourceTree (IoBridge);\r
1600 DestroyResourceTree (Mem32Bridge);\r
1601 DestroyResourceTree (PMem32Bridge);\r
1602 DestroyResourceTree (PMem64Bridge);\r
1603 DestroyResourceTree (Mem64Bridge);\r
1604\r
1605 gBS->FreePool (IoBridge);\r
1606 gBS->FreePool (Mem32Bridge);\r
1607 gBS->FreePool (PMem32Bridge);\r
1608 gBS->FreePool (PMem64Bridge);\r
1609 gBS->FreePool (Mem64Bridge);\r
1610\r
1611 return EFI_SUCCESS;\r
1612}\r
1613\r
1614/**\r
1615 Get resource base address for a pci bridge device.\r
1616\r
1617 @param Bridge Given Pci driver instance.\r
1618 @param IoBase Output for base address of I/O type resource.\r
1619 @param Mem32Base Output for base address of 32-bit memory type resource.\r
1620 @param PMem32Base Ooutput for base address of 32-bit Pmemory type resource.\r
1621 @param Mem64Base Output for base address of 64-bit memory type resource.\r
1622 @param PMem64Base Output for base address of 64-bit Pmemory type resource.\r
1623\r
1624 @retval EFI_SUCCESS Successfully got resource base address.\r
1625 @retval EFI_OUT_OF_RESOURCES PCI bridge is not available.\r
1626\r
1627**/\r
1628EFI_STATUS\r
1629GetResourceBaseFromBridge (\r
1630 IN PCI_IO_DEVICE *Bridge,\r
1631 OUT UINT64 *IoBase,\r
1632 OUT UINT64 *Mem32Base,\r
1633 OUT UINT64 *PMem32Base,\r
1634 OUT UINT64 *Mem64Base,\r
1635 OUT UINT64 *PMem64Base\r
1636 )\r
1637{\r
1638 if (!Bridge->Allocated) {\r
1639 return EFI_OUT_OF_RESOURCES;\r
1640 }\r
1641\r
1642 *IoBase = gAllOne;\r
1643 *Mem32Base = gAllOne;\r
1644 *PMem32Base = gAllOne;\r
1645 *Mem64Base = gAllOne;\r
1646 *PMem64Base = gAllOne;\r
1647\r
1648 if (IS_PCI_BRIDGE (&Bridge->Pci)) {\r
1649\r
1650 if (Bridge->PciBar[PPB_IO_RANGE].Length > 0) {\r
1651 *IoBase = Bridge->PciBar[PPB_IO_RANGE].BaseAddress;\r
1652 }\r
1653\r
1654 if (Bridge->PciBar[PPB_MEM32_RANGE].Length > 0) {\r
1655 *Mem32Base = Bridge->PciBar[PPB_MEM32_RANGE].BaseAddress;\r
1656 }\r
1657\r
1658 if (Bridge->PciBar[PPB_PMEM32_RANGE].Length > 0) {\r
1659 *PMem32Base = Bridge->PciBar[PPB_PMEM32_RANGE].BaseAddress;\r
1660 }\r
1661\r
1662 if (Bridge->PciBar[PPB_PMEM64_RANGE].Length > 0) {\r
1663 *PMem64Base = Bridge->PciBar[PPB_PMEM64_RANGE].BaseAddress;\r
1664 } else {\r
1665 *PMem64Base = gAllOne;\r
1666 }\r
1667\r
1668 }\r
1669\r
1670 if (IS_CARDBUS_BRIDGE (&Bridge->Pci)) {\r
1671 if (Bridge->PciBar[P2C_IO_1].Length > 0) {\r
1672 *IoBase = Bridge->PciBar[P2C_IO_1].BaseAddress;\r
1673 } else {\r
1674 if (Bridge->PciBar[P2C_IO_2].Length > 0) {\r
1675 *IoBase = Bridge->PciBar[P2C_IO_2].BaseAddress;\r
1676 }\r
1677 }\r
1678\r
1679 if (Bridge->PciBar[P2C_MEM_1].Length > 0) {\r
1680 if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypePMem32) {\r
1681 *PMem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;\r
1682 }\r
1683\r
1684 if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypeMem32) {\r
1685 *Mem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;\r
1686 }\r
1687 }\r
1688\r
1689 if (Bridge->PciBar[P2C_MEM_2].Length > 0) {\r
1690 if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypePMem32) {\r
1691 *PMem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;\r
1692 }\r
1693\r
1694 if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypeMem32) {\r
1695 *Mem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;\r
1696 }\r
1697 }\r
1698 }\r
1699\r
1700 return EFI_SUCCESS;\r
1701}\r
1702\r
1703/**\r
1704 These are the notifications from the PCI bus driver that it is about to enter a certain\r
1705 phase of the PCI enumeration process.\r
1706\r
1707 This member function can be used to notify the host bridge driver to perform specific actions,\r
1708 including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r
1709 Eight notification points are defined at this time. See belows:\r
1710 EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data\r
1711 structures. The PCI enumerator should issue this notification\r
1712 before starting a fresh enumeration process. Enumeration cannot\r
1713 be restarted after sending any other notification such as\r
1714 EfiPciHostBridgeBeginBusAllocation.\r
1715 EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is\r
1716 required here. This notification can be used to perform any\r
1717 chipset-specific programming.\r
1718 EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No\r
1719 specific action is required here. This notification can be used to\r
1720 perform any chipset-specific programming.\r
1721 EfiPciHostBridgeBeginResourceAllocation\r
1722 The resource allocation phase is about to begin. No specific\r
1723 action is required here. This notification can be used to perform\r
1724 any chipset-specific programming.\r
1725 EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI\r
1726 root bridges. These resource settings are returned on the next call to\r
1727 GetProposedResources(). Before calling NotifyPhase() with a Phase of\r
1728 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r
1729 for gathering I/O and memory requests for\r
1730 all the PCI root bridges and submitting these requests using\r
1731 SubmitResources(). This function pads the resource amount\r
1732 to suit the root bridge hardware, takes care of dependencies between\r
1733 the PCI root bridges, and calls the Global Coherency Domain (GCD)\r
1734 with the allocation request. In the case of padding, the allocated range\r
1735 could be bigger than what was requested.\r
1736 EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated\r
1737 resources (proposed resources) for all the PCI root bridges. After the\r
1738 hardware is programmed, reassigning resources will not be supported.\r
1739 The bus settings are not affected.\r
1740 EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI\r
1741 root bridges and resets the I/O and memory apertures to their initial\r
1742 state. The bus settings are not affected. If the request to allocate\r
1743 resources fails, the PCI enumerator can use this notification to\r
1744 deallocate previous resources, adjust the requests, and retry\r
1745 allocation.\r
1746 EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is\r
1747 required here. This notification can be used to perform any chipsetspecific\r
1748 programming.\r
1749\r
1750 @param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
1751 @param[in] Phase The phase during enumeration\r
1752\r
1753 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r
1754 is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
1755 SubmitResources() has not been called for one or more\r
1756 PCI root bridges before this call\r
1757 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid\r
1758 for a Phase of EfiPciHostBridgeSetResources.\r
1759 @retval EFI_INVALID_PARAMETER Invalid phase parameter\r
1760 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
1761 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the\r
1762 previously submitted resource requests cannot be fulfilled or\r
1763 were only partially fulfilled.\r
1764 @retval EFI_SUCCESS The notification was accepted without any errors.\r
1765\r
1766**/\r
1767EFI_STATUS\r
1768NotifyPhase (\r
1769 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r
1770 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
1771 )\r
1772{\r
1773 EFI_HANDLE HostBridgeHandle;\r
1774 EFI_HANDLE RootBridgeHandle;\r
1775 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
1776 EFI_STATUS Status;\r
1777\r
1778 HostBridgeHandle = NULL;\r
1779 RootBridgeHandle = NULL;\r
1780 if (gPciPlatformProtocol != NULL) {\r
1781 //\r
1782 // Get Host Bridge Handle.\r
1783 //\r
1784 PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle);\r
1785\r
1786 //\r
1787 // Get the rootbridge Io protocol to find the host bridge handle\r
1788 //\r
1789 Status = gBS->HandleProtocol (\r
1790 RootBridgeHandle,\r
1791 &gEfiPciRootBridgeIoProtocolGuid,\r
1792 (VOID **) &PciRootBridgeIo\r
1793 );\r
1794\r
1795 if (EFI_ERROR (Status)) {\r
1796 return EFI_NOT_FOUND;\r
1797 }\r
1798\r
1799 HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
1800\r
1801 //\r
1802 // Call PlatformPci::PlatformNotify() if the protocol is present.\r
1803 //\r
1804 gPciPlatformProtocol->PlatformNotify (\r
1805 gPciPlatformProtocol,\r
1806 HostBridgeHandle,\r
1807 Phase,\r
1808 ChipsetEntry\r
1809 );\r
1810 } else if (gPciOverrideProtocol != NULL){\r
1811 //\r
1812 // Get Host Bridge Handle.\r
1813 //\r
1814 PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle);\r
1815\r
1816 //\r
1817 // Get the rootbridge Io protocol to find the host bridge handle\r
1818 //\r
1819 Status = gBS->HandleProtocol (\r
1820 RootBridgeHandle,\r
1821 &gEfiPciRootBridgeIoProtocolGuid,\r
1822 (VOID **) &PciRootBridgeIo\r
1823 );\r
1824\r
1825 if (EFI_ERROR (Status)) {\r
1826 return EFI_NOT_FOUND;\r
1827 }\r
1828\r
1829 HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
1830\r
1831 //\r
1832 // Call PlatformPci::PhaseNotify() if the protocol is present.\r
1833 //\r
1834 gPciOverrideProtocol->PlatformNotify (\r
1835 gPciOverrideProtocol,\r
1836 HostBridgeHandle,\r
1837 Phase,\r
1838 ChipsetEntry\r
1839 );\r
1840 } \r
1841\r
1842 Status = PciResAlloc->NotifyPhase (\r
1843 PciResAlloc,\r
1844 Phase\r
1845 );\r
1846\r
1847 if (gPciPlatformProtocol != NULL) {\r
1848 //\r
1849 // Call PlatformPci::PlatformNotify() if the protocol is present.\r
1850 //\r
1851 gPciPlatformProtocol->PlatformNotify (\r
1852 gPciPlatformProtocol,\r
1853 HostBridgeHandle,\r
1854 Phase,\r
1855 ChipsetExit\r
1856 );\r
1857\r
1858 } else if (gPciOverrideProtocol != NULL) {\r
1859 //\r
1860 // Call PlatformPci::PhaseNotify() if the protocol is present.\r
1861 //\r
1862 gPciOverrideProtocol->PlatformNotify (\r
1863 gPciOverrideProtocol,\r
1864 HostBridgeHandle,\r
1865 Phase,\r
1866 ChipsetExit\r
1867 );\r
1868 }\r
1869\r
1870 return EFI_SUCCESS;\r
1871}\r
1872\r
1873/**\r
1874 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
1875 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
1876 PCI controllers before enumeration.\r
1877\r
1878 This function is called during the PCI enumeration process. No specific action is expected from this\r
1879 member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
1880 enumeration.\r
1881\r
1882 @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
1883 @param Bus The bus number of the pci device.\r
1884 @param Device The device number of the pci device.\r
1885 @param Func The function number of the pci device.\r
1886 @param Phase The phase of the PCI device enumeration.\r
1887\r
1888 @retval EFI_SUCCESS The requested parameters were returned.\r
1889 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
1890 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
1891 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
1892 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
1893 not enumerate this device, including its child devices if it is a PCI-to-PCI\r
1894 bridge.\r
1895\r
1896**/\r
1897EFI_STATUS\r
1898PreprocessController (\r
1899 IN PCI_IO_DEVICE *Bridge,\r
1900 IN UINT8 Bus,\r
1901 IN UINT8 Device,\r
1902 IN UINT8 Func,\r
1903 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
1904 )\r
1905{\r
1906 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS RootBridgePciAddress;\r
1907 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc;\r
1908 EFI_HANDLE RootBridgeHandle;\r
1909 EFI_HANDLE HostBridgeHandle;\r
1910 EFI_STATUS Status;\r
1911\r
1912 //\r
1913 // Get the host bridge handle\r
1914 //\r
1915 HostBridgeHandle = Bridge->PciRootBridgeIo->ParentHandle;\r
1916\r
1917 //\r
1918 // Get the pci host bridge resource allocation protocol\r
1919 //\r
1920 Status = gBS->OpenProtocol (\r
1921 HostBridgeHandle,\r
1922 &gEfiPciHostBridgeResourceAllocationProtocolGuid,\r
1923 (VOID **) &PciResAlloc,\r
1924 NULL,\r
1925 NULL,\r
1926 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
1927 );\r
1928\r
1929 if (EFI_ERROR (Status)) {\r
1930 return EFI_UNSUPPORTED;\r
1931 }\r
1932\r
1933 //\r
1934 // Get Root Brige Handle\r
1935 //\r
1936 while (Bridge->Parent != NULL) {\r
1937 Bridge = Bridge->Parent;\r
1938 }\r
1939\r
1940 RootBridgeHandle = Bridge->Handle;\r
1941\r
1942 RootBridgePciAddress.Register = 0;\r
1943 RootBridgePciAddress.Function = Func;\r
1944 RootBridgePciAddress.Device = Device;\r
1945 RootBridgePciAddress.Bus = Bus;\r
1946 RootBridgePciAddress.ExtendedRegister = 0;\r
1947\r
1948 if (gPciPlatformProtocol != NULL) {\r
1949 //\r
1950 // Call PlatformPci::PrepController() if the protocol is present.\r
1951 //\r
1952 gPciPlatformProtocol->PlatformPrepController (\r
1953 gPciPlatformProtocol,\r
1954 HostBridgeHandle,\r
1955 RootBridgeHandle,\r
1956 RootBridgePciAddress,\r
1957 Phase,\r
1958 ChipsetEntry\r
1959 );\r
1960 } else if (gPciOverrideProtocol != NULL) {\r
1961 //\r
1962 // Call PlatformPci::PrepController() if the protocol is present.\r
1963 //\r
1964 gPciOverrideProtocol->PlatformPrepController (\r
1965 gPciOverrideProtocol,\r
1966 HostBridgeHandle,\r
1967 RootBridgeHandle,\r
1968 RootBridgePciAddress,\r
1969 Phase,\r
1970 ChipsetEntry\r
1971 );\r
1972 }\r
1973\r
1974 Status = PciResAlloc->PreprocessController (\r
1975 PciResAlloc,\r
1976 RootBridgeHandle,\r
1977 RootBridgePciAddress,\r
1978 Phase\r
1979 );\r
1980\r
1981 if (gPciPlatformProtocol != NULL) {\r
1982 //\r
1983 // Call PlatformPci::PrepController() if the protocol is present.\r
1984 //\r
1985 gPciPlatformProtocol->PlatformPrepController (\r
1986 gPciPlatformProtocol,\r
1987 HostBridgeHandle,\r
1988 RootBridgeHandle,\r
1989 RootBridgePciAddress,\r
1990 Phase,\r
1991 ChipsetExit\r
1992 );\r
1993 } else if (gPciOverrideProtocol != NULL) {\r
1994 //\r
1995 // Call PlatformPci::PrepController() if the protocol is present.\r
1996 //\r
1997 gPciOverrideProtocol->PlatformPrepController (\r
1998 gPciOverrideProtocol,\r
1999 HostBridgeHandle,\r
2000 RootBridgeHandle,\r
2001 RootBridgePciAddress,\r
2002 Phase,\r
2003 ChipsetExit\r
2004 );\r
2005 }\r
2006\r
2007 return EFI_SUCCESS;\r
2008}\r
2009\r
2010/**\r
2011 This function allows the PCI bus driver to be notified to act as requested when a hot-plug event has\r
2012 happened on the hot-plug controller. Currently, the operations include add operation and remove operation..\r
2013\r
2014 @param This A pointer to the hot plug request protocol.\r
2015 @param Operation The operation the PCI bus driver is requested to make.\r
2016 @param Controller The handle of the hot-plug controller.\r
2017 @param RemainingDevicePath The remaining device path for the PCI-like hot-plug device.\r
2018 @param NumberOfChildren The number of child handles.\r
2019 For a add operation, it is an output parameter.\r
2020 For a remove operation, it's an input parameter.\r
2021 @param ChildHandleBuffer The buffer which contains the child handles.\r
2022\r
2023 @retval EFI_INVALID_PARAMETER Operation is not a legal value.\r
2024 Controller is NULL or not a valid handle.\r
2025 NumberOfChildren is NULL.\r
2026 ChildHandleBuffer is NULL while Operation is add.\r
2027 @retval EFI_OUT_OF_RESOURCES There are no enough resources to start the devices.\r
2028 @retval EFI_NOT_FOUND Can not find bridge according to controller handle.\r
2029 @retval EFI_SUCCESS The handles for the specified device have been created or destroyed\r
2030 as requested, and for an add operation, the new handles are\r
2031 returned in ChildHandleBuffer.\r
2032**/\r
2033EFI_STATUS\r
2034EFIAPI\r
2035PciHotPlugRequestNotify (\r
2036 IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL * This,\r
2037 IN EFI_PCI_HOTPLUG_OPERATION Operation,\r
2038 IN EFI_HANDLE Controller,\r
2039 IN EFI_DEVICE_PATH_PROTOCOL * RemainingDevicePath OPTIONAL,\r
2040 IN OUT UINT8 *NumberOfChildren,\r
2041 IN OUT EFI_HANDLE * ChildHandleBuffer\r
2042 )\r
2043{\r
2044 PCI_IO_DEVICE *Bridge;\r
2045 PCI_IO_DEVICE *Temp;\r
2046 EFI_PCI_IO_PROTOCOL *PciIo;\r
2047 UINTN Index;\r
2048 EFI_HANDLE RootBridgeHandle;\r
2049 EFI_STATUS Status;\r
2050\r
2051 //\r
2052 // Check input parameter validity\r
2053 //\r
2054 if ((Controller == NULL) || (NumberOfChildren == NULL)){\r
2055 return EFI_INVALID_PARAMETER;\r
2056 }\r
2057\r
2058 if ((Operation != EfiPciHotPlugRequestAdd) && (Operation != EfiPciHotplugRequestRemove)) {\r
2059 return EFI_INVALID_PARAMETER;\r
2060 }\r
2061\r
2062 if (Operation == EfiPciHotPlugRequestAdd){\r
2063 if (ChildHandleBuffer == NULL) {\r
2064 return EFI_INVALID_PARAMETER;\r
2065 }\r
2066 } else if ((Operation == EfiPciHotplugRequestRemove) && (*NumberOfChildren != 0)) {\r
2067 if (ChildHandleBuffer == NULL) {\r
2068 return EFI_INVALID_PARAMETER;\r
2069 }\r
2070 }\r
2071 \r
2072 Status = gBS->OpenProtocol (\r
2073 Controller,\r
2074 &gEfiPciIoProtocolGuid,\r
2075 (VOID **) &PciIo,\r
2076 gPciBusDriverBinding.DriverBindingHandle,\r
2077 Controller,\r
2078 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
2079 );\r
2080\r
2081 if (EFI_ERROR (Status)) {\r
2082 return EFI_NOT_FOUND;\r
2083 }\r
2084\r
2085 Bridge = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);\r
2086\r
2087 //\r
2088 // Get root bridge handle\r
2089 //\r
2090 Temp = Bridge;\r
2091 while (Temp->Parent != NULL) {\r
2092 Temp = Temp->Parent;\r
2093 }\r
2094\r
2095 RootBridgeHandle = Temp->Handle;\r
2096\r
2097 if (Operation == EfiPciHotPlugRequestAdd) {\r
2098\r
2099 if (NumberOfChildren != NULL) {\r
2100 *NumberOfChildren = 0;\r
2101 }\r
2102\r
2103 if (IsListEmpty (&Bridge->ChildList)) {\r
2104\r
2105 Status = PciBridgeEnumerator (Bridge);\r
2106\r
2107 if (EFI_ERROR (Status)) {\r
2108 return Status;\r
2109 }\r
2110 }\r
2111\r
2112 Status = StartPciDevicesOnBridge (\r
2113 RootBridgeHandle,\r
2114 Bridge,\r
2115 RemainingDevicePath,\r
2116 NumberOfChildren,\r
2117 ChildHandleBuffer\r
2118 );\r
2119\r
2120 return Status;\r
2121 }\r
2122\r
2123 if (Operation == EfiPciHotplugRequestRemove) {\r
2124\r
2125 if (*NumberOfChildren == 0) {\r
2126 //\r
2127 // Remove all devices on the bridge\r
2128 //\r
2129 RemoveAllPciDeviceOnBridge (RootBridgeHandle, Bridge);\r
2130 return EFI_SUCCESS;\r
2131\r
2132 }\r
2133\r
2134 for (Index = 0; Index < *NumberOfChildren; Index++) {\r
2135 //\r
2136 // De register all the pci device\r
2137 //\r
2138 Status = DeRegisterPciDevice (RootBridgeHandle, ChildHandleBuffer[Index]);\r
2139\r
2140 if (EFI_ERROR (Status)) {\r
2141 return Status;\r
2142 }\r
2143\r
2144 }\r
2145 //\r
2146 // End for\r
2147 //\r
2148 return EFI_SUCCESS;\r
2149 }\r
2150\r
2151 return EFI_SUCCESS;\r
2152}\r
2153\r
2154/**\r
2155 Search hostbridge according to given handle\r
2156\r
2157 @param RootBridgeHandle Host bridge handle.\r
2158\r
2159 @retval TRUE Found host bridge handle.\r
2160 @retval FALSE Not found hot bridge handle.\r
2161\r
2162**/\r
2163BOOLEAN\r
2164SearchHostBridgeHandle (\r
2165 IN EFI_HANDLE RootBridgeHandle\r
2166 )\r
2167{\r
2168 EFI_HANDLE HostBridgeHandle;\r
2169 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
2170 UINTN Index;\r
2171 EFI_STATUS Status;\r
2172\r
2173 //\r
2174 // Get the rootbridge Io protocol to find the host bridge handle\r
2175 //\r
2176 Status = gBS->OpenProtocol (\r
2177 RootBridgeHandle,\r
2178 &gEfiPciRootBridgeIoProtocolGuid,\r
2179 (VOID **) &PciRootBridgeIo,\r
2180 gPciBusDriverBinding.DriverBindingHandle,\r
2181 RootBridgeHandle,\r
2182 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
2183 );\r
2184\r
2185 if (EFI_ERROR (Status)) {\r
2186 return FALSE;\r
2187 }\r
2188\r
2189 HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
2190 for (Index = 0; Index < gPciHostBridgeNumber; Index++) {\r
2191 if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {\r
2192 return TRUE;\r
2193 }\r
2194 }\r
2195\r
2196 return FALSE;\r
2197}\r
2198\r
2199/**\r
2200 Add host bridge handle to global variable for enumerating.\r
2201\r
2202 @param HostBridgeHandle Host bridge handle.\r
2203\r
2204 @retval EFI_SUCCESS Successfully added host bridge.\r
2205 @retval EFI_ABORTED Host bridge is NULL, or given host bridge\r
2206 has been in host bridge list.\r
2207\r
2208**/\r
2209EFI_STATUS\r
2210AddHostBridgeEnumerator (\r
2211 IN EFI_HANDLE HostBridgeHandle\r
2212 )\r
2213{\r
2214 UINTN Index;\r
2215\r
2216 if (HostBridgeHandle == NULL) {\r
2217 return EFI_ABORTED;\r
2218 }\r
2219\r
2220 for (Index = 0; Index < gPciHostBridgeNumber; Index++) {\r
2221 if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {\r
2222 return EFI_ABORTED;\r
2223 }\r
2224 }\r
2225\r
2226 if (Index < PCI_MAX_HOST_BRIDGE_NUM) {\r
2227 gPciHostBrigeHandles[Index] = HostBridgeHandle;\r
2228 gPciHostBridgeNumber++;\r
2229 }\r
2230\r
2231 return EFI_SUCCESS;\r
2232}\r
2233\r
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