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9060e3ec | 1 | /** @file\r |
2 | EFI PCI IO protocol functions implementation for PCI Bus module.\r | |
3 | \r | |
46537499 | 4 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r |
cd5ebaa0 | 5 | This program and the accompanying materials\r |
9060e3ec | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include "PciBus.h"\r | |
16 | \r | |
11a6cc5b JY |
17 | extern EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;\r |
18 | \r | |
9060e3ec | 19 | //\r |
20 | // Pci Io Protocol Interface\r | |
21 | //\r | |
22 | EFI_PCI_IO_PROTOCOL mPciIoInterface = {\r | |
23 | PciIoPollMem,\r | |
24 | PciIoPollIo,\r | |
25 | {\r | |
26 | PciIoMemRead,\r | |
27 | PciIoMemWrite\r | |
28 | },\r | |
29 | {\r | |
30 | PciIoIoRead,\r | |
31 | PciIoIoWrite\r | |
32 | },\r | |
33 | {\r | |
34 | PciIoConfigRead,\r | |
35 | PciIoConfigWrite\r | |
36 | },\r | |
37 | PciIoCopyMem,\r | |
38 | PciIoMap,\r | |
39 | PciIoUnmap,\r | |
40 | PciIoAllocateBuffer,\r | |
41 | PciIoFreeBuffer,\r | |
42 | PciIoFlush,\r | |
43 | PciIoGetLocation,\r | |
44 | PciIoAttributes,\r | |
45 | PciIoGetBarAttributes,\r | |
46 | PciIoSetBarAttributes,\r | |
47 | 0,\r | |
48 | NULL\r | |
49 | };\r | |
50 | \r | |
9060e3ec | 51 | /**\r |
52 | Initializes a PCI I/O Instance.\r | |
53 | \r | |
54 | @param PciIoDevice Pci device instance.\r | |
55 | \r | |
56 | **/\r | |
57 | VOID\r | |
58 | InitializePciIoInstance (\r | |
59 | IN PCI_IO_DEVICE *PciIoDevice\r | |
60 | )\r | |
61 | {\r | |
62 | CopyMem (&PciIoDevice->PciIo, &mPciIoInterface, sizeof (EFI_PCI_IO_PROTOCOL));\r | |
63 | }\r | |
64 | \r | |
65 | /**\r | |
66 | Verifies access to a PCI Base Address Register (BAR).\r | |
67 | \r | |
68 | @param PciIoDevice Pci device instance.\r | |
69 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
70 | base address for the memory or I/O operation to perform.\r | |
71 | @param Type Operation type could be memory or I/O.\r | |
72 | @param Width Signifies the width of the memory or I/O operations.\r | |
73 | @param Count The number of memory or I/O operations to perform.\r | |
74 | @param Offset The offset within the PCI configuration space for the PCI controller.\r | |
75 | \r | |
76 | @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.\r | |
77 | @retval EFI_SUCCESS Successfully verified.\r | |
78 | \r | |
79 | **/\r | |
80 | EFI_STATUS\r | |
81 | PciIoVerifyBarAccess (\r | |
82 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
83 | IN UINT8 BarIndex,\r | |
84 | IN PCI_BAR_TYPE Type,\r | |
85 | IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
86 | IN IN UINTN Count,\r | |
87 | IN UINT64 *Offset\r | |
88 | )\r | |
89 | {\r | |
3d78c020 | 90 | if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r |
9060e3ec | 91 | return EFI_INVALID_PARAMETER;\r |
92 | }\r | |
93 | \r | |
94 | if (BarIndex == EFI_PCI_IO_PASS_THROUGH_BAR) {\r | |
95 | return EFI_SUCCESS;\r | |
96 | }\r | |
97 | \r | |
98 | //\r | |
99 | // BarIndex 0-5 is legal\r | |
100 | //\r | |
101 | if (BarIndex >= PCI_MAX_BAR) {\r | |
102 | return EFI_INVALID_PARAMETER;\r | |
103 | }\r | |
104 | \r | |
105 | if (!CheckBarType (PciIoDevice, BarIndex, Type)) {\r | |
106 | return EFI_INVALID_PARAMETER;\r | |
107 | }\r | |
108 | \r | |
109 | //\r | |
110 | // If Width is EfiPciIoWidthFifoUintX then convert to EfiPciIoWidthUintX\r | |
111 | // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX\r | |
112 | //\r | |
815119f3 | 113 | if (Width >= EfiPciIoWidthFifoUint8 && Width <= EfiPciIoWidthFifoUint64) {\r |
9060e3ec | 114 | Count = 1;\r |
115 | }\r | |
116 | \r | |
117 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);\r | |
118 | \r | |
119 | if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PciIoDevice->PciBar[BarIndex].Length) {\r | |
120 | return EFI_INVALID_PARAMETER;\r | |
121 | }\r | |
122 | \r | |
123 | *Offset = *Offset + PciIoDevice->PciBar[BarIndex].BaseAddress;\r | |
124 | \r | |
125 | return EFI_SUCCESS;\r | |
126 | }\r | |
127 | \r | |
128 | /**\r | |
129 | Verifies access to a PCI Configuration Header.\r | |
130 | \r | |
131 | @param PciIoDevice Pci device instance.\r | |
132 | @param Width Signifies the width of the memory or I/O operations.\r | |
133 | @param Count The number of memory or I/O operations to perform.\r | |
134 | @param Offset The offset within the PCI configuration space for the PCI controller.\r | |
135 | \r | |
136 | @retval EFI_INVALID_PARAMETER Invalid Width\r | |
137 | @retval EFI_UNSUPPORTED Offset overflowed.\r | |
138 | @retval EFI_SUCCESS Successfully verified.\r | |
139 | \r | |
140 | **/\r | |
141 | EFI_STATUS\r | |
142 | PciIoVerifyConfigAccess (\r | |
143 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
144 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
145 | IN UINTN Count,\r | |
146 | IN UINT64 *Offset\r | |
147 | )\r | |
148 | {\r | |
149 | UINT64 ExtendOffset;\r | |
150 | \r | |
3d78c020 | 151 | if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r |
9060e3ec | 152 | return EFI_INVALID_PARAMETER;\r |
153 | }\r | |
154 | \r | |
155 | //\r | |
156 | // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX\r | |
157 | //\r | |
158 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);\r | |
159 | \r | |
160 | if (PciIoDevice->IsPciExp) {\r | |
161 | if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_EXP_MAX_CONFIG_OFFSET) {\r | |
162 | return EFI_UNSUPPORTED;\r | |
163 | }\r | |
164 | \r | |
165 | ExtendOffset = LShiftU64 (*Offset, 32);\r | |
166 | *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);\r | |
167 | *Offset = (*Offset) | ExtendOffset;\r | |
168 | \r | |
169 | } else {\r | |
170 | if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_MAX_CONFIG_OFFSET) {\r | |
171 | return EFI_UNSUPPORTED;\r | |
172 | }\r | |
173 | \r | |
174 | *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, *Offset);\r | |
175 | }\r | |
176 | \r | |
177 | return EFI_SUCCESS;\r | |
178 | }\r | |
179 | \r | |
180 | /**\r | |
181 | Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r | |
182 | satisfied or after a defined duration.\r | |
183 | \r | |
184 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
185 | @param Width Signifies the width of the memory or I/O operations.\r | |
186 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
187 | base address for the memory operation to perform.\r | |
188 | @param Offset The offset within the selected BAR to start the memory operation.\r | |
189 | @param Mask Mask used for the polling criteria.\r | |
190 | @param Value The comparison value used for the polling exit criteria.\r | |
191 | @param Delay The number of 100 ns units to poll.\r | |
192 | @param Result Pointer to the last value read from the memory location.\r | |
193 | \r | |
194 | @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r | |
195 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
196 | @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r | |
197 | @retval EFI_TIMEOUT Delay expired before a match occurred.\r | |
198 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
199 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
200 | \r | |
201 | **/\r | |
202 | EFI_STATUS\r | |
203 | EFIAPI\r | |
204 | PciIoPollMem (\r | |
205 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
206 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
207 | IN UINT8 BarIndex,\r | |
208 | IN UINT64 Offset,\r | |
209 | IN UINT64 Mask,\r | |
210 | IN UINT64 Value,\r | |
211 | IN UINT64 Delay,\r | |
212 | OUT UINT64 *Result\r | |
213 | )\r | |
214 | {\r | |
215 | EFI_STATUS Status;\r | |
216 | PCI_IO_DEVICE *PciIoDevice;\r | |
217 | \r | |
218 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
219 | \r | |
3d78c020 | 220 | if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r |
9060e3ec | 221 | return EFI_INVALID_PARAMETER;\r |
222 | }\r | |
223 | \r | |
224 | Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, 1, &Offset);\r | |
225 | if (EFI_ERROR (Status)) {\r | |
226 | return EFI_UNSUPPORTED;\r | |
227 | }\r | |
228 | \r | |
229 | if (Width > EfiPciIoWidthUint64) {\r | |
230 | return EFI_INVALID_PARAMETER;\r | |
231 | }\r | |
232 | \r | |
aeeb84ba | 233 | //\r |
234 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
235 | // \r | |
236 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
237 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
238 | Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);\r | |
239 | if (EFI_ERROR (Status)) {\r | |
240 | return Status;\r | |
241 | }\r | |
242 | if ((*Result & Mask) == Value || Delay == 0) {\r | |
243 | return EFI_SUCCESS;\r | |
244 | }\r | |
245 | do {\r | |
246 | //\r | |
247 | // Stall 10 us = 100 * 100ns\r | |
248 | //\r | |
249 | gBS->Stall (10);\r | |
250 | \r | |
251 | Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);\r | |
252 | if (EFI_ERROR (Status)) {\r | |
253 | return Status;\r | |
254 | }\r | |
255 | if ((*Result & Mask) == Value) {\r | |
256 | return EFI_SUCCESS;\r | |
257 | }\r | |
258 | if (Delay <= 100) {\r | |
259 | return EFI_TIMEOUT;\r | |
260 | }\r | |
261 | Delay -= 100;\r | |
262 | } while (TRUE);\r | |
263 | }\r | |
264 | }\r | |
265 | \r | |
9060e3ec | 266 | Status = PciIoDevice->PciRootBridgeIo->PollMem (\r |
267 | PciIoDevice->PciRootBridgeIo,\r | |
268 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
269 | Offset,\r | |
270 | Mask,\r | |
271 | Value,\r | |
272 | Delay,\r | |
273 | Result\r | |
274 | );\r | |
275 | \r | |
276 | if (EFI_ERROR (Status)) {\r | |
250057b5 | 277 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r |
278 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
279 | EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r | |
280 | PciIoDevice->DevicePath\r | |
281 | );\r | |
9060e3ec | 282 | }\r |
283 | \r | |
284 | return Status;\r | |
285 | }\r | |
286 | \r | |
287 | /**\r | |
288 | Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r | |
289 | satisfied or after a defined duration.\r | |
290 | \r | |
291 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
292 | @param Width Signifies the width of the memory or I/O operations.\r | |
293 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
294 | base address for the memory operation to perform.\r | |
295 | @param Offset The offset within the selected BAR to start the memory operation.\r | |
296 | @param Mask Mask used for the polling criteria.\r | |
297 | @param Value The comparison value used for the polling exit criteria.\r | |
298 | @param Delay The number of 100 ns units to poll.\r | |
299 | @param Result Pointer to the last value read from the memory location.\r | |
300 | \r | |
301 | @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r | |
302 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
303 | @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r | |
304 | @retval EFI_TIMEOUT Delay expired before a match occurred.\r | |
305 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
306 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
307 | \r | |
308 | **/\r | |
309 | EFI_STATUS\r | |
310 | EFIAPI\r | |
311 | PciIoPollIo (\r | |
312 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
313 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
314 | IN UINT8 BarIndex,\r | |
315 | IN UINT64 Offset,\r | |
316 | IN UINT64 Mask,\r | |
317 | IN UINT64 Value,\r | |
318 | IN UINT64 Delay,\r | |
319 | OUT UINT64 *Result\r | |
320 | )\r | |
321 | {\r | |
322 | EFI_STATUS Status;\r | |
323 | PCI_IO_DEVICE *PciIoDevice;\r | |
324 | \r | |
325 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
326 | \r | |
3d78c020 | 327 | if ((UINT32)Width > EfiPciIoWidthUint64) {\r |
9060e3ec | 328 | return EFI_INVALID_PARAMETER;\r |
329 | }\r | |
330 | \r | |
331 | Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, 1, &Offset);\r | |
332 | if (EFI_ERROR (Status)) {\r | |
333 | return EFI_UNSUPPORTED;\r | |
334 | }\r | |
335 | \r | |
aeeb84ba | 336 | //\r |
337 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
338 | // \r | |
339 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
340 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
341 | Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);\r | |
342 | if (EFI_ERROR (Status)) {\r | |
343 | return Status;\r | |
344 | }\r | |
345 | if ((*Result & Mask) == Value || Delay == 0) {\r | |
346 | return EFI_SUCCESS;\r | |
347 | }\r | |
348 | do {\r | |
349 | //\r | |
350 | // Stall 10 us = 100 * 100ns\r | |
351 | //\r | |
352 | gBS->Stall (10);\r | |
353 | \r | |
354 | Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);\r | |
355 | if (EFI_ERROR (Status)) {\r | |
356 | return Status;\r | |
357 | }\r | |
358 | if ((*Result & Mask) == Value) {\r | |
359 | return EFI_SUCCESS;\r | |
360 | }\r | |
361 | if (Delay <= 100) {\r | |
362 | return EFI_TIMEOUT;\r | |
363 | }\r | |
364 | Delay -= 100;\r | |
365 | } while (TRUE);\r | |
366 | }\r | |
367 | }\r | |
368 | \r | |
9060e3ec | 369 | Status = PciIoDevice->PciRootBridgeIo->PollIo (\r |
370 | PciIoDevice->PciRootBridgeIo,\r | |
371 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
372 | Offset,\r | |
373 | Mask,\r | |
374 | Value,\r | |
375 | Delay,\r | |
376 | Result\r | |
377 | );\r | |
378 | \r | |
379 | if (EFI_ERROR (Status)) {\r | |
250057b5 | 380 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r |
381 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
382 | EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r | |
383 | PciIoDevice->DevicePath\r | |
384 | );\r | |
9060e3ec | 385 | }\r |
386 | \r | |
387 | return Status;\r | |
388 | }\r | |
389 | \r | |
390 | /**\r | |
391 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r | |
392 | \r | |
393 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
394 | @param Width Signifies the width of the memory or I/O operations.\r | |
395 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
396 | base address for the memory or I/O operation to perform.\r | |
397 | @param Offset The offset within the selected BAR to start the memory or I/O operation.\r | |
398 | @param Count The number of memory or I/O operations to perform.\r | |
399 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
400 | operations, the source buffer to write data from.\r | |
401 | \r | |
402 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
403 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
404 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
405 | valid for the PCI BAR specified by BarIndex.\r | |
406 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
407 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
408 | \r | |
409 | **/\r | |
410 | EFI_STATUS\r | |
411 | EFIAPI\r | |
412 | PciIoMemRead (\r | |
413 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
414 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
415 | IN UINT8 BarIndex,\r | |
416 | IN UINT64 Offset,\r | |
417 | IN UINTN Count,\r | |
418 | IN OUT VOID *Buffer\r | |
419 | )\r | |
420 | {\r | |
421 | EFI_STATUS Status;\r | |
422 | PCI_IO_DEVICE *PciIoDevice;\r | |
423 | \r | |
424 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
425 | \r | |
3d78c020 | 426 | if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r |
9060e3ec | 427 | return EFI_INVALID_PARAMETER;\r |
428 | }\r | |
429 | \r | |
430 | if (Buffer == NULL) {\r | |
431 | return EFI_INVALID_PARAMETER;\r | |
432 | }\r | |
433 | \r | |
434 | Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);\r | |
435 | if (EFI_ERROR (Status)) {\r | |
436 | return EFI_UNSUPPORTED;\r | |
437 | }\r | |
438 | \r | |
aeeb84ba | 439 | //\r |
440 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
441 | // \r | |
442 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
443 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
aeeb84ba | 444 | Count *= (UINTN)(1 << (Width & 0x03));\r |
c1450e16 | 445 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r |
aeeb84ba | 446 | }\r |
447 | } \r | |
448 | \r | |
449 | \r | |
9060e3ec | 450 | Status = PciIoDevice->PciRootBridgeIo->Mem.Read (\r |
451 | PciIoDevice->PciRootBridgeIo,\r | |
452 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
453 | Offset,\r | |
454 | Count,\r | |
455 | Buffer\r | |
456 | );\r | |
457 | \r | |
458 | if (EFI_ERROR (Status)) {\r | |
250057b5 | 459 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r |
460 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
461 | EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,\r | |
462 | PciIoDevice->DevicePath\r | |
463 | );\r | |
9060e3ec | 464 | }\r |
465 | \r | |
466 | return Status;\r | |
467 | }\r | |
468 | \r | |
469 | /**\r | |
470 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r | |
471 | \r | |
472 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
473 | @param Width Signifies the width of the memory or I/O operations.\r | |
474 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
475 | base address for the memory or I/O operation to perform.\r | |
476 | @param Offset The offset within the selected BAR to start the memory or I/O operation.\r | |
477 | @param Count The number of memory or I/O operations to perform.\r | |
478 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
479 | operations, the source buffer to write data from.\r | |
480 | \r | |
481 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
482 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
483 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
484 | valid for the PCI BAR specified by BarIndex.\r | |
485 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
486 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
487 | \r | |
488 | **/\r | |
489 | EFI_STATUS\r | |
490 | EFIAPI\r | |
491 | PciIoMemWrite (\r | |
492 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
493 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
494 | IN UINT8 BarIndex,\r | |
495 | IN UINT64 Offset,\r | |
496 | IN UINTN Count,\r | |
497 | IN OUT VOID *Buffer\r | |
498 | )\r | |
499 | {\r | |
500 | EFI_STATUS Status;\r | |
501 | PCI_IO_DEVICE *PciIoDevice;\r | |
502 | \r | |
503 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
504 | \r | |
3d78c020 | 505 | if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r |
9060e3ec | 506 | return EFI_INVALID_PARAMETER;\r |
507 | }\r | |
508 | \r | |
509 | if (Buffer == NULL) {\r | |
510 | return EFI_INVALID_PARAMETER;\r | |
511 | }\r | |
512 | \r | |
513 | Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);\r | |
514 | if (EFI_ERROR (Status)) {\r | |
515 | return EFI_UNSUPPORTED;\r | |
516 | }\r | |
517 | \r | |
aeeb84ba | 518 | //\r |
519 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
520 | // \r | |
521 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
522 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
aeeb84ba | 523 | Count *= (UINTN)(1 << (Width & 0x03));\r |
c1450e16 | 524 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r |
aeeb84ba | 525 | }\r |
526 | }\r | |
527 | \r | |
9060e3ec | 528 | Status = PciIoDevice->PciRootBridgeIo->Mem.Write (\r |
529 | PciIoDevice->PciRootBridgeIo,\r | |
530 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
531 | Offset,\r | |
532 | Count,\r | |
533 | Buffer\r | |
534 | );\r | |
535 | \r | |
536 | if (EFI_ERROR (Status)) {\r | |
250057b5 | 537 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r |
538 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
539 | EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,\r | |
540 | PciIoDevice->DevicePath\r | |
541 | );\r | |
9060e3ec | 542 | }\r |
543 | \r | |
544 | return Status;\r | |
545 | }\r | |
546 | \r | |
547 | /**\r | |
548 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r | |
549 | \r | |
550 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
551 | @param Width Signifies the width of the memory or I/O operations.\r | |
552 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
553 | base address for the memory or I/O operation to perform.\r | |
554 | @param Offset The offset within the selected BAR to start the memory or I/O operation.\r | |
555 | @param Count The number of memory or I/O operations to perform.\r | |
556 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
557 | operations, the source buffer to write data from.\r | |
558 | \r | |
559 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
560 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
561 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
562 | valid for the PCI BAR specified by BarIndex.\r | |
563 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
564 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
565 | \r | |
566 | **/\r | |
567 | EFI_STATUS\r | |
568 | EFIAPI\r | |
569 | PciIoIoRead (\r | |
570 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
571 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
572 | IN UINT8 BarIndex,\r | |
573 | IN UINT64 Offset,\r | |
574 | IN UINTN Count,\r | |
575 | IN OUT VOID *Buffer\r | |
576 | )\r | |
577 | {\r | |
578 | EFI_STATUS Status;\r | |
579 | PCI_IO_DEVICE *PciIoDevice;\r | |
580 | \r | |
581 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
582 | \r | |
3d78c020 | 583 | if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r |
9060e3ec | 584 | return EFI_INVALID_PARAMETER;\r |
585 | }\r | |
586 | \r | |
587 | if (Buffer == NULL) {\r | |
588 | return EFI_INVALID_PARAMETER;\r | |
589 | }\r | |
590 | \r | |
591 | Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);\r | |
592 | if (EFI_ERROR (Status)) {\r | |
593 | return EFI_UNSUPPORTED;\r | |
594 | }\r | |
595 | \r | |
aeeb84ba | 596 | //\r |
597 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
598 | // \r | |
599 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
600 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
aeeb84ba | 601 | Count *= (UINTN)(1 << (Width & 0x03));\r |
c1450e16 | 602 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r |
aeeb84ba | 603 | }\r |
604 | } \r | |
605 | \r | |
9060e3ec | 606 | Status = PciIoDevice->PciRootBridgeIo->Io.Read (\r |
607 | PciIoDevice->PciRootBridgeIo,\r | |
608 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
609 | Offset,\r | |
610 | Count,\r | |
611 | Buffer\r | |
612 | );\r | |
613 | \r | |
614 | if (EFI_ERROR (Status)) {\r | |
250057b5 | 615 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r |
616 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
617 | EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,\r | |
618 | PciIoDevice->DevicePath\r | |
619 | );\r | |
9060e3ec | 620 | }\r |
621 | \r | |
622 | return Status;\r | |
623 | }\r | |
624 | \r | |
625 | /**\r | |
626 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r | |
627 | \r | |
628 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
629 | @param Width Signifies the width of the memory or I/O operations.\r | |
630 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
631 | base address for the memory or I/O operation to perform.\r | |
632 | @param Offset The offset within the selected BAR to start the memory or I/O operation.\r | |
633 | @param Count The number of memory or I/O operations to perform.\r | |
634 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
635 | operations, the source buffer to write data from.\r | |
636 | \r | |
637 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
638 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
639 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
640 | valid for the PCI BAR specified by BarIndex.\r | |
641 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
642 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
643 | \r | |
644 | **/\r | |
645 | EFI_STATUS\r | |
646 | EFIAPI\r | |
647 | PciIoIoWrite (\r | |
648 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
649 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
650 | IN UINT8 BarIndex,\r | |
651 | IN UINT64 Offset,\r | |
652 | IN UINTN Count,\r | |
653 | IN OUT VOID *Buffer\r | |
654 | )\r | |
655 | {\r | |
656 | EFI_STATUS Status;\r | |
657 | PCI_IO_DEVICE *PciIoDevice;\r | |
658 | \r | |
659 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
660 | \r | |
3d78c020 | 661 | if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r |
9060e3ec | 662 | return EFI_INVALID_PARAMETER;\r |
663 | }\r | |
664 | \r | |
665 | if (Buffer == NULL) {\r | |
666 | return EFI_INVALID_PARAMETER;\r | |
667 | }\r | |
668 | \r | |
669 | Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);\r | |
670 | if (EFI_ERROR (Status)) {\r | |
671 | return EFI_UNSUPPORTED;\r | |
672 | }\r | |
673 | \r | |
aeeb84ba | 674 | //\r |
675 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
676 | // \r | |
677 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
678 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
aeeb84ba | 679 | Count *= (UINTN)(1 << (Width & 0x03));\r |
c1450e16 | 680 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r |
aeeb84ba | 681 | }\r |
682 | } \r | |
683 | \r | |
9060e3ec | 684 | Status = PciIoDevice->PciRootBridgeIo->Io.Write (\r |
685 | PciIoDevice->PciRootBridgeIo,\r | |
686 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
687 | Offset,\r | |
688 | Count,\r | |
689 | Buffer\r | |
690 | );\r | |
691 | \r | |
692 | if (EFI_ERROR (Status)) {\r | |
250057b5 | 693 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r |
694 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
695 | EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,\r | |
696 | PciIoDevice->DevicePath\r | |
697 | );\r | |
9060e3ec | 698 | }\r |
699 | \r | |
700 | return Status;\r | |
701 | }\r | |
702 | \r | |
703 | /**\r | |
704 | Enable a PCI driver to access PCI controller registers in PCI configuration space.\r | |
705 | \r | |
706 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
707 | @param Width Signifies the width of the memory operations.\r | |
708 | @param Offset The offset within the PCI configuration space for the PCI controller.\r | |
709 | @param Count The number of PCI configuration operations to perform.\r | |
710 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
711 | operations, the source buffer to write data from.\r | |
712 | \r | |
713 | \r | |
714 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
715 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
716 | valid for the PCI configuration header of the PCI controller.\r | |
717 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
718 | @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r | |
719 | \r | |
720 | **/\r | |
721 | EFI_STATUS\r | |
722 | EFIAPI\r | |
723 | PciIoConfigRead (\r | |
724 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
725 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
726 | IN UINT32 Offset,\r | |
727 | IN UINTN Count,\r | |
728 | IN OUT VOID *Buffer\r | |
729 | )\r | |
730 | {\r | |
731 | EFI_STATUS Status;\r | |
732 | PCI_IO_DEVICE *PciIoDevice;\r | |
733 | UINT64 Address;\r | |
734 | \r | |
735 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
736 | \r | |
737 | Address = Offset;\r | |
738 | Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);\r | |
739 | if (EFI_ERROR (Status)) {\r | |
740 | return Status;\r | |
741 | }\r | |
aeeb84ba | 742 | \r |
743 | //\r | |
744 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
745 | // \r | |
746 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
747 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
aeeb84ba | 748 | Count *= (UINTN)(1 << (Width & 0x03));\r |
c1450e16 | 749 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r |
aeeb84ba | 750 | }\r |
751 | } \r | |
9060e3ec | 752 | \r |
753 | Status = PciIoDevice->PciRootBridgeIo->Pci.Read (\r | |
754 | PciIoDevice->PciRootBridgeIo,\r | |
755 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
756 | Address,\r | |
757 | Count,\r | |
758 | Buffer\r | |
759 | );\r | |
760 | \r | |
761 | if (EFI_ERROR (Status)) {\r | |
250057b5 | 762 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r |
763 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
764 | EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,\r | |
765 | PciIoDevice->DevicePath\r | |
766 | );\r | |
9060e3ec | 767 | }\r |
768 | \r | |
769 | return Status;\r | |
770 | }\r | |
771 | \r | |
772 | /**\r | |
773 | Enable a PCI driver to access PCI controller registers in PCI configuration space.\r | |
774 | \r | |
775 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
776 | @param Width Signifies the width of the memory operations.\r | |
777 | @param Offset The offset within the PCI configuration space for the PCI controller.\r | |
778 | @param Count The number of PCI configuration operations to perform.\r | |
779 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
780 | operations, the source buffer to write data from.\r | |
781 | \r | |
782 | \r | |
783 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
784 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
785 | valid for the PCI configuration header of the PCI controller.\r | |
786 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
787 | @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r | |
788 | \r | |
789 | **/\r | |
790 | EFI_STATUS\r | |
791 | EFIAPI\r | |
792 | PciIoConfigWrite (\r | |
793 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
794 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
795 | IN UINT32 Offset,\r | |
796 | IN UINTN Count,\r | |
797 | IN OUT VOID *Buffer\r | |
798 | )\r | |
799 | {\r | |
800 | EFI_STATUS Status;\r | |
801 | PCI_IO_DEVICE *PciIoDevice;\r | |
802 | UINT64 Address;\r | |
803 | \r | |
804 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
805 | \r | |
806 | Address = Offset;\r | |
807 | Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);\r | |
808 | if (EFI_ERROR (Status)) {\r | |
809 | return Status;\r | |
810 | }\r | |
811 | \r | |
aeeb84ba | 812 | //\r |
813 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
814 | // \r | |
815 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
816 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
aeeb84ba | 817 | Count *= (UINTN)(1 << (Width & 0x03));\r |
c1450e16 | 818 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r |
aeeb84ba | 819 | }\r |
820 | } \r | |
821 | \r | |
9060e3ec | 822 | Status = PciIoDevice->PciRootBridgeIo->Pci.Write (\r |
823 | PciIoDevice->PciRootBridgeIo,\r | |
824 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
825 | Address,\r | |
826 | Count,\r | |
827 | Buffer\r | |
828 | );\r | |
829 | \r | |
830 | if (EFI_ERROR (Status)) {\r | |
250057b5 | 831 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r |
832 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
833 | EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,\r | |
834 | PciIoDevice->DevicePath\r | |
835 | );\r | |
9060e3ec | 836 | }\r |
837 | \r | |
838 | return Status;\r | |
839 | }\r | |
840 | \r | |
841 | /**\r | |
842 | Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r | |
843 | memory space.\r | |
844 | \r | |
845 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
846 | @param Width Signifies the width of the memory operations.\r | |
847 | @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r | |
848 | base address for the memory operation to perform.\r | |
849 | @param DestOffset The destination offset within the BAR specified by DestBarIndex to\r | |
850 | start the memory writes for the copy operation.\r | |
851 | @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r | |
852 | base address for the memory operation to perform.\r | |
853 | @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r | |
854 | the memory reads for the copy operation.\r | |
855 | @param Count The number of memory operations to perform. Bytes moved is Width\r | |
856 | size * Count, starting at DestOffset and SrcOffset.\r | |
857 | \r | |
858 | @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r | |
859 | @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r | |
860 | @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r | |
861 | @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r | |
862 | is not valid for the PCI BAR specified by DestBarIndex.\r | |
863 | @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r | |
864 | not valid for the PCI BAR specified by SrcBarIndex.\r | |
865 | @retval EFI_INVALID_PARAMETER Width is invalid.\r | |
866 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
867 | \r | |
868 | **/\r | |
869 | EFI_STATUS\r | |
870 | EFIAPI\r | |
871 | PciIoCopyMem (\r | |
872 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
873 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
874 | IN UINT8 DestBarIndex,\r | |
875 | IN UINT64 DestOffset,\r | |
876 | IN UINT8 SrcBarIndex,\r | |
877 | IN UINT64 SrcOffset,\r | |
878 | IN UINTN Count\r | |
879 | )\r | |
880 | {\r | |
881 | EFI_STATUS Status;\r | |
882 | PCI_IO_DEVICE *PciIoDevice;\r | |
883 | \r | |
884 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
885 | \r | |
3d78c020 | 886 | if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r |
9060e3ec | 887 | return EFI_INVALID_PARAMETER;\r |
888 | }\r | |
889 | \r | |
890 | if (Width == EfiPciIoWidthFifoUint8 ||\r | |
891 | Width == EfiPciIoWidthFifoUint16 ||\r | |
892 | Width == EfiPciIoWidthFifoUint32 ||\r | |
893 | Width == EfiPciIoWidthFifoUint64 ||\r | |
894 | Width == EfiPciIoWidthFillUint8 ||\r | |
895 | Width == EfiPciIoWidthFillUint16 ||\r | |
896 | Width == EfiPciIoWidthFillUint32 ||\r | |
897 | Width == EfiPciIoWidthFillUint64) {\r | |
898 | return EFI_INVALID_PARAMETER;\r | |
899 | }\r | |
900 | \r | |
901 | Status = PciIoVerifyBarAccess (PciIoDevice, DestBarIndex, PciBarTypeMem, Width, Count, &DestOffset);\r | |
902 | if (EFI_ERROR (Status)) {\r | |
903 | return EFI_UNSUPPORTED;\r | |
904 | }\r | |
905 | \r | |
906 | Status = PciIoVerifyBarAccess (PciIoDevice, SrcBarIndex, PciBarTypeMem, Width, Count, &SrcOffset);\r | |
907 | if (EFI_ERROR (Status)) {\r | |
908 | return EFI_UNSUPPORTED;\r | |
909 | }\r | |
910 | \r | |
aeeb84ba | 911 | //\r |
912 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
913 | // \r | |
914 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
915 | if ((SrcOffset & ((1 << (Width & 0x03)) - 1)) != 0 || (DestOffset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
aeeb84ba | 916 | Count *= (UINTN)(1 << (Width & 0x03));\r |
c1450e16 | 917 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r |
aeeb84ba | 918 | }\r |
919 | } \r | |
920 | \r | |
9060e3ec | 921 | Status = PciIoDevice->PciRootBridgeIo->CopyMem (\r |
922 | PciIoDevice->PciRootBridgeIo,\r | |
923 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
924 | DestOffset,\r | |
925 | SrcOffset,\r | |
926 | Count\r | |
927 | );\r | |
928 | \r | |
929 | if (EFI_ERROR (Status)) {\r | |
250057b5 | 930 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r |
931 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
932 | EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r | |
933 | PciIoDevice->DevicePath\r | |
934 | );\r | |
9060e3ec | 935 | }\r |
936 | \r | |
937 | return Status;\r | |
938 | }\r | |
939 | \r | |
940 | /**\r | |
941 | Provides the PCI controller-specific addresses needed to access system memory.\r | |
942 | \r | |
943 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
944 | @param Operation Indicates if the bus master is going to read or write to system memory.\r | |
945 | @param HostAddress The system memory address to map to the PCI controller.\r | |
946 | @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r | |
947 | that were mapped.\r | |
948 | @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r | |
949 | access the hosts HostAddress.\r | |
950 | @param Mapping A resulting value to pass to Unmap().\r | |
951 | \r | |
952 | @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r | |
953 | @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r | |
954 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
955 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
956 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r | |
957 | \r | |
958 | **/\r | |
959 | EFI_STATUS\r | |
960 | EFIAPI\r | |
961 | PciIoMap (\r | |
962 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
963 | IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r | |
964 | IN VOID *HostAddress,\r | |
965 | IN OUT UINTN *NumberOfBytes,\r | |
966 | OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r | |
967 | OUT VOID **Mapping\r | |
968 | )\r | |
969 | {\r | |
11a6cc5b JY |
970 | EFI_STATUS Status;\r |
971 | PCI_IO_DEVICE *PciIoDevice;\r | |
972 | UINT64 IoMmuAttribute;\r | |
973 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION RootBridgeIoOperation;\r | |
9060e3ec | 974 | \r |
975 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
976 | \r | |
3d78c020 | 977 | if ((UINT32)Operation >= EfiPciIoOperationMaximum) {\r |
9060e3ec | 978 | return EFI_INVALID_PARAMETER;\r |
979 | }\r | |
980 | \r | |
981 | if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {\r | |
982 | return EFI_INVALID_PARAMETER;\r | |
983 | }\r | |
984 | \r | |
11a6cc5b | 985 | RootBridgeIoOperation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)Operation;\r |
9060e3ec | 986 | if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {\r |
11a6cc5b | 987 | RootBridgeIoOperation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)(Operation + EfiPciOperationBusMasterRead64);\r |
9060e3ec | 988 | }\r |
989 | \r | |
990 | Status = PciIoDevice->PciRootBridgeIo->Map (\r | |
991 | PciIoDevice->PciRootBridgeIo,\r | |
11a6cc5b | 992 | RootBridgeIoOperation,\r |
9060e3ec | 993 | HostAddress,\r |
994 | NumberOfBytes,\r | |
995 | DeviceAddress,\r | |
996 | Mapping\r | |
997 | );\r | |
998 | \r | |
999 | if (EFI_ERROR (Status)) {\r | |
250057b5 | 1000 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r |
1001 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
1002 | EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r | |
1003 | PciIoDevice->DevicePath\r | |
1004 | );\r | |
9060e3ec | 1005 | }\r |
1006 | \r | |
11a6cc5b JY |
1007 | if (mIoMmuProtocol != NULL) {\r |
1008 | if (!EFI_ERROR (Status)) {\r | |
1009 | switch (Operation) {\r | |
1010 | case EfiPciIoOperationBusMasterRead:\r | |
1011 | IoMmuAttribute = EDKII_IOMMU_ACCESS_READ;\r | |
1012 | break;\r | |
1013 | case EfiPciIoOperationBusMasterWrite:\r | |
1014 | IoMmuAttribute = EDKII_IOMMU_ACCESS_WRITE;\r | |
1015 | break;\r | |
1016 | case EfiPciIoOperationBusMasterCommonBuffer:\r | |
1017 | IoMmuAttribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;\r | |
1018 | break;\r | |
1019 | default:\r | |
1020 | ASSERT(FALSE);\r | |
1021 | return EFI_INVALID_PARAMETER;\r | |
1022 | }\r | |
1023 | mIoMmuProtocol->SetAttribute (\r | |
1024 | mIoMmuProtocol,\r | |
1025 | PciIoDevice->Handle,\r | |
1026 | *Mapping,\r | |
1027 | IoMmuAttribute\r | |
1028 | );\r | |
1029 | }\r | |
1030 | }\r | |
1031 | \r | |
9060e3ec | 1032 | return Status;\r |
1033 | }\r | |
1034 | \r | |
1035 | /**\r | |
1036 | Completes the Map() operation and releases any corresponding resources.\r | |
1037 | \r | |
1038 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
1039 | @param Mapping The mapping value returned from Map().\r | |
1040 | \r | |
1041 | @retval EFI_SUCCESS The range was unmapped.\r | |
1042 | @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r | |
1043 | \r | |
1044 | **/\r | |
1045 | EFI_STATUS\r | |
1046 | EFIAPI\r | |
1047 | PciIoUnmap (\r | |
1048 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
1049 | IN VOID *Mapping\r | |
1050 | )\r | |
1051 | {\r | |
1052 | EFI_STATUS Status;\r | |
1053 | PCI_IO_DEVICE *PciIoDevice;\r | |
1054 | \r | |
1055 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
1056 | \r | |
11a6cc5b JY |
1057 | if (mIoMmuProtocol != NULL) {\r |
1058 | mIoMmuProtocol->SetAttribute (\r | |
1059 | mIoMmuProtocol,\r | |
1060 | PciIoDevice->Handle,\r | |
1061 | Mapping,\r | |
1062 | 0\r | |
1063 | );\r | |
1064 | }\r | |
1065 | \r | |
9060e3ec | 1066 | Status = PciIoDevice->PciRootBridgeIo->Unmap (\r |
1067 | PciIoDevice->PciRootBridgeIo,\r | |
1068 | Mapping\r | |
1069 | );\r | |
1070 | \r | |
1071 | if (EFI_ERROR (Status)) {\r | |
250057b5 | 1072 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r |
1073 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
1074 | EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r | |
1075 | PciIoDevice->DevicePath\r | |
1076 | );\r | |
9060e3ec | 1077 | }\r |
1078 | \r | |
1079 | return Status;\r | |
1080 | }\r | |
1081 | \r | |
1082 | /**\r | |
1083 | Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r | |
1084 | mapping.\r | |
1085 | \r | |
1086 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
1087 | @param Type This parameter is not used and must be ignored.\r | |
1088 | @param MemoryType The type of memory to allocate, EfiBootServicesData or\r | |
1089 | EfiRuntimeServicesData.\r | |
1090 | @param Pages The number of pages to allocate.\r | |
1091 | @param HostAddress A pointer to store the base system memory address of the\r | |
1092 | allocated range.\r | |
1093 | @param Attributes The requested bit mask of attributes for the allocated range.\r | |
1094 | \r | |
1095 | @retval EFI_SUCCESS The requested memory pages were allocated.\r | |
1096 | @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r | |
1097 | MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r | |
1098 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
1099 | @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r | |
1100 | \r | |
1101 | **/\r | |
1102 | EFI_STATUS\r | |
1103 | EFIAPI\r | |
1104 | PciIoAllocateBuffer (\r | |
1105 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
1106 | IN EFI_ALLOCATE_TYPE Type,\r | |
1107 | IN EFI_MEMORY_TYPE MemoryType,\r | |
1108 | IN UINTN Pages,\r | |
1109 | OUT VOID **HostAddress,\r | |
1110 | IN UINT64 Attributes\r | |
1111 | )\r | |
1112 | {\r | |
1113 | EFI_STATUS Status;\r | |
1114 | PCI_IO_DEVICE *PciIoDevice;\r | |
1115 | \r | |
1116 | if ((Attributes &\r | |
1117 | (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) != 0){\r | |
1118 | return EFI_UNSUPPORTED;\r | |
1119 | }\r | |
1120 | \r | |
1121 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
1122 | \r | |
1123 | if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {\r | |
1124 | Attributes |= EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE;\r | |
1125 | }\r | |
1126 | \r | |
1127 | Status = PciIoDevice->PciRootBridgeIo->AllocateBuffer (\r | |
1128 | PciIoDevice->PciRootBridgeIo,\r | |
1129 | Type,\r | |
1130 | MemoryType,\r | |
1131 | Pages,\r | |
1132 | HostAddress,\r | |
1133 | Attributes\r | |
1134 | );\r | |
1135 | \r | |
1136 | if (EFI_ERROR (Status)) {\r | |
250057b5 | 1137 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r |
1138 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
1139 | EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r | |
1140 | PciIoDevice->DevicePath\r | |
1141 | );\r | |
9060e3ec | 1142 | }\r |
1143 | \r | |
1144 | return Status;\r | |
1145 | }\r | |
1146 | \r | |
1147 | /**\r | |
1148 | Frees memory that was allocated with AllocateBuffer().\r | |
1149 | \r | |
1150 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
1151 | @param Pages The number of pages to free.\r | |
1152 | @param HostAddress The base system memory address of the allocated range.\r | |
1153 | \r | |
1154 | @retval EFI_SUCCESS The requested memory pages were freed.\r | |
1155 | @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r | |
1156 | was not allocated with AllocateBuffer().\r | |
1157 | \r | |
1158 | **/\r | |
1159 | EFI_STATUS\r | |
1160 | EFIAPI\r | |
1161 | PciIoFreeBuffer (\r | |
1162 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
1163 | IN UINTN Pages,\r | |
1164 | IN VOID *HostAddress\r | |
1165 | )\r | |
1166 | {\r | |
1167 | EFI_STATUS Status;\r | |
1168 | PCI_IO_DEVICE *PciIoDevice;\r | |
1169 | \r | |
1170 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
1171 | \r | |
1172 | Status = PciIoDevice->PciRootBridgeIo->FreeBuffer (\r | |
1173 | PciIoDevice->PciRootBridgeIo,\r | |
1174 | Pages,\r | |
1175 | HostAddress\r | |
1176 | );\r | |
1177 | \r | |
1178 | if (EFI_ERROR (Status)) {\r | |
250057b5 | 1179 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r |
1180 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
1181 | EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r | |
1182 | PciIoDevice->DevicePath\r | |
1183 | );\r | |
9060e3ec | 1184 | }\r |
1185 | \r | |
1186 | return Status;\r | |
1187 | }\r | |
1188 | \r | |
1189 | /**\r | |
1190 | Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r | |
1191 | \r | |
1192 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
1193 | \r | |
1194 | @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r | |
1195 | bridge to system memory.\r | |
1196 | @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r | |
1197 | host bridge due to a hardware error.\r | |
1198 | \r | |
1199 | **/\r | |
1200 | EFI_STATUS\r | |
1201 | EFIAPI\r | |
1202 | PciIoFlush (\r | |
1203 | IN EFI_PCI_IO_PROTOCOL *This\r | |
1204 | )\r | |
1205 | {\r | |
1206 | EFI_STATUS Status;\r | |
1207 | PCI_IO_DEVICE *PciIoDevice;\r | |
1208 | \r | |
1209 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
1210 | \r | |
1211 | Status = PciIoDevice->PciRootBridgeIo->Flush (\r | |
1212 | PciIoDevice->PciRootBridgeIo\r | |
1213 | );\r | |
1214 | if (EFI_ERROR (Status)) {\r | |
250057b5 | 1215 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r |
1216 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
1217 | EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r | |
1218 | PciIoDevice->DevicePath\r | |
1219 | );\r | |
9060e3ec | 1220 | }\r |
1221 | \r | |
1222 | return Status;\r | |
1223 | }\r | |
1224 | \r | |
1225 | /**\r | |
1226 | Retrieves this PCI controller's current PCI bus number, device number, and function number.\r | |
1227 | \r | |
1228 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
1229 | @param SegmentNumber The PCI controller's current PCI segment number.\r | |
1230 | @param BusNumber The PCI controller's current PCI bus number.\r | |
1231 | @param DeviceNumber The PCI controller's current PCI device number.\r | |
1232 | @param FunctionNumber The PCI controller's current PCI function number.\r | |
1233 | \r | |
1234 | @retval EFI_SUCCESS The PCI controller location was returned.\r | |
1235 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
1236 | \r | |
1237 | **/\r | |
1238 | EFI_STATUS\r | |
1239 | EFIAPI\r | |
1240 | PciIoGetLocation (\r | |
1241 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
1242 | OUT UINTN *Segment,\r | |
1243 | OUT UINTN *Bus,\r | |
1244 | OUT UINTN *Device,\r | |
1245 | OUT UINTN *Function\r | |
1246 | )\r | |
1247 | {\r | |
1248 | PCI_IO_DEVICE *PciIoDevice;\r | |
1249 | \r | |
1250 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
1251 | \r | |
1252 | if (Segment == NULL || Bus == NULL || Device == NULL || Function == NULL) {\r | |
1253 | return EFI_INVALID_PARAMETER;\r | |
1254 | }\r | |
1255 | \r | |
1256 | *Segment = PciIoDevice->PciRootBridgeIo->SegmentNumber;\r | |
1257 | *Bus = PciIoDevice->BusNumber;\r | |
1258 | *Device = PciIoDevice->DeviceNumber;\r | |
1259 | *Function = PciIoDevice->FunctionNumber;\r | |
1260 | \r | |
1261 | return EFI_SUCCESS;\r | |
1262 | }\r | |
1263 | \r | |
1264 | /**\r | |
1265 | Check BAR type for PCI resource.\r | |
1266 | \r | |
1267 | @param PciIoDevice PCI device instance.\r | |
1268 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
1269 | base address for the memory or I/O operation to perform.\r | |
1270 | @param BarType Memory or I/O.\r | |
1271 | \r | |
1272 | @retval TRUE Pci device's bar type is same with input BarType.\r | |
1273 | @retval TRUE Pci device's bar type is not same with input BarType.\r | |
1274 | \r | |
1275 | **/\r | |
1276 | BOOLEAN\r | |
1277 | CheckBarType (\r | |
1278 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
1279 | IN UINT8 BarIndex,\r | |
1280 | IN PCI_BAR_TYPE BarType\r | |
1281 | )\r | |
1282 | {\r | |
1283 | switch (BarType) {\r | |
1284 | \r | |
1285 | case PciBarTypeMem:\r | |
1286 | \r | |
1287 | if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem32 &&\r | |
1288 | PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem32 &&\r | |
1289 | PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem64 &&\r | |
1290 | PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem64 ) {\r | |
1291 | return FALSE;\r | |
1292 | }\r | |
1293 | \r | |
1294 | return TRUE;\r | |
1295 | \r | |
1296 | case PciBarTypeIo:\r | |
1297 | if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo32 &&\r | |
1298 | PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo16){\r | |
1299 | return FALSE;\r | |
1300 | }\r | |
1301 | \r | |
1302 | return TRUE;\r | |
1303 | \r | |
1304 | default:\r | |
1305 | break;\r | |
1306 | }\r | |
1307 | \r | |
1308 | return FALSE;\r | |
1309 | }\r | |
1310 | \r | |
1311 | /**\r | |
1312 | Set/Disable new attributes to a Root Bridge.\r | |
1313 | \r | |
1314 | @param PciIoDevice Pci device instance.\r | |
1315 | @param Attributes New attribute want to be set.\r | |
1316 | @param Operation Set or Disable.\r | |
1317 | \r | |
1318 | @retval EFI_UNSUPPORTED If root bridge does not support change attribute.\r | |
1319 | @retval EFI_SUCCESS Successfully set new attributs.\r | |
1320 | \r | |
1321 | **/\r | |
1322 | EFI_STATUS\r | |
1323 | ModifyRootBridgeAttributes (\r | |
1324 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
1325 | IN UINT64 Attributes,\r | |
1326 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r | |
1327 | )\r | |
1328 | {\r | |
1329 | UINT64 PciRootBridgeSupports;\r | |
1330 | UINT64 PciRootBridgeAttributes;\r | |
1331 | UINT64 NewPciRootBridgeAttributes;\r | |
1332 | EFI_STATUS Status;\r | |
1333 | \r | |
1334 | //\r | |
1335 | // Get the current attributes of this PCI device's PCI Root Bridge\r | |
1336 | //\r | |
1337 | Status = PciIoDevice->PciRootBridgeIo->GetAttributes (\r | |
1338 | PciIoDevice->PciRootBridgeIo,\r | |
1339 | &PciRootBridgeSupports,\r | |
1340 | &PciRootBridgeAttributes\r | |
1341 | );\r | |
1342 | if (EFI_ERROR (Status)) {\r | |
1343 | return EFI_UNSUPPORTED;\r | |
1344 | }\r | |
1345 | \r | |
7afa5ea8 | 1346 | //\r |
5a3a6aa7 | 1347 | // Mask off attributes not supported by PCI root bridge.\r |
7afa5ea8 | 1348 | //\r |
1349 | Attributes &= ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |\r | |
5a3a6aa7 | 1350 | EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |\r |
1351 | EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);\r | |
7afa5ea8 | 1352 | \r |
9060e3ec | 1353 | //\r |
1354 | // Record the new attribute of the Root Bridge\r | |
1355 | //\r | |
1356 | if (Operation == EfiPciIoAttributeOperationEnable) {\r | |
1357 | NewPciRootBridgeAttributes = PciRootBridgeAttributes | Attributes;\r | |
1358 | } else {\r | |
1359 | NewPciRootBridgeAttributes = PciRootBridgeAttributes & (~Attributes);\r | |
1360 | }\r | |
1361 | \r | |
1362 | //\r | |
1363 | // Call the PCI Root Bridge to attempt to modify the attributes\r | |
1364 | //\r | |
1365 | if ((NewPciRootBridgeAttributes ^ PciRootBridgeAttributes) != 0) {\r | |
1366 | \r | |
1367 | Status = PciIoDevice->PciRootBridgeIo->SetAttributes (\r | |
1368 | PciIoDevice->PciRootBridgeIo,\r | |
1369 | NewPciRootBridgeAttributes,\r | |
1370 | NULL,\r | |
1371 | NULL\r | |
1372 | );\r | |
1373 | if (EFI_ERROR (Status)) {\r | |
1374 | //\r | |
1375 | // The PCI Root Bridge could not modify the attributes, so return the error.\r | |
1376 | //\r | |
1377 | return EFI_UNSUPPORTED;\r | |
1378 | }\r | |
1379 | }\r | |
1380 | \r | |
1381 | //\r | |
1382 | // Also update the attributes for this Root Bridge structure\r | |
1383 | //\r | |
1384 | PciIoDevice->Attributes = NewPciRootBridgeAttributes;\r | |
1385 | \r | |
1386 | return EFI_SUCCESS;\r | |
1387 | }\r | |
1388 | \r | |
1389 | /**\r | |
1390 | Check whether this device can be enable/disable to snoop.\r | |
1391 | \r | |
1392 | @param PciIoDevice Pci device instance.\r | |
1393 | @param Operation Enable/Disable.\r | |
1394 | \r | |
1395 | @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop.\r | |
1396 | @retval EFI_SUCCESS Snoop can be supported.\r | |
1397 | \r | |
1398 | **/\r | |
1399 | EFI_STATUS\r | |
1400 | SupportPaletteSnoopAttributes (\r | |
1401 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
1402 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r | |
1403 | )\r | |
1404 | {\r | |
1405 | PCI_IO_DEVICE *Temp;\r | |
1406 | UINT16 VGACommand;\r | |
1407 | \r | |
1408 | //\r | |
1409 | // Snoop attribute can be only modified by GFX\r | |
1410 | //\r | |
1411 | if (!IS_PCI_GFX (&PciIoDevice->Pci)) {\r | |
1412 | return EFI_UNSUPPORTED;\r | |
1413 | }\r | |
1414 | \r | |
1415 | //\r | |
1416 | // Get the boot VGA on the same segement\r | |
1417 | //\r | |
1418 | Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);\r | |
1419 | \r | |
1420 | if (Temp == NULL) {\r | |
1421 | //\r | |
1422 | // If there is no VGA device on the segement, set\r | |
1423 | // this graphics card to decode the palette range\r | |
1424 | //\r | |
1425 | return EFI_SUCCESS;\r | |
1426 | }\r | |
1427 | \r | |
1428 | //\r | |
1429 | // Check these two agents are on the same path\r | |
1430 | //\r | |
1431 | if (!PciDevicesOnTheSamePath (Temp, PciIoDevice)) {\r | |
1432 | //\r | |
1433 | // they are not on the same path, so snoop can be enabled or disabled\r | |
1434 | //\r | |
1435 | return EFI_SUCCESS;\r | |
1436 | }\r | |
1437 | //\r | |
1438 | // Check if they are on the same bus\r | |
1439 | //\r | |
1440 | if (Temp->Parent == PciIoDevice->Parent) {\r | |
1441 | \r | |
1442 | PCI_READ_COMMAND_REGISTER (Temp, &VGACommand);\r | |
1443 | \r | |
1444 | //\r | |
1445 | // If they are on the same bus, either one can\r | |
1446 | // be set to snoop, the other set to decode\r | |
1447 | //\r | |
1448 | if ((VGACommand & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {\r | |
1449 | //\r | |
1450 | // VGA has set to snoop, so GFX can be only set to disable snoop\r | |
1451 | //\r | |
1452 | if (Operation == EfiPciIoAttributeOperationEnable) {\r | |
1453 | return EFI_UNSUPPORTED;\r | |
1454 | }\r | |
1455 | } else {\r | |
1456 | //\r | |
1457 | // VGA has disabled to snoop, so GFX can be only enabled\r | |
1458 | //\r | |
1459 | if (Operation == EfiPciIoAttributeOperationDisable) {\r | |
1460 | return EFI_UNSUPPORTED;\r | |
1461 | }\r | |
1462 | }\r | |
1463 | \r | |
1464 | return EFI_SUCCESS;\r | |
1465 | }\r | |
1466 | \r | |
1467 | //\r | |
1468 | // If they are on the same path but on the different bus\r | |
1469 | // The first agent is set to snoop, the second one set to\r | |
1470 | // decode\r | |
1471 | //\r | |
1472 | \r | |
1473 | if (Temp->BusNumber < PciIoDevice->BusNumber) {\r | |
1474 | //\r | |
1475 | // GFX should be set to decode\r | |
1476 | //\r | |
1477 | if (Operation == EfiPciIoAttributeOperationDisable) {\r | |
1478 | PCI_ENABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r | |
1479 | Temp->Attributes |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;\r | |
1480 | } else {\r | |
1481 | return EFI_UNSUPPORTED;\r | |
1482 | }\r | |
1483 | \r | |
1484 | } else {\r | |
1485 | //\r | |
1486 | // GFX should be set to snoop\r | |
1487 | //\r | |
1488 | if (Operation == EfiPciIoAttributeOperationEnable) {\r | |
1489 | PCI_DISABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r | |
6e1e5405 | 1490 | Temp->Attributes &= (~(UINT64)EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r |
9060e3ec | 1491 | } else {\r |
1492 | return EFI_UNSUPPORTED;\r | |
1493 | }\r | |
1494 | \r | |
1495 | }\r | |
1496 | \r | |
1497 | return EFI_SUCCESS;\r | |
1498 | }\r | |
1499 | \r | |
1500 | /**\r | |
1501 | Performs an operation on the attributes that this PCI controller supports. The operations include\r | |
1502 | getting the set of supported attributes, retrieving the current attributes, setting the current\r | |
1503 | attributes, enabling attributes, and disabling attributes.\r | |
1504 | \r | |
1505 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
1506 | @param Operation The operation to perform on the attributes for this PCI controller.\r | |
1507 | @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r | |
1508 | operations.\r | |
1509 | @param Result A pointer to the result mask of attributes that are returned for the Get\r | |
1510 | and Supported operations.\r | |
1511 | \r | |
1512 | @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r | |
1513 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
1514 | @retval EFI_UNSUPPORTED one or more of the bits set in\r | |
1515 | Attributes are not supported by this PCI controller or one of\r | |
1516 | its parent bridges when Operation is Set, Enable or Disable.\r | |
1517 | \r | |
1518 | **/\r | |
1519 | EFI_STATUS\r | |
1520 | EFIAPI\r | |
1521 | PciIoAttributes (\r | |
1522 | IN EFI_PCI_IO_PROTOCOL * This,\r | |
1523 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r | |
1524 | IN UINT64 Attributes,\r | |
1525 | OUT UINT64 *Result OPTIONAL\r | |
1526 | )\r | |
1527 | {\r | |
1528 | EFI_STATUS Status;\r | |
1529 | \r | |
1530 | PCI_IO_DEVICE *PciIoDevice;\r | |
1531 | PCI_IO_DEVICE *UpStreamBridge;\r | |
1532 | PCI_IO_DEVICE *Temp;\r | |
1533 | \r | |
1534 | UINT64 Supports;\r | |
1535 | UINT64 UpStreamAttributes;\r | |
1536 | UINT16 BridgeControl;\r | |
1537 | UINT16 Command;\r | |
1538 | \r | |
1539 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
1540 | \r | |
1541 | switch (Operation) {\r | |
1542 | case EfiPciIoAttributeOperationGet:\r | |
1543 | if (Result == NULL) {\r | |
1544 | return EFI_INVALID_PARAMETER;\r | |
1545 | }\r | |
1546 | \r | |
1547 | *Result = PciIoDevice->Attributes;\r | |
1548 | return EFI_SUCCESS;\r | |
1549 | \r | |
1550 | case EfiPciIoAttributeOperationSupported:\r | |
1551 | if (Result == NULL) {\r | |
1552 | return EFI_INVALID_PARAMETER;\r | |
1553 | }\r | |
1554 | \r | |
1555 | *Result = PciIoDevice->Supports;\r | |
1556 | return EFI_SUCCESS;\r | |
1557 | \r | |
1558 | case EfiPciIoAttributeOperationSet:\r | |
1559 | Status = PciIoDevice->PciIo.Attributes (\r | |
1560 | &(PciIoDevice->PciIo),\r | |
1561 | EfiPciIoAttributeOperationEnable,\r | |
1562 | Attributes,\r | |
1563 | NULL\r | |
1564 | );\r | |
1565 | if (EFI_ERROR (Status)) {\r | |
1566 | return EFI_UNSUPPORTED;\r | |
1567 | }\r | |
1568 | \r | |
1569 | Status = PciIoDevice->PciIo.Attributes (\r | |
1570 | &(PciIoDevice->PciIo),\r | |
1571 | EfiPciIoAttributeOperationDisable,\r | |
1572 | (~Attributes) & (PciIoDevice->Supports),\r | |
1573 | NULL\r | |
1574 | );\r | |
1575 | if (EFI_ERROR (Status)) {\r | |
1576 | return EFI_UNSUPPORTED;\r | |
1577 | }\r | |
1578 | \r | |
1579 | return EFI_SUCCESS;\r | |
1580 | \r | |
1581 | case EfiPciIoAttributeOperationEnable:\r | |
1582 | case EfiPciIoAttributeOperationDisable:\r | |
1583 | break;\r | |
1584 | \r | |
1585 | default:\r | |
1586 | return EFI_INVALID_PARAMETER;\r | |
1587 | }\r | |
1588 | //\r | |
1589 | // Just a trick for ENABLE attribute\r | |
1590 | // EFI_PCI_DEVICE_ENABLE is not defined in UEFI spec, which is the internal usage.\r | |
1591 | // So, this logic doesn't confrom to UEFI spec, which should be removed.\r | |
1592 | // But this trick logic is still kept for some binary drivers that depend on it.\r | |
1593 | //\r | |
1594 | if ((Attributes & EFI_PCI_DEVICE_ENABLE) == EFI_PCI_DEVICE_ENABLE) {\r | |
1595 | Attributes &= (PciIoDevice->Supports);\r | |
1596 | \r | |
1597 | //\r | |
1598 | // Raise the EFI_P_PC_ENABLE Status code\r | |
1599 | //\r | |
1600 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r | |
1601 | EFI_PROGRESS_CODE,\r | |
1602 | EFI_IO_BUS_PCI | EFI_P_PC_ENABLE,\r | |
1603 | PciIoDevice->DevicePath\r | |
1604 | );\r | |
1605 | }\r | |
1606 | \r | |
e0ee9d93 | 1607 | //\r |
1608 | // Check VGA and VGA16, they can not be set at the same time\r | |
1609 | //\r | |
b5675042 MK |
1610 | if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO)) != 0) {\r |
1611 | if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {\r | |
1612 | return EFI_UNSUPPORTED;\r | |
1613 | }\r | |
e0ee9d93 | 1614 | }\r |
1615 | \r | |
9060e3ec | 1616 | //\r |
1617 | // If no attributes can be supported, then return.\r | |
1618 | // Otherwise, set the attributes that it can support.\r | |
1619 | //\r | |
1620 | Supports = (PciIoDevice->Supports) & Attributes;\r | |
1621 | if (Supports != Attributes) {\r | |
1622 | return EFI_UNSUPPORTED;\r | |
1623 | }\r | |
1624 | \r | |
1625 | //\r | |
1626 | // For Root Bridge, just call RootBridgeIo to set attributes;\r | |
1627 | //\r | |
1628 | if (PciIoDevice->Parent == NULL) {\r | |
1629 | Status = ModifyRootBridgeAttributes (PciIoDevice, Attributes, Operation);\r | |
1630 | return Status;\r | |
1631 | }\r | |
1632 | \r | |
1633 | Command = 0;\r | |
1634 | BridgeControl = 0;\r | |
1635 | \r | |
9060e3ec | 1636 | //\r |
1637 | // For PPB & P2C, set relevant attribute bits\r | |
1638 | //\r | |
1639 | if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r | |
1640 | \r | |
1641 | if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {\r | |
1642 | BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA;\r | |
1643 | }\r | |
1644 | \r | |
1645 | if ((Attributes & EFI_PCI_IO_ATTRIBUTE_ISA_IO) != 0) {\r | |
1646 | BridgeControl |= EFI_PCI_BRIDGE_CONTROL_ISA;\r | |
1647 | }\r | |
1648 | \r | |
1649 | if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {\r | |
1650 | Command |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;\r | |
1651 | }\r | |
1652 | \r | |
1653 | if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {\r | |
1654 | BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA_16;\r | |
1655 | }\r | |
1656 | \r | |
1657 | } else {\r | |
1658 | //\r | |
1659 | // Do with the attributes on VGA\r | |
1660 | // Only for VGA's legacy resource, we just can enable once.\r | |
1661 | //\r | |
1662 | if ((Attributes &\r | |
1663 | (EFI_PCI_IO_ATTRIBUTE_VGA_IO |\r | |
1664 | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 |\r | |
1665 | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY)) != 0) {\r | |
1666 | //\r | |
1667 | // Check if a VGA has been enabled before enabling a new one\r | |
1668 | //\r | |
1669 | if (Operation == EfiPciIoAttributeOperationEnable) {\r | |
1670 | //\r | |
1671 | // Check if there have been an active VGA device on the same segment\r | |
1672 | //\r | |
1673 | Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);\r | |
1674 | if (Temp != NULL && Temp != PciIoDevice) {\r | |
1675 | //\r | |
1676 | // An active VGA has been detected, so can not enable another\r | |
1677 | //\r | |
1678 | return EFI_UNSUPPORTED;\r | |
1679 | }\r | |
1680 | }\r | |
1681 | }\r | |
1682 | \r | |
1683 | //\r | |
1684 | // Do with the attributes on GFX\r | |
1685 | //\r | |
1686 | if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {\r | |
1687 | \r | |
1688 | if (Operation == EfiPciIoAttributeOperationEnable) {\r | |
1689 | //\r | |
1690 | // Check if snoop can be enabled in current configuration\r | |
1691 | //\r | |
1692 | Status = SupportPaletteSnoopAttributes (PciIoDevice, Operation);\r | |
1693 | \r | |
1694 | if (EFI_ERROR (Status)) {\r | |
1695 | \r | |
1696 | //\r | |
1697 | // Enable operation is forbidden, so mask the bit in attributes\r | |
1698 | // so as to keep consistent with the actual Status\r | |
1699 | //\r | |
1700 | // Attributes &= (~EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO);\r | |
1701 | //\r | |
1702 | //\r | |
1703 | //\r | |
1704 | return EFI_UNSUPPORTED;\r | |
1705 | \r | |
1706 | }\r | |
1707 | }\r | |
1708 | \r | |
1709 | //\r | |
1710 | // It can be supported, so get ready to set the bit\r | |
1711 | //\r | |
1712 | Command |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;\r | |
1713 | }\r | |
1714 | }\r | |
1715 | \r | |
1716 | if ((Attributes & EFI_PCI_IO_ATTRIBUTE_IO) != 0) {\r | |
1717 | Command |= EFI_PCI_COMMAND_IO_SPACE;\r | |
1718 | }\r | |
1719 | \r | |
1720 | if ((Attributes & EFI_PCI_IO_ATTRIBUTE_MEMORY) != 0) {\r | |
1721 | Command |= EFI_PCI_COMMAND_MEMORY_SPACE;\r | |
1722 | }\r | |
1723 | \r | |
1724 | if ((Attributes & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) != 0) {\r | |
1725 | Command |= EFI_PCI_COMMAND_BUS_MASTER;\r | |
1726 | }\r | |
1727 | //\r | |
1728 | // The upstream bridge should be also set to revelant attribute\r | |
1729 | // expect for IO, Mem and BusMaster\r | |
1730 | //\r | |
1731 | UpStreamAttributes = Attributes &\r | |
1732 | (~(EFI_PCI_IO_ATTRIBUTE_IO |\r | |
1733 | EFI_PCI_IO_ATTRIBUTE_MEMORY |\r | |
1734 | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER\r | |
1735 | )\r | |
1736 | );\r | |
1737 | UpStreamBridge = PciIoDevice->Parent;\r | |
1738 | \r | |
1739 | if (Operation == EfiPciIoAttributeOperationEnable) {\r | |
1740 | //\r | |
1741 | // Enable relevant attributes to command register and bridge control register\r | |
1742 | //\r | |
1743 | Status = PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, Command);\r | |
1744 | if (BridgeControl != 0) {\r | |
1745 | Status = PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);\r | |
1746 | }\r | |
1747 | \r | |
1748 | PciIoDevice->Attributes |= Attributes;\r | |
1749 | \r | |
1750 | //\r | |
1751 | // Enable attributes of the upstream bridge\r | |
1752 | //\r | |
1753 | Status = UpStreamBridge->PciIo.Attributes (\r | |
1754 | &(UpStreamBridge->PciIo),\r | |
1755 | EfiPciIoAttributeOperationEnable,\r | |
1756 | UpStreamAttributes,\r | |
1757 | NULL\r | |
1758 | );\r | |
1759 | } else {\r | |
1760 | \r | |
1761 | //\r | |
1762 | // Disable relevant attributes to command register and bridge control register\r | |
1763 | //\r | |
1764 | Status = PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, Command);\r | |
1765 | if (BridgeControl != 0) {\r | |
1766 | Status = PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);\r | |
1767 | }\r | |
1768 | \r | |
1769 | PciIoDevice->Attributes &= (~Attributes);\r | |
1770 | Status = EFI_SUCCESS;\r | |
1771 | \r | |
1772 | }\r | |
1773 | \r | |
1774 | if (EFI_ERROR (Status)) {\r | |
250057b5 | 1775 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r |
1776 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
1777 | EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r | |
1778 | PciIoDevice->DevicePath\r | |
1779 | );\r | |
9060e3ec | 1780 | }\r |
1781 | \r | |
1782 | return Status;\r | |
1783 | }\r | |
1784 | \r | |
7b0a1ead RN |
1785 | /**\r |
1786 | Retrieve the AddrTranslationOffset from RootBridgeIo for the\r | |
1787 | specified range.\r | |
1788 | \r | |
1789 | @param RootBridgeIo Root Bridge IO instance.\r | |
1790 | @param AddrRangeMin The base address of the MMIO.\r | |
1791 | @param AddrLen The length of the MMIO.\r | |
1792 | \r | |
1793 | @retval The AddrTranslationOffset from RootBridgeIo for the \r | |
1794 | specified range, or (UINT64) -1 if the range is not\r | |
1795 | found in RootBridgeIo.\r | |
1796 | **/\r | |
1797 | UINT64\r | |
1798 | GetMmioAddressTranslationOffset (\r | |
1799 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo,\r | |
1800 | UINT64 AddrRangeMin,\r | |
1801 | UINT64 AddrLen\r | |
1802 | )\r | |
1803 | {\r | |
1804 | EFI_STATUS Status;\r | |
1805 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r | |
1806 | \r | |
1807 | Status = RootBridgeIo->Configuration (\r | |
1808 | RootBridgeIo,\r | |
1809 | (VOID **) &Configuration\r | |
1810 | );\r | |
1811 | if (EFI_ERROR (Status)) {\r | |
1812 | return (UINT64) -1;\r | |
1813 | }\r | |
1814 | \r | |
1815 | while (Configuration->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r | |
1816 | if ((Configuration->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) &&\r | |
1817 | (Configuration->AddrRangeMin <= AddrRangeMin) &&\r | |
1818 | (Configuration->AddrRangeMin + Configuration->AddrLen >= AddrRangeMin + AddrLen)\r | |
1819 | ) {\r | |
1820 | return Configuration->AddrTranslationOffset;\r | |
1821 | }\r | |
1822 | Configuration++;\r | |
1823 | }\r | |
1824 | \r | |
1825 | //\r | |
1826 | // The resource occupied by BAR should be in the range reported by RootBridge.\r | |
1827 | //\r | |
1828 | ASSERT (FALSE);\r | |
1829 | return (UINT64) -1;\r | |
1830 | }\r | |
1831 | \r | |
9060e3ec | 1832 | /**\r |
1833 | Gets the attributes that this PCI controller supports setting on a BAR using\r | |
1834 | SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r | |
1835 | \r | |
1836 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
1837 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
1838 | base address for resource range. The legal range for this field is 0..5.\r | |
1839 | @param Supports A pointer to the mask of attributes that this PCI controller supports\r | |
1840 | setting for this BAR with SetBarAttributes().\r | |
1841 | @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current\r | |
1842 | configuration of this BAR of the PCI controller.\r | |
1843 | \r | |
1844 | @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI\r | |
1845 | controller supports are returned in Supports. If Resources\r | |
1846 | is not NULL, then the ACPI 2.0 resource descriptors that the PCI\r | |
1847 | controller is currently using are returned in Resources.\r | |
1848 | @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r | |
1849 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
1850 | @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r | |
1851 | Resources.\r | |
1852 | \r | |
1853 | **/\r | |
1854 | EFI_STATUS\r | |
1855 | EFIAPI\r | |
1856 | PciIoGetBarAttributes (\r | |
1857 | IN EFI_PCI_IO_PROTOCOL * This,\r | |
1858 | IN UINT8 BarIndex,\r | |
1859 | OUT UINT64 *Supports, OPTIONAL\r | |
1860 | OUT VOID **Resources OPTIONAL\r | |
1861 | )\r | |
1862 | {\r | |
9060e3ec | 1863 | PCI_IO_DEVICE *PciIoDevice;\r |
46537499 | 1864 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r |
3bdb6d12 | 1865 | EFI_ACPI_END_TAG_DESCRIPTOR *End;\r |
9060e3ec | 1866 | \r |
1867 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
1868 | \r | |
1869 | if (Supports == NULL && Resources == NULL) {\r | |
1870 | return EFI_INVALID_PARAMETER;\r | |
1871 | }\r | |
1872 | \r | |
3bdb6d12 | 1873 | if ((BarIndex >= PCI_MAX_BAR) || (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown)) {\r |
9060e3ec | 1874 | return EFI_UNSUPPORTED;\r |
1875 | }\r | |
1876 | \r | |
1877 | //\r | |
1878 | // This driver does not support modifications to the WRITE_COMBINE or\r | |
1879 | // CACHED attributes for BAR ranges.\r | |
1880 | //\r | |
1881 | if (Supports != NULL) {\r | |
1882 | *Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;\r | |
1883 | }\r | |
1884 | \r | |
1885 | if (Resources != NULL) {\r | |
46537499 RN |
1886 | Descriptor = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r |
1887 | if (Descriptor == NULL) {\r | |
9060e3ec | 1888 | return EFI_OUT_OF_RESOURCES;\r |
1889 | }\r | |
1890 | \r | |
46537499 | 1891 | *Resources = Descriptor;\r |
9060e3ec | 1892 | \r |
46537499 RN |
1893 | Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r |
1894 | Descriptor->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r | |
1895 | Descriptor->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;\r | |
1896 | Descriptor->AddrLen = PciIoDevice->PciBar[BarIndex].Length;\r | |
1897 | Descriptor->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;\r | |
9060e3ec | 1898 | \r |
3bdb6d12 RN |
1899 | switch (PciIoDevice->PciBar[BarIndex].BarType) {\r |
1900 | case PciBarTypeIo16:\r | |
1901 | case PciBarTypeIo32:\r | |
1902 | //\r | |
1903 | // Io\r | |
1904 | //\r | |
46537499 | 1905 | Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r |
3bdb6d12 | 1906 | break;\r |
9060e3ec | 1907 | \r |
e90f51a8 | 1908 | case PciBarTypePMem32:\r |
3bdb6d12 | 1909 | //\r |
e90f51a8 | 1910 | // prefechable\r |
3bdb6d12 | 1911 | //\r |
e90f51a8 | 1912 | Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r |
3bdb6d12 | 1913 | //\r |
e90f51a8 | 1914 | // Fall through\r |
3bdb6d12 | 1915 | //\r |
e90f51a8 | 1916 | case PciBarTypeMem32:\r |
3bdb6d12 RN |
1917 | //\r |
1918 | // Mem\r | |
1919 | //\r | |
46537499 | 1920 | Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r |
3bdb6d12 | 1921 | //\r |
3bdb6d12 RN |
1922 | // 32 bit\r |
1923 | //\r | |
46537499 | 1924 | Descriptor->AddrSpaceGranularity = 32;\r |
3bdb6d12 | 1925 | break;\r |
9060e3ec | 1926 | \r |
e90f51a8 | 1927 | case PciBarTypePMem64:\r |
3bdb6d12 | 1928 | //\r |
e90f51a8 | 1929 | // prefechable\r |
3bdb6d12 | 1930 | //\r |
e90f51a8 | 1931 | Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r |
3bdb6d12 | 1932 | //\r |
e90f51a8 | 1933 | // Fall through\r |
3bdb6d12 | 1934 | //\r |
e90f51a8 | 1935 | case PciBarTypeMem64:\r |
3bdb6d12 RN |
1936 | //\r |
1937 | // Mem\r | |
1938 | //\r | |
46537499 | 1939 | Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r |
3bdb6d12 | 1940 | //\r |
3bdb6d12 RN |
1941 | // 64 bit\r |
1942 | //\r | |
46537499 | 1943 | Descriptor->AddrSpaceGranularity = 64;\r |
3bdb6d12 | 1944 | break;\r |
9060e3ec | 1945 | \r |
3bdb6d12 RN |
1946 | default:\r |
1947 | break;\r | |
9060e3ec | 1948 | }\r |
1949 | \r | |
1950 | //\r | |
1951 | // put the checksum\r | |
1952 | //\r | |
46537499 | 1953 | End = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Descriptor + 1);\r |
3bdb6d12 RN |
1954 | End->Desc = ACPI_END_TAG_DESCRIPTOR;\r |
1955 | End->Checksum = 0;\r | |
7b0a1ead RN |
1956 | \r |
1957 | //\r | |
1958 | // Get the Address Translation Offset\r | |
1959 | //\r | |
1960 | if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {\r | |
1961 | Descriptor->AddrTranslationOffset = GetMmioAddressTranslationOffset (\r | |
1962 | PciIoDevice->PciRootBridgeIo,\r | |
1963 | Descriptor->AddrRangeMin,\r | |
1964 | Descriptor->AddrLen\r | |
1965 | );\r | |
1966 | if (Descriptor->AddrTranslationOffset == (UINT64) -1) {\r | |
1967 | FreePool (Descriptor);\r | |
1968 | return EFI_UNSUPPORTED;\r | |
1969 | }\r | |
1970 | }\r | |
9060e3ec | 1971 | }\r |
1972 | \r | |
1973 | return EFI_SUCCESS;\r | |
1974 | }\r | |
1975 | \r | |
1976 | /**\r | |
1977 | Sets the attributes for a range of a BAR on a PCI controller.\r | |
1978 | \r | |
1979 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
1980 | @param Attributes The mask of attributes to set for the resource range specified by\r | |
1981 | BarIndex, Offset, and Length.\r | |
1982 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
1983 | base address for resource range. The legal range for this field is 0..5.\r | |
1984 | @param Offset A pointer to the BAR relative base address of the resource range to be\r | |
1985 | modified by the attributes specified by Attributes.\r | |
1986 | @param Length A pointer to the length of the resource range to be modified by the\r | |
1987 | attributes specified by Attributes.\r | |
1988 | \r | |
1989 | @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource\r | |
1990 | range specified by BarIndex, Offset, and Length were\r | |
1991 | set on the PCI controller, and the actual resource range is returned\r | |
1992 | in Offset and Length.\r | |
1993 | @retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r | |
1994 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
1995 | @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r | |
1996 | resource range specified by BarIndex, Offset, and\r | |
1997 | Length.\r | |
1998 | \r | |
1999 | **/\r | |
2000 | EFI_STATUS\r | |
2001 | EFIAPI\r | |
2002 | PciIoSetBarAttributes (\r | |
2003 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
2004 | IN UINT64 Attributes,\r | |
2005 | IN UINT8 BarIndex,\r | |
2006 | IN OUT UINT64 *Offset,\r | |
2007 | IN OUT UINT64 *Length\r | |
2008 | )\r | |
2009 | {\r | |
2010 | EFI_STATUS Status;\r | |
2011 | PCI_IO_DEVICE *PciIoDevice;\r | |
2012 | UINT64 NonRelativeOffset;\r | |
2013 | UINT64 Supports;\r | |
2014 | \r | |
2015 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
2016 | \r | |
2017 | //\r | |
2018 | // Make sure Offset and Length are not NULL\r | |
2019 | //\r | |
2020 | if (Offset == NULL || Length == NULL) {\r | |
2021 | return EFI_INVALID_PARAMETER;\r | |
2022 | }\r | |
2023 | \r | |
2024 | if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown) {\r | |
2025 | return EFI_UNSUPPORTED;\r | |
2026 | }\r | |
2027 | //\r | |
2028 | // This driver does not support setting the WRITE_COMBINE or the CACHED attributes.\r | |
2029 | // If Attributes is not 0, then return EFI_UNSUPPORTED.\r | |
2030 | //\r | |
2031 | Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;\r | |
2032 | \r | |
2033 | if (Attributes != (Attributes & Supports)) {\r | |
2034 | return EFI_UNSUPPORTED;\r | |
2035 | }\r | |
2036 | //\r | |
2037 | // Attributes must be supported. Make sure the BAR range describd by BarIndex, Offset, and\r | |
2038 | // Length are valid for this PCI device.\r | |
2039 | //\r | |
2040 | NonRelativeOffset = *Offset;\r | |
2041 | Status = PciIoVerifyBarAccess (\r | |
2042 | PciIoDevice,\r | |
2043 | BarIndex,\r | |
2044 | PciBarTypeMem,\r | |
2045 | EfiPciIoWidthUint8,\r | |
2046 | (UINT32) *Length,\r | |
2047 | &NonRelativeOffset\r | |
2048 | );\r | |
2049 | if (EFI_ERROR (Status)) {\r | |
2050 | return EFI_UNSUPPORTED;\r | |
2051 | }\r | |
2052 | \r | |
2053 | return EFI_SUCCESS;\r | |
2054 | }\r | |
2055 | \r | |
2056 | /**\r | |
2057 | Program parent bridge's attribute recurrently.\r | |
2058 | \r | |
2059 | @param PciIoDevice Child Pci device instance\r | |
2060 | @param Operation The operation to perform on the attributes for this PCI controller.\r | |
2061 | @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r | |
2062 | operations.\r | |
2063 | \r | |
2064 | @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r | |
2065 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
2066 | @retval EFI_UNSUPPORTED one or more of the bits set in\r | |
2067 | Attributes are not supported by this PCI controller or one of\r | |
2068 | its parent bridges when Operation is Set, Enable or Disable.\r | |
2069 | \r | |
2070 | **/\r | |
2071 | EFI_STATUS\r | |
2072 | UpStreamBridgesAttributes (\r | |
2073 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
2074 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r | |
2075 | IN UINT64 Attributes\r | |
2076 | )\r | |
2077 | {\r | |
2078 | PCI_IO_DEVICE *Parent;\r | |
2079 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
2080 | \r | |
2081 | Parent = PciIoDevice->Parent;\r | |
2082 | \r | |
2083 | while (Parent != NULL && IS_PCI_BRIDGE (&Parent->Pci)) {\r | |
2084 | \r | |
2085 | //\r | |
2086 | // Get the PciIo Protocol\r | |
2087 | //\r | |
2088 | PciIo = &Parent->PciIo;\r | |
2089 | \r | |
2090 | PciIo->Attributes (PciIo, Operation, Attributes, NULL);\r | |
2091 | \r | |
2092 | Parent = Parent->Parent;\r | |
2093 | }\r | |
2094 | \r | |
2095 | return EFI_SUCCESS;\r | |
2096 | }\r | |
2097 | \r | |
2098 | /**\r | |
2099 | Test whether two Pci devices has same parent bridge.\r | |
2100 | \r | |
2101 | @param PciDevice1 The first pci device for testing.\r | |
2102 | @param PciDevice2 The second pci device for testing.\r | |
2103 | \r | |
2104 | @retval TRUE Two Pci device has the same parent bridge.\r | |
2105 | @retval FALSE Two Pci device has not the same parent bridge.\r | |
2106 | \r | |
2107 | **/\r | |
2108 | BOOLEAN\r | |
2109 | PciDevicesOnTheSamePath (\r | |
2110 | IN PCI_IO_DEVICE *PciDevice1,\r | |
2111 | IN PCI_IO_DEVICE *PciDevice2\r | |
2112 | )\r | |
2113 | {\r | |
2114 | BOOLEAN Existed1;\r | |
2115 | BOOLEAN Existed2;\r | |
2116 | \r | |
2117 | if (PciDevice1->Parent == PciDevice2->Parent) {\r | |
2118 | return TRUE;\r | |
2119 | }\r | |
2120 | \r | |
2121 | Existed1 = PciDeviceExisted (PciDevice1->Parent, PciDevice2);\r | |
2122 | Existed2 = PciDeviceExisted (PciDevice2->Parent, PciDevice1);\r | |
2123 | \r | |
2124 | return (BOOLEAN) (Existed1 || Existed2);\r | |
2125 | }\r | |
2126 | \r |