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9060e3ec | 1 | /** @file\r |
2 | EFI PCI IO protocol functions implementation for PCI Bus module.\r | |
3 | \r | |
cd5ebaa0 HT |
4 | Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r |
5 | This program and the accompanying materials\r | |
9060e3ec | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include "PciBus.h"\r | |
16 | \r | |
17 | //\r | |
18 | // Pci Io Protocol Interface\r | |
19 | //\r | |
20 | EFI_PCI_IO_PROTOCOL mPciIoInterface = {\r | |
21 | PciIoPollMem,\r | |
22 | PciIoPollIo,\r | |
23 | {\r | |
24 | PciIoMemRead,\r | |
25 | PciIoMemWrite\r | |
26 | },\r | |
27 | {\r | |
28 | PciIoIoRead,\r | |
29 | PciIoIoWrite\r | |
30 | },\r | |
31 | {\r | |
32 | PciIoConfigRead,\r | |
33 | PciIoConfigWrite\r | |
34 | },\r | |
35 | PciIoCopyMem,\r | |
36 | PciIoMap,\r | |
37 | PciIoUnmap,\r | |
38 | PciIoAllocateBuffer,\r | |
39 | PciIoFreeBuffer,\r | |
40 | PciIoFlush,\r | |
41 | PciIoGetLocation,\r | |
42 | PciIoAttributes,\r | |
43 | PciIoGetBarAttributes,\r | |
44 | PciIoSetBarAttributes,\r | |
45 | 0,\r | |
46 | NULL\r | |
47 | };\r | |
48 | \r | |
49 | /**\r | |
50 | Report a error Status code of PCI bus driver controller.\r | |
51 | \r | |
52 | @param PciIoDevice Pci device instance.\r | |
53 | @param Code Status code value.\r | |
54 | \r | |
55 | **/\r | |
56 | EFI_STATUS\r | |
57 | ReportErrorStatusCode (\r | |
58 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
59 | IN EFI_STATUS_CODE_VALUE Code\r | |
60 | )\r | |
61 | {\r | |
62 | return REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r | |
63 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
64 | Code,\r | |
65 | PciIoDevice->DevicePath\r | |
66 | );\r | |
67 | }\r | |
68 | \r | |
69 | /**\r | |
70 | Initializes a PCI I/O Instance.\r | |
71 | \r | |
72 | @param PciIoDevice Pci device instance.\r | |
73 | \r | |
74 | **/\r | |
75 | VOID\r | |
76 | InitializePciIoInstance (\r | |
77 | IN PCI_IO_DEVICE *PciIoDevice\r | |
78 | )\r | |
79 | {\r | |
80 | CopyMem (&PciIoDevice->PciIo, &mPciIoInterface, sizeof (EFI_PCI_IO_PROTOCOL));\r | |
81 | }\r | |
82 | \r | |
83 | /**\r | |
84 | Verifies access to a PCI Base Address Register (BAR).\r | |
85 | \r | |
86 | @param PciIoDevice Pci device instance.\r | |
87 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
88 | base address for the memory or I/O operation to perform.\r | |
89 | @param Type Operation type could be memory or I/O.\r | |
90 | @param Width Signifies the width of the memory or I/O operations.\r | |
91 | @param Count The number of memory or I/O operations to perform.\r | |
92 | @param Offset The offset within the PCI configuration space for the PCI controller.\r | |
93 | \r | |
94 | @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.\r | |
95 | @retval EFI_SUCCESS Successfully verified.\r | |
96 | \r | |
97 | **/\r | |
98 | EFI_STATUS\r | |
99 | PciIoVerifyBarAccess (\r | |
100 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
101 | IN UINT8 BarIndex,\r | |
102 | IN PCI_BAR_TYPE Type,\r | |
103 | IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
104 | IN IN UINTN Count,\r | |
105 | IN UINT64 *Offset\r | |
106 | )\r | |
107 | {\r | |
108 | if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r | |
109 | return EFI_INVALID_PARAMETER;\r | |
110 | }\r | |
111 | \r | |
112 | if (BarIndex == EFI_PCI_IO_PASS_THROUGH_BAR) {\r | |
113 | return EFI_SUCCESS;\r | |
114 | }\r | |
115 | \r | |
116 | //\r | |
117 | // BarIndex 0-5 is legal\r | |
118 | //\r | |
119 | if (BarIndex >= PCI_MAX_BAR) {\r | |
120 | return EFI_INVALID_PARAMETER;\r | |
121 | }\r | |
122 | \r | |
123 | if (!CheckBarType (PciIoDevice, BarIndex, Type)) {\r | |
124 | return EFI_INVALID_PARAMETER;\r | |
125 | }\r | |
126 | \r | |
127 | //\r | |
128 | // If Width is EfiPciIoWidthFifoUintX then convert to EfiPciIoWidthUintX\r | |
129 | // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX\r | |
130 | //\r | |
815119f3 | 131 | if (Width >= EfiPciIoWidthFifoUint8 && Width <= EfiPciIoWidthFifoUint64) {\r |
9060e3ec | 132 | Count = 1;\r |
133 | }\r | |
134 | \r | |
135 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);\r | |
136 | \r | |
137 | if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PciIoDevice->PciBar[BarIndex].Length) {\r | |
138 | return EFI_INVALID_PARAMETER;\r | |
139 | }\r | |
140 | \r | |
141 | *Offset = *Offset + PciIoDevice->PciBar[BarIndex].BaseAddress;\r | |
142 | \r | |
143 | return EFI_SUCCESS;\r | |
144 | }\r | |
145 | \r | |
146 | /**\r | |
147 | Verifies access to a PCI Configuration Header.\r | |
148 | \r | |
149 | @param PciIoDevice Pci device instance.\r | |
150 | @param Width Signifies the width of the memory or I/O operations.\r | |
151 | @param Count The number of memory or I/O operations to perform.\r | |
152 | @param Offset The offset within the PCI configuration space for the PCI controller.\r | |
153 | \r | |
154 | @retval EFI_INVALID_PARAMETER Invalid Width\r | |
155 | @retval EFI_UNSUPPORTED Offset overflowed.\r | |
156 | @retval EFI_SUCCESS Successfully verified.\r | |
157 | \r | |
158 | **/\r | |
159 | EFI_STATUS\r | |
160 | PciIoVerifyConfigAccess (\r | |
161 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
162 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
163 | IN UINTN Count,\r | |
164 | IN UINT64 *Offset\r | |
165 | )\r | |
166 | {\r | |
167 | UINT64 ExtendOffset;\r | |
168 | \r | |
169 | if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r | |
170 | return EFI_INVALID_PARAMETER;\r | |
171 | }\r | |
172 | \r | |
173 | //\r | |
174 | // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX\r | |
175 | //\r | |
176 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);\r | |
177 | \r | |
178 | if (PciIoDevice->IsPciExp) {\r | |
179 | if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_EXP_MAX_CONFIG_OFFSET) {\r | |
180 | return EFI_UNSUPPORTED;\r | |
181 | }\r | |
182 | \r | |
183 | ExtendOffset = LShiftU64 (*Offset, 32);\r | |
184 | *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);\r | |
185 | *Offset = (*Offset) | ExtendOffset;\r | |
186 | \r | |
187 | } else {\r | |
188 | if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_MAX_CONFIG_OFFSET) {\r | |
189 | return EFI_UNSUPPORTED;\r | |
190 | }\r | |
191 | \r | |
192 | *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, *Offset);\r | |
193 | }\r | |
194 | \r | |
195 | return EFI_SUCCESS;\r | |
196 | }\r | |
197 | \r | |
198 | /**\r | |
199 | Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r | |
200 | satisfied or after a defined duration.\r | |
201 | \r | |
202 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
203 | @param Width Signifies the width of the memory or I/O operations.\r | |
204 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
205 | base address for the memory operation to perform.\r | |
206 | @param Offset The offset within the selected BAR to start the memory operation.\r | |
207 | @param Mask Mask used for the polling criteria.\r | |
208 | @param Value The comparison value used for the polling exit criteria.\r | |
209 | @param Delay The number of 100 ns units to poll.\r | |
210 | @param Result Pointer to the last value read from the memory location.\r | |
211 | \r | |
212 | @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r | |
213 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
214 | @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r | |
215 | @retval EFI_TIMEOUT Delay expired before a match occurred.\r | |
216 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
217 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
218 | \r | |
219 | **/\r | |
220 | EFI_STATUS\r | |
221 | EFIAPI\r | |
222 | PciIoPollMem (\r | |
223 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
224 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
225 | IN UINT8 BarIndex,\r | |
226 | IN UINT64 Offset,\r | |
227 | IN UINT64 Mask,\r | |
228 | IN UINT64 Value,\r | |
229 | IN UINT64 Delay,\r | |
230 | OUT UINT64 *Result\r | |
231 | )\r | |
232 | {\r | |
233 | EFI_STATUS Status;\r | |
234 | PCI_IO_DEVICE *PciIoDevice;\r | |
235 | \r | |
236 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
237 | \r | |
238 | if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r | |
239 | return EFI_INVALID_PARAMETER;\r | |
240 | }\r | |
241 | \r | |
242 | Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, 1, &Offset);\r | |
243 | if (EFI_ERROR (Status)) {\r | |
244 | return EFI_UNSUPPORTED;\r | |
245 | }\r | |
246 | \r | |
247 | if (Width > EfiPciIoWidthUint64) {\r | |
248 | return EFI_INVALID_PARAMETER;\r | |
249 | }\r | |
250 | \r | |
aeeb84ba | 251 | //\r |
252 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
253 | // \r | |
254 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
255 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
256 | Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);\r | |
257 | if (EFI_ERROR (Status)) {\r | |
258 | return Status;\r | |
259 | }\r | |
260 | if ((*Result & Mask) == Value || Delay == 0) {\r | |
261 | return EFI_SUCCESS;\r | |
262 | }\r | |
263 | do {\r | |
264 | //\r | |
265 | // Stall 10 us = 100 * 100ns\r | |
266 | //\r | |
267 | gBS->Stall (10);\r | |
268 | \r | |
269 | Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);\r | |
270 | if (EFI_ERROR (Status)) {\r | |
271 | return Status;\r | |
272 | }\r | |
273 | if ((*Result & Mask) == Value) {\r | |
274 | return EFI_SUCCESS;\r | |
275 | }\r | |
276 | if (Delay <= 100) {\r | |
277 | return EFI_TIMEOUT;\r | |
278 | }\r | |
279 | Delay -= 100;\r | |
280 | } while (TRUE);\r | |
281 | }\r | |
282 | }\r | |
283 | \r | |
9060e3ec | 284 | Status = PciIoDevice->PciRootBridgeIo->PollMem (\r |
285 | PciIoDevice->PciRootBridgeIo,\r | |
286 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
287 | Offset,\r | |
288 | Mask,\r | |
289 | Value,\r | |
290 | Delay,\r | |
291 | Result\r | |
292 | );\r | |
293 | \r | |
294 | if (EFI_ERROR (Status)) {\r | |
295 | ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r | |
296 | }\r | |
297 | \r | |
298 | return Status;\r | |
299 | }\r | |
300 | \r | |
301 | /**\r | |
302 | Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r | |
303 | satisfied or after a defined duration.\r | |
304 | \r | |
305 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
306 | @param Width Signifies the width of the memory or I/O operations.\r | |
307 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
308 | base address for the memory operation to perform.\r | |
309 | @param Offset The offset within the selected BAR to start the memory operation.\r | |
310 | @param Mask Mask used for the polling criteria.\r | |
311 | @param Value The comparison value used for the polling exit criteria.\r | |
312 | @param Delay The number of 100 ns units to poll.\r | |
313 | @param Result Pointer to the last value read from the memory location.\r | |
314 | \r | |
315 | @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r | |
316 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
317 | @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r | |
318 | @retval EFI_TIMEOUT Delay expired before a match occurred.\r | |
319 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
320 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
321 | \r | |
322 | **/\r | |
323 | EFI_STATUS\r | |
324 | EFIAPI\r | |
325 | PciIoPollIo (\r | |
326 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
327 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
328 | IN UINT8 BarIndex,\r | |
329 | IN UINT64 Offset,\r | |
330 | IN UINT64 Mask,\r | |
331 | IN UINT64 Value,\r | |
332 | IN UINT64 Delay,\r | |
333 | OUT UINT64 *Result\r | |
334 | )\r | |
335 | {\r | |
336 | EFI_STATUS Status;\r | |
337 | PCI_IO_DEVICE *PciIoDevice;\r | |
338 | \r | |
339 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
340 | \r | |
341 | if (Width < 0 || Width > EfiPciIoWidthUint64) {\r | |
342 | return EFI_INVALID_PARAMETER;\r | |
343 | }\r | |
344 | \r | |
345 | Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, 1, &Offset);\r | |
346 | if (EFI_ERROR (Status)) {\r | |
347 | return EFI_UNSUPPORTED;\r | |
348 | }\r | |
349 | \r | |
aeeb84ba | 350 | //\r |
351 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
352 | // \r | |
353 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
354 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
355 | Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);\r | |
356 | if (EFI_ERROR (Status)) {\r | |
357 | return Status;\r | |
358 | }\r | |
359 | if ((*Result & Mask) == Value || Delay == 0) {\r | |
360 | return EFI_SUCCESS;\r | |
361 | }\r | |
362 | do {\r | |
363 | //\r | |
364 | // Stall 10 us = 100 * 100ns\r | |
365 | //\r | |
366 | gBS->Stall (10);\r | |
367 | \r | |
368 | Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);\r | |
369 | if (EFI_ERROR (Status)) {\r | |
370 | return Status;\r | |
371 | }\r | |
372 | if ((*Result & Mask) == Value) {\r | |
373 | return EFI_SUCCESS;\r | |
374 | }\r | |
375 | if (Delay <= 100) {\r | |
376 | return EFI_TIMEOUT;\r | |
377 | }\r | |
378 | Delay -= 100;\r | |
379 | } while (TRUE);\r | |
380 | }\r | |
381 | }\r | |
382 | \r | |
9060e3ec | 383 | Status = PciIoDevice->PciRootBridgeIo->PollIo (\r |
384 | PciIoDevice->PciRootBridgeIo,\r | |
385 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
386 | Offset,\r | |
387 | Mask,\r | |
388 | Value,\r | |
389 | Delay,\r | |
390 | Result\r | |
391 | );\r | |
392 | \r | |
393 | if (EFI_ERROR (Status)) {\r | |
394 | ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r | |
395 | }\r | |
396 | \r | |
397 | return Status;\r | |
398 | }\r | |
399 | \r | |
400 | /**\r | |
401 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r | |
402 | \r | |
403 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
404 | @param Width Signifies the width of the memory or I/O operations.\r | |
405 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
406 | base address for the memory or I/O operation to perform.\r | |
407 | @param Offset The offset within the selected BAR to start the memory or I/O operation.\r | |
408 | @param Count The number of memory or I/O operations to perform.\r | |
409 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
410 | operations, the source buffer to write data from.\r | |
411 | \r | |
412 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
413 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
414 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
415 | valid for the PCI BAR specified by BarIndex.\r | |
416 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
417 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
418 | \r | |
419 | **/\r | |
420 | EFI_STATUS\r | |
421 | EFIAPI\r | |
422 | PciIoMemRead (\r | |
423 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
424 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
425 | IN UINT8 BarIndex,\r | |
426 | IN UINT64 Offset,\r | |
427 | IN UINTN Count,\r | |
428 | IN OUT VOID *Buffer\r | |
429 | )\r | |
430 | {\r | |
431 | EFI_STATUS Status;\r | |
432 | PCI_IO_DEVICE *PciIoDevice;\r | |
433 | \r | |
434 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
435 | \r | |
436 | if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r | |
437 | return EFI_INVALID_PARAMETER;\r | |
438 | }\r | |
439 | \r | |
440 | if (Buffer == NULL) {\r | |
441 | return EFI_INVALID_PARAMETER;\r | |
442 | }\r | |
443 | \r | |
444 | Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);\r | |
445 | if (EFI_ERROR (Status)) {\r | |
446 | return EFI_UNSUPPORTED;\r | |
447 | }\r | |
448 | \r | |
aeeb84ba | 449 | //\r |
450 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
451 | // \r | |
452 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
453 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
aeeb84ba | 454 | Count *= (UINTN)(1 << (Width & 0x03));\r |
c1450e16 | 455 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r |
aeeb84ba | 456 | }\r |
457 | } \r | |
458 | \r | |
459 | \r | |
9060e3ec | 460 | Status = PciIoDevice->PciRootBridgeIo->Mem.Read (\r |
461 | PciIoDevice->PciRootBridgeIo,\r | |
462 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
463 | Offset,\r | |
464 | Count,\r | |
465 | Buffer\r | |
466 | );\r | |
467 | \r | |
468 | if (EFI_ERROR (Status)) {\r | |
469 | ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);\r | |
470 | }\r | |
471 | \r | |
472 | return Status;\r | |
473 | }\r | |
474 | \r | |
475 | /**\r | |
476 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r | |
477 | \r | |
478 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
479 | @param Width Signifies the width of the memory or I/O operations.\r | |
480 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
481 | base address for the memory or I/O operation to perform.\r | |
482 | @param Offset The offset within the selected BAR to start the memory or I/O operation.\r | |
483 | @param Count The number of memory or I/O operations to perform.\r | |
484 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
485 | operations, the source buffer to write data from.\r | |
486 | \r | |
487 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
488 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
489 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
490 | valid for the PCI BAR specified by BarIndex.\r | |
491 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
492 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
493 | \r | |
494 | **/\r | |
495 | EFI_STATUS\r | |
496 | EFIAPI\r | |
497 | PciIoMemWrite (\r | |
498 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
499 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
500 | IN UINT8 BarIndex,\r | |
501 | IN UINT64 Offset,\r | |
502 | IN UINTN Count,\r | |
503 | IN OUT VOID *Buffer\r | |
504 | )\r | |
505 | {\r | |
506 | EFI_STATUS Status;\r | |
507 | PCI_IO_DEVICE *PciIoDevice;\r | |
508 | \r | |
509 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
510 | \r | |
511 | if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r | |
512 | return EFI_INVALID_PARAMETER;\r | |
513 | }\r | |
514 | \r | |
515 | if (Buffer == NULL) {\r | |
516 | return EFI_INVALID_PARAMETER;\r | |
517 | }\r | |
518 | \r | |
519 | Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);\r | |
520 | if (EFI_ERROR (Status)) {\r | |
521 | return EFI_UNSUPPORTED;\r | |
522 | }\r | |
523 | \r | |
aeeb84ba | 524 | //\r |
525 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
526 | // \r | |
527 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
528 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
aeeb84ba | 529 | Count *= (UINTN)(1 << (Width & 0x03));\r |
c1450e16 | 530 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r |
aeeb84ba | 531 | }\r |
532 | }\r | |
533 | \r | |
9060e3ec | 534 | Status = PciIoDevice->PciRootBridgeIo->Mem.Write (\r |
535 | PciIoDevice->PciRootBridgeIo,\r | |
536 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
537 | Offset,\r | |
538 | Count,\r | |
539 | Buffer\r | |
540 | );\r | |
541 | \r | |
542 | if (EFI_ERROR (Status)) {\r | |
543 | ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);\r | |
544 | }\r | |
545 | \r | |
546 | return Status;\r | |
547 | }\r | |
548 | \r | |
549 | /**\r | |
550 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r | |
551 | \r | |
552 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
553 | @param Width Signifies the width of the memory or I/O operations.\r | |
554 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
555 | base address for the memory or I/O operation to perform.\r | |
556 | @param Offset The offset within the selected BAR to start the memory or I/O operation.\r | |
557 | @param Count The number of memory or I/O operations to perform.\r | |
558 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
559 | operations, the source buffer to write data from.\r | |
560 | \r | |
561 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
562 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
563 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
564 | valid for the PCI BAR specified by BarIndex.\r | |
565 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
566 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
567 | \r | |
568 | **/\r | |
569 | EFI_STATUS\r | |
570 | EFIAPI\r | |
571 | PciIoIoRead (\r | |
572 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
573 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
574 | IN UINT8 BarIndex,\r | |
575 | IN UINT64 Offset,\r | |
576 | IN UINTN Count,\r | |
577 | IN OUT VOID *Buffer\r | |
578 | )\r | |
579 | {\r | |
580 | EFI_STATUS Status;\r | |
581 | PCI_IO_DEVICE *PciIoDevice;\r | |
582 | \r | |
583 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
584 | \r | |
585 | if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r | |
586 | return EFI_INVALID_PARAMETER;\r | |
587 | }\r | |
588 | \r | |
589 | if (Buffer == NULL) {\r | |
590 | return EFI_INVALID_PARAMETER;\r | |
591 | }\r | |
592 | \r | |
593 | Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);\r | |
594 | if (EFI_ERROR (Status)) {\r | |
595 | return EFI_UNSUPPORTED;\r | |
596 | }\r | |
597 | \r | |
aeeb84ba | 598 | //\r |
599 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
600 | // \r | |
601 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
602 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
aeeb84ba | 603 | Count *= (UINTN)(1 << (Width & 0x03));\r |
c1450e16 | 604 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r |
aeeb84ba | 605 | }\r |
606 | } \r | |
607 | \r | |
9060e3ec | 608 | Status = PciIoDevice->PciRootBridgeIo->Io.Read (\r |
609 | PciIoDevice->PciRootBridgeIo,\r | |
610 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
611 | Offset,\r | |
612 | Count,\r | |
613 | Buffer\r | |
614 | );\r | |
615 | \r | |
616 | if (EFI_ERROR (Status)) {\r | |
617 | ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);\r | |
618 | }\r | |
619 | \r | |
620 | return Status;\r | |
621 | }\r | |
622 | \r | |
623 | /**\r | |
624 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r | |
625 | \r | |
626 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
627 | @param Width Signifies the width of the memory or I/O operations.\r | |
628 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
629 | base address for the memory or I/O operation to perform.\r | |
630 | @param Offset The offset within the selected BAR to start the memory or I/O operation.\r | |
631 | @param Count The number of memory or I/O operations to perform.\r | |
632 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
633 | operations, the source buffer to write data from.\r | |
634 | \r | |
635 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
636 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
637 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
638 | valid for the PCI BAR specified by BarIndex.\r | |
639 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
640 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
641 | \r | |
642 | **/\r | |
643 | EFI_STATUS\r | |
644 | EFIAPI\r | |
645 | PciIoIoWrite (\r | |
646 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
647 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
648 | IN UINT8 BarIndex,\r | |
649 | IN UINT64 Offset,\r | |
650 | IN UINTN Count,\r | |
651 | IN OUT VOID *Buffer\r | |
652 | )\r | |
653 | {\r | |
654 | EFI_STATUS Status;\r | |
655 | PCI_IO_DEVICE *PciIoDevice;\r | |
656 | \r | |
657 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
658 | \r | |
659 | if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r | |
660 | return EFI_INVALID_PARAMETER;\r | |
661 | }\r | |
662 | \r | |
663 | if (Buffer == NULL) {\r | |
664 | return EFI_INVALID_PARAMETER;\r | |
665 | }\r | |
666 | \r | |
667 | Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);\r | |
668 | if (EFI_ERROR (Status)) {\r | |
669 | return EFI_UNSUPPORTED;\r | |
670 | }\r | |
671 | \r | |
aeeb84ba | 672 | //\r |
673 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
674 | // \r | |
675 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
676 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
aeeb84ba | 677 | Count *= (UINTN)(1 << (Width & 0x03));\r |
c1450e16 | 678 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r |
aeeb84ba | 679 | }\r |
680 | } \r | |
681 | \r | |
9060e3ec | 682 | Status = PciIoDevice->PciRootBridgeIo->Io.Write (\r |
683 | PciIoDevice->PciRootBridgeIo,\r | |
684 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
685 | Offset,\r | |
686 | Count,\r | |
687 | Buffer\r | |
688 | );\r | |
689 | \r | |
690 | if (EFI_ERROR (Status)) {\r | |
691 | ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);\r | |
692 | }\r | |
693 | \r | |
694 | return Status;\r | |
695 | }\r | |
696 | \r | |
697 | /**\r | |
698 | Enable a PCI driver to access PCI controller registers in PCI configuration space.\r | |
699 | \r | |
700 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
701 | @param Width Signifies the width of the memory operations.\r | |
702 | @param Offset The offset within the PCI configuration space for the PCI controller.\r | |
703 | @param Count The number of PCI configuration operations to perform.\r | |
704 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
705 | operations, the source buffer to write data from.\r | |
706 | \r | |
707 | \r | |
708 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
709 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
710 | valid for the PCI configuration header of the PCI controller.\r | |
711 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
712 | @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r | |
713 | \r | |
714 | **/\r | |
715 | EFI_STATUS\r | |
716 | EFIAPI\r | |
717 | PciIoConfigRead (\r | |
718 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
719 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
720 | IN UINT32 Offset,\r | |
721 | IN UINTN Count,\r | |
722 | IN OUT VOID *Buffer\r | |
723 | )\r | |
724 | {\r | |
725 | EFI_STATUS Status;\r | |
726 | PCI_IO_DEVICE *PciIoDevice;\r | |
727 | UINT64 Address;\r | |
728 | \r | |
729 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
730 | \r | |
731 | Address = Offset;\r | |
732 | Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);\r | |
733 | if (EFI_ERROR (Status)) {\r | |
734 | return Status;\r | |
735 | }\r | |
aeeb84ba | 736 | \r |
737 | //\r | |
738 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
739 | // \r | |
740 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
741 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
aeeb84ba | 742 | Count *= (UINTN)(1 << (Width & 0x03));\r |
c1450e16 | 743 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r |
aeeb84ba | 744 | }\r |
745 | } \r | |
9060e3ec | 746 | \r |
747 | Status = PciIoDevice->PciRootBridgeIo->Pci.Read (\r | |
748 | PciIoDevice->PciRootBridgeIo,\r | |
749 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
750 | Address,\r | |
751 | Count,\r | |
752 | Buffer\r | |
753 | );\r | |
754 | \r | |
755 | if (EFI_ERROR (Status)) {\r | |
756 | ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);\r | |
757 | }\r | |
758 | \r | |
759 | return Status;\r | |
760 | }\r | |
761 | \r | |
762 | /**\r | |
763 | Enable a PCI driver to access PCI controller registers in PCI configuration space.\r | |
764 | \r | |
765 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
766 | @param Width Signifies the width of the memory operations.\r | |
767 | @param Offset The offset within the PCI configuration space for the PCI controller.\r | |
768 | @param Count The number of PCI configuration operations to perform.\r | |
769 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
770 | operations, the source buffer to write data from.\r | |
771 | \r | |
772 | \r | |
773 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
774 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
775 | valid for the PCI configuration header of the PCI controller.\r | |
776 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
777 | @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r | |
778 | \r | |
779 | **/\r | |
780 | EFI_STATUS\r | |
781 | EFIAPI\r | |
782 | PciIoConfigWrite (\r | |
783 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
784 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
785 | IN UINT32 Offset,\r | |
786 | IN UINTN Count,\r | |
787 | IN OUT VOID *Buffer\r | |
788 | )\r | |
789 | {\r | |
790 | EFI_STATUS Status;\r | |
791 | PCI_IO_DEVICE *PciIoDevice;\r | |
792 | UINT64 Address;\r | |
793 | \r | |
794 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
795 | \r | |
796 | Address = Offset;\r | |
797 | Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);\r | |
798 | if (EFI_ERROR (Status)) {\r | |
799 | return Status;\r | |
800 | }\r | |
801 | \r | |
aeeb84ba | 802 | //\r |
803 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
804 | // \r | |
805 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
806 | if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
aeeb84ba | 807 | Count *= (UINTN)(1 << (Width & 0x03));\r |
c1450e16 | 808 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r |
aeeb84ba | 809 | }\r |
810 | } \r | |
811 | \r | |
9060e3ec | 812 | Status = PciIoDevice->PciRootBridgeIo->Pci.Write (\r |
813 | PciIoDevice->PciRootBridgeIo,\r | |
814 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
815 | Address,\r | |
816 | Count,\r | |
817 | Buffer\r | |
818 | );\r | |
819 | \r | |
820 | if (EFI_ERROR (Status)) {\r | |
821 | ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);\r | |
822 | }\r | |
823 | \r | |
824 | return Status;\r | |
825 | }\r | |
826 | \r | |
827 | /**\r | |
828 | Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r | |
829 | memory space.\r | |
830 | \r | |
831 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
832 | @param Width Signifies the width of the memory operations.\r | |
833 | @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r | |
834 | base address for the memory operation to perform.\r | |
835 | @param DestOffset The destination offset within the BAR specified by DestBarIndex to\r | |
836 | start the memory writes for the copy operation.\r | |
837 | @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r | |
838 | base address for the memory operation to perform.\r | |
839 | @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r | |
840 | the memory reads for the copy operation.\r | |
841 | @param Count The number of memory operations to perform. Bytes moved is Width\r | |
842 | size * Count, starting at DestOffset and SrcOffset.\r | |
843 | \r | |
844 | @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r | |
845 | @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r | |
846 | @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r | |
847 | @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r | |
848 | is not valid for the PCI BAR specified by DestBarIndex.\r | |
849 | @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r | |
850 | not valid for the PCI BAR specified by SrcBarIndex.\r | |
851 | @retval EFI_INVALID_PARAMETER Width is invalid.\r | |
852 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
853 | \r | |
854 | **/\r | |
855 | EFI_STATUS\r | |
856 | EFIAPI\r | |
857 | PciIoCopyMem (\r | |
858 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
859 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
860 | IN UINT8 DestBarIndex,\r | |
861 | IN UINT64 DestOffset,\r | |
862 | IN UINT8 SrcBarIndex,\r | |
863 | IN UINT64 SrcOffset,\r | |
864 | IN UINTN Count\r | |
865 | )\r | |
866 | {\r | |
867 | EFI_STATUS Status;\r | |
868 | PCI_IO_DEVICE *PciIoDevice;\r | |
869 | \r | |
870 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
871 | \r | |
872 | if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r | |
873 | return EFI_INVALID_PARAMETER;\r | |
874 | }\r | |
875 | \r | |
876 | if (Width == EfiPciIoWidthFifoUint8 ||\r | |
877 | Width == EfiPciIoWidthFifoUint16 ||\r | |
878 | Width == EfiPciIoWidthFifoUint32 ||\r | |
879 | Width == EfiPciIoWidthFifoUint64 ||\r | |
880 | Width == EfiPciIoWidthFillUint8 ||\r | |
881 | Width == EfiPciIoWidthFillUint16 ||\r | |
882 | Width == EfiPciIoWidthFillUint32 ||\r | |
883 | Width == EfiPciIoWidthFillUint64) {\r | |
884 | return EFI_INVALID_PARAMETER;\r | |
885 | }\r | |
886 | \r | |
887 | Status = PciIoVerifyBarAccess (PciIoDevice, DestBarIndex, PciBarTypeMem, Width, Count, &DestOffset);\r | |
888 | if (EFI_ERROR (Status)) {\r | |
889 | return EFI_UNSUPPORTED;\r | |
890 | }\r | |
891 | \r | |
892 | Status = PciIoVerifyBarAccess (PciIoDevice, SrcBarIndex, PciBarTypeMem, Width, Count, &SrcOffset);\r | |
893 | if (EFI_ERROR (Status)) {\r | |
894 | return EFI_UNSUPPORTED;\r | |
895 | }\r | |
896 | \r | |
aeeb84ba | 897 | //\r |
898 | // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r | |
899 | // \r | |
900 | if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r | |
901 | if ((SrcOffset & ((1 << (Width & 0x03)) - 1)) != 0 || (DestOffset & ((1 << (Width & 0x03)) - 1)) != 0) {\r | |
aeeb84ba | 902 | Count *= (UINTN)(1 << (Width & 0x03));\r |
c1450e16 | 903 | Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r |
aeeb84ba | 904 | }\r |
905 | } \r | |
906 | \r | |
9060e3ec | 907 | Status = PciIoDevice->PciRootBridgeIo->CopyMem (\r |
908 | PciIoDevice->PciRootBridgeIo,\r | |
909 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r | |
910 | DestOffset,\r | |
911 | SrcOffset,\r | |
912 | Count\r | |
913 | );\r | |
914 | \r | |
915 | if (EFI_ERROR (Status)) {\r | |
916 | ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r | |
917 | }\r | |
918 | \r | |
919 | return Status;\r | |
920 | }\r | |
921 | \r | |
922 | /**\r | |
923 | Provides the PCI controller-specific addresses needed to access system memory.\r | |
924 | \r | |
925 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
926 | @param Operation Indicates if the bus master is going to read or write to system memory.\r | |
927 | @param HostAddress The system memory address to map to the PCI controller.\r | |
928 | @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r | |
929 | that were mapped.\r | |
930 | @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r | |
931 | access the hosts HostAddress.\r | |
932 | @param Mapping A resulting value to pass to Unmap().\r | |
933 | \r | |
934 | @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r | |
935 | @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r | |
936 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
937 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
938 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r | |
939 | \r | |
940 | **/\r | |
941 | EFI_STATUS\r | |
942 | EFIAPI\r | |
943 | PciIoMap (\r | |
944 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
945 | IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r | |
946 | IN VOID *HostAddress,\r | |
947 | IN OUT UINTN *NumberOfBytes,\r | |
948 | OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r | |
949 | OUT VOID **Mapping\r | |
950 | )\r | |
951 | {\r | |
952 | EFI_STATUS Status;\r | |
953 | PCI_IO_DEVICE *PciIoDevice;\r | |
954 | \r | |
955 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
956 | \r | |
957 | if (Operation < 0 || Operation >= EfiPciIoOperationMaximum) {\r | |
958 | return EFI_INVALID_PARAMETER;\r | |
959 | }\r | |
960 | \r | |
961 | if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {\r | |
962 | return EFI_INVALID_PARAMETER;\r | |
963 | }\r | |
964 | \r | |
965 | if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {\r | |
966 | Operation = (EFI_PCI_IO_PROTOCOL_OPERATION) (Operation + EfiPciOperationBusMasterRead64);\r | |
967 | }\r | |
968 | \r | |
969 | Status = PciIoDevice->PciRootBridgeIo->Map (\r | |
970 | PciIoDevice->PciRootBridgeIo,\r | |
971 | (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) Operation,\r | |
972 | HostAddress,\r | |
973 | NumberOfBytes,\r | |
974 | DeviceAddress,\r | |
975 | Mapping\r | |
976 | );\r | |
977 | \r | |
978 | if (EFI_ERROR (Status)) {\r | |
979 | ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r | |
980 | }\r | |
981 | \r | |
982 | return Status;\r | |
983 | }\r | |
984 | \r | |
985 | /**\r | |
986 | Completes the Map() operation and releases any corresponding resources.\r | |
987 | \r | |
988 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
989 | @param Mapping The mapping value returned from Map().\r | |
990 | \r | |
991 | @retval EFI_SUCCESS The range was unmapped.\r | |
992 | @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r | |
993 | \r | |
994 | **/\r | |
995 | EFI_STATUS\r | |
996 | EFIAPI\r | |
997 | PciIoUnmap (\r | |
998 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
999 | IN VOID *Mapping\r | |
1000 | )\r | |
1001 | {\r | |
1002 | EFI_STATUS Status;\r | |
1003 | PCI_IO_DEVICE *PciIoDevice;\r | |
1004 | \r | |
1005 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
1006 | \r | |
1007 | Status = PciIoDevice->PciRootBridgeIo->Unmap (\r | |
1008 | PciIoDevice->PciRootBridgeIo,\r | |
1009 | Mapping\r | |
1010 | );\r | |
1011 | \r | |
1012 | if (EFI_ERROR (Status)) {\r | |
1013 | ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r | |
1014 | }\r | |
1015 | \r | |
1016 | return Status;\r | |
1017 | }\r | |
1018 | \r | |
1019 | /**\r | |
1020 | Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r | |
1021 | mapping.\r | |
1022 | \r | |
1023 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
1024 | @param Type This parameter is not used and must be ignored.\r | |
1025 | @param MemoryType The type of memory to allocate, EfiBootServicesData or\r | |
1026 | EfiRuntimeServicesData.\r | |
1027 | @param Pages The number of pages to allocate.\r | |
1028 | @param HostAddress A pointer to store the base system memory address of the\r | |
1029 | allocated range.\r | |
1030 | @param Attributes The requested bit mask of attributes for the allocated range.\r | |
1031 | \r | |
1032 | @retval EFI_SUCCESS The requested memory pages were allocated.\r | |
1033 | @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r | |
1034 | MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r | |
1035 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
1036 | @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r | |
1037 | \r | |
1038 | **/\r | |
1039 | EFI_STATUS\r | |
1040 | EFIAPI\r | |
1041 | PciIoAllocateBuffer (\r | |
1042 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
1043 | IN EFI_ALLOCATE_TYPE Type,\r | |
1044 | IN EFI_MEMORY_TYPE MemoryType,\r | |
1045 | IN UINTN Pages,\r | |
1046 | OUT VOID **HostAddress,\r | |
1047 | IN UINT64 Attributes\r | |
1048 | )\r | |
1049 | {\r | |
1050 | EFI_STATUS Status;\r | |
1051 | PCI_IO_DEVICE *PciIoDevice;\r | |
1052 | \r | |
1053 | if ((Attributes &\r | |
1054 | (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) != 0){\r | |
1055 | return EFI_UNSUPPORTED;\r | |
1056 | }\r | |
1057 | \r | |
1058 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
1059 | \r | |
1060 | if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {\r | |
1061 | Attributes |= EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE;\r | |
1062 | }\r | |
1063 | \r | |
1064 | Status = PciIoDevice->PciRootBridgeIo->AllocateBuffer (\r | |
1065 | PciIoDevice->PciRootBridgeIo,\r | |
1066 | Type,\r | |
1067 | MemoryType,\r | |
1068 | Pages,\r | |
1069 | HostAddress,\r | |
1070 | Attributes\r | |
1071 | );\r | |
1072 | \r | |
1073 | if (EFI_ERROR (Status)) {\r | |
1074 | ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r | |
1075 | }\r | |
1076 | \r | |
1077 | return Status;\r | |
1078 | }\r | |
1079 | \r | |
1080 | /**\r | |
1081 | Frees memory that was allocated with AllocateBuffer().\r | |
1082 | \r | |
1083 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
1084 | @param Pages The number of pages to free.\r | |
1085 | @param HostAddress The base system memory address of the allocated range.\r | |
1086 | \r | |
1087 | @retval EFI_SUCCESS The requested memory pages were freed.\r | |
1088 | @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r | |
1089 | was not allocated with AllocateBuffer().\r | |
1090 | \r | |
1091 | **/\r | |
1092 | EFI_STATUS\r | |
1093 | EFIAPI\r | |
1094 | PciIoFreeBuffer (\r | |
1095 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
1096 | IN UINTN Pages,\r | |
1097 | IN VOID *HostAddress\r | |
1098 | )\r | |
1099 | {\r | |
1100 | EFI_STATUS Status;\r | |
1101 | PCI_IO_DEVICE *PciIoDevice;\r | |
1102 | \r | |
1103 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
1104 | \r | |
1105 | Status = PciIoDevice->PciRootBridgeIo->FreeBuffer (\r | |
1106 | PciIoDevice->PciRootBridgeIo,\r | |
1107 | Pages,\r | |
1108 | HostAddress\r | |
1109 | );\r | |
1110 | \r | |
1111 | if (EFI_ERROR (Status)) {\r | |
1112 | ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r | |
1113 | }\r | |
1114 | \r | |
1115 | return Status;\r | |
1116 | }\r | |
1117 | \r | |
1118 | /**\r | |
1119 | Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r | |
1120 | \r | |
1121 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
1122 | \r | |
1123 | @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r | |
1124 | bridge to system memory.\r | |
1125 | @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r | |
1126 | host bridge due to a hardware error.\r | |
1127 | \r | |
1128 | **/\r | |
1129 | EFI_STATUS\r | |
1130 | EFIAPI\r | |
1131 | PciIoFlush (\r | |
1132 | IN EFI_PCI_IO_PROTOCOL *This\r | |
1133 | )\r | |
1134 | {\r | |
1135 | EFI_STATUS Status;\r | |
1136 | PCI_IO_DEVICE *PciIoDevice;\r | |
1137 | \r | |
1138 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
1139 | \r | |
1140 | Status = PciIoDevice->PciRootBridgeIo->Flush (\r | |
1141 | PciIoDevice->PciRootBridgeIo\r | |
1142 | );\r | |
1143 | if (EFI_ERROR (Status)) {\r | |
1144 | ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r | |
1145 | }\r | |
1146 | \r | |
1147 | return Status;\r | |
1148 | }\r | |
1149 | \r | |
1150 | /**\r | |
1151 | Retrieves this PCI controller's current PCI bus number, device number, and function number.\r | |
1152 | \r | |
1153 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
1154 | @param SegmentNumber The PCI controller's current PCI segment number.\r | |
1155 | @param BusNumber The PCI controller's current PCI bus number.\r | |
1156 | @param DeviceNumber The PCI controller's current PCI device number.\r | |
1157 | @param FunctionNumber The PCI controller's current PCI function number.\r | |
1158 | \r | |
1159 | @retval EFI_SUCCESS The PCI controller location was returned.\r | |
1160 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
1161 | \r | |
1162 | **/\r | |
1163 | EFI_STATUS\r | |
1164 | EFIAPI\r | |
1165 | PciIoGetLocation (\r | |
1166 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
1167 | OUT UINTN *Segment,\r | |
1168 | OUT UINTN *Bus,\r | |
1169 | OUT UINTN *Device,\r | |
1170 | OUT UINTN *Function\r | |
1171 | )\r | |
1172 | {\r | |
1173 | PCI_IO_DEVICE *PciIoDevice;\r | |
1174 | \r | |
1175 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
1176 | \r | |
1177 | if (Segment == NULL || Bus == NULL || Device == NULL || Function == NULL) {\r | |
1178 | return EFI_INVALID_PARAMETER;\r | |
1179 | }\r | |
1180 | \r | |
1181 | *Segment = PciIoDevice->PciRootBridgeIo->SegmentNumber;\r | |
1182 | *Bus = PciIoDevice->BusNumber;\r | |
1183 | *Device = PciIoDevice->DeviceNumber;\r | |
1184 | *Function = PciIoDevice->FunctionNumber;\r | |
1185 | \r | |
1186 | return EFI_SUCCESS;\r | |
1187 | }\r | |
1188 | \r | |
1189 | /**\r | |
1190 | Check BAR type for PCI resource.\r | |
1191 | \r | |
1192 | @param PciIoDevice PCI device instance.\r | |
1193 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
1194 | base address for the memory or I/O operation to perform.\r | |
1195 | @param BarType Memory or I/O.\r | |
1196 | \r | |
1197 | @retval TRUE Pci device's bar type is same with input BarType.\r | |
1198 | @retval TRUE Pci device's bar type is not same with input BarType.\r | |
1199 | \r | |
1200 | **/\r | |
1201 | BOOLEAN\r | |
1202 | CheckBarType (\r | |
1203 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
1204 | IN UINT8 BarIndex,\r | |
1205 | IN PCI_BAR_TYPE BarType\r | |
1206 | )\r | |
1207 | {\r | |
1208 | switch (BarType) {\r | |
1209 | \r | |
1210 | case PciBarTypeMem:\r | |
1211 | \r | |
1212 | if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem32 &&\r | |
1213 | PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem32 &&\r | |
1214 | PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem64 &&\r | |
1215 | PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem64 ) {\r | |
1216 | return FALSE;\r | |
1217 | }\r | |
1218 | \r | |
1219 | return TRUE;\r | |
1220 | \r | |
1221 | case PciBarTypeIo:\r | |
1222 | if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo32 &&\r | |
1223 | PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo16){\r | |
1224 | return FALSE;\r | |
1225 | }\r | |
1226 | \r | |
1227 | return TRUE;\r | |
1228 | \r | |
1229 | default:\r | |
1230 | break;\r | |
1231 | }\r | |
1232 | \r | |
1233 | return FALSE;\r | |
1234 | }\r | |
1235 | \r | |
1236 | /**\r | |
1237 | Set/Disable new attributes to a Root Bridge.\r | |
1238 | \r | |
1239 | @param PciIoDevice Pci device instance.\r | |
1240 | @param Attributes New attribute want to be set.\r | |
1241 | @param Operation Set or Disable.\r | |
1242 | \r | |
1243 | @retval EFI_UNSUPPORTED If root bridge does not support change attribute.\r | |
1244 | @retval EFI_SUCCESS Successfully set new attributs.\r | |
1245 | \r | |
1246 | **/\r | |
1247 | EFI_STATUS\r | |
1248 | ModifyRootBridgeAttributes (\r | |
1249 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
1250 | IN UINT64 Attributes,\r | |
1251 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r | |
1252 | )\r | |
1253 | {\r | |
1254 | UINT64 PciRootBridgeSupports;\r | |
1255 | UINT64 PciRootBridgeAttributes;\r | |
1256 | UINT64 NewPciRootBridgeAttributes;\r | |
1257 | EFI_STATUS Status;\r | |
1258 | \r | |
1259 | //\r | |
1260 | // Get the current attributes of this PCI device's PCI Root Bridge\r | |
1261 | //\r | |
1262 | Status = PciIoDevice->PciRootBridgeIo->GetAttributes (\r | |
1263 | PciIoDevice->PciRootBridgeIo,\r | |
1264 | &PciRootBridgeSupports,\r | |
1265 | &PciRootBridgeAttributes\r | |
1266 | );\r | |
1267 | if (EFI_ERROR (Status)) {\r | |
1268 | return EFI_UNSUPPORTED;\r | |
1269 | }\r | |
1270 | \r | |
1271 | //\r | |
1272 | // Record the new attribute of the Root Bridge\r | |
1273 | //\r | |
1274 | if (Operation == EfiPciIoAttributeOperationEnable) {\r | |
1275 | NewPciRootBridgeAttributes = PciRootBridgeAttributes | Attributes;\r | |
1276 | } else {\r | |
1277 | NewPciRootBridgeAttributes = PciRootBridgeAttributes & (~Attributes);\r | |
1278 | }\r | |
1279 | \r | |
1280 | //\r | |
1281 | // Call the PCI Root Bridge to attempt to modify the attributes\r | |
1282 | //\r | |
1283 | if ((NewPciRootBridgeAttributes ^ PciRootBridgeAttributes) != 0) {\r | |
1284 | \r | |
1285 | Status = PciIoDevice->PciRootBridgeIo->SetAttributes (\r | |
1286 | PciIoDevice->PciRootBridgeIo,\r | |
1287 | NewPciRootBridgeAttributes,\r | |
1288 | NULL,\r | |
1289 | NULL\r | |
1290 | );\r | |
1291 | if (EFI_ERROR (Status)) {\r | |
1292 | //\r | |
1293 | // The PCI Root Bridge could not modify the attributes, so return the error.\r | |
1294 | //\r | |
1295 | return EFI_UNSUPPORTED;\r | |
1296 | }\r | |
1297 | }\r | |
1298 | \r | |
1299 | //\r | |
1300 | // Also update the attributes for this Root Bridge structure\r | |
1301 | //\r | |
1302 | PciIoDevice->Attributes = NewPciRootBridgeAttributes;\r | |
1303 | \r | |
1304 | return EFI_SUCCESS;\r | |
1305 | }\r | |
1306 | \r | |
1307 | /**\r | |
1308 | Check whether this device can be enable/disable to snoop.\r | |
1309 | \r | |
1310 | @param PciIoDevice Pci device instance.\r | |
1311 | @param Operation Enable/Disable.\r | |
1312 | \r | |
1313 | @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop.\r | |
1314 | @retval EFI_SUCCESS Snoop can be supported.\r | |
1315 | \r | |
1316 | **/\r | |
1317 | EFI_STATUS\r | |
1318 | SupportPaletteSnoopAttributes (\r | |
1319 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
1320 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r | |
1321 | )\r | |
1322 | {\r | |
1323 | PCI_IO_DEVICE *Temp;\r | |
1324 | UINT16 VGACommand;\r | |
1325 | \r | |
1326 | //\r | |
1327 | // Snoop attribute can be only modified by GFX\r | |
1328 | //\r | |
1329 | if (!IS_PCI_GFX (&PciIoDevice->Pci)) {\r | |
1330 | return EFI_UNSUPPORTED;\r | |
1331 | }\r | |
1332 | \r | |
1333 | //\r | |
1334 | // Get the boot VGA on the same segement\r | |
1335 | //\r | |
1336 | Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);\r | |
1337 | \r | |
1338 | if (Temp == NULL) {\r | |
1339 | //\r | |
1340 | // If there is no VGA device on the segement, set\r | |
1341 | // this graphics card to decode the palette range\r | |
1342 | //\r | |
1343 | return EFI_SUCCESS;\r | |
1344 | }\r | |
1345 | \r | |
1346 | //\r | |
1347 | // Check these two agents are on the same path\r | |
1348 | //\r | |
1349 | if (!PciDevicesOnTheSamePath (Temp, PciIoDevice)) {\r | |
1350 | //\r | |
1351 | // they are not on the same path, so snoop can be enabled or disabled\r | |
1352 | //\r | |
1353 | return EFI_SUCCESS;\r | |
1354 | }\r | |
1355 | //\r | |
1356 | // Check if they are on the same bus\r | |
1357 | //\r | |
1358 | if (Temp->Parent == PciIoDevice->Parent) {\r | |
1359 | \r | |
1360 | PCI_READ_COMMAND_REGISTER (Temp, &VGACommand);\r | |
1361 | \r | |
1362 | //\r | |
1363 | // If they are on the same bus, either one can\r | |
1364 | // be set to snoop, the other set to decode\r | |
1365 | //\r | |
1366 | if ((VGACommand & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {\r | |
1367 | //\r | |
1368 | // VGA has set to snoop, so GFX can be only set to disable snoop\r | |
1369 | //\r | |
1370 | if (Operation == EfiPciIoAttributeOperationEnable) {\r | |
1371 | return EFI_UNSUPPORTED;\r | |
1372 | }\r | |
1373 | } else {\r | |
1374 | //\r | |
1375 | // VGA has disabled to snoop, so GFX can be only enabled\r | |
1376 | //\r | |
1377 | if (Operation == EfiPciIoAttributeOperationDisable) {\r | |
1378 | return EFI_UNSUPPORTED;\r | |
1379 | }\r | |
1380 | }\r | |
1381 | \r | |
1382 | return EFI_SUCCESS;\r | |
1383 | }\r | |
1384 | \r | |
1385 | //\r | |
1386 | // If they are on the same path but on the different bus\r | |
1387 | // The first agent is set to snoop, the second one set to\r | |
1388 | // decode\r | |
1389 | //\r | |
1390 | \r | |
1391 | if (Temp->BusNumber < PciIoDevice->BusNumber) {\r | |
1392 | //\r | |
1393 | // GFX should be set to decode\r | |
1394 | //\r | |
1395 | if (Operation == EfiPciIoAttributeOperationDisable) {\r | |
1396 | PCI_ENABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r | |
1397 | Temp->Attributes |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;\r | |
1398 | } else {\r | |
1399 | return EFI_UNSUPPORTED;\r | |
1400 | }\r | |
1401 | \r | |
1402 | } else {\r | |
1403 | //\r | |
1404 | // GFX should be set to snoop\r | |
1405 | //\r | |
1406 | if (Operation == EfiPciIoAttributeOperationEnable) {\r | |
1407 | PCI_DISABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r | |
1408 | Temp->Attributes &= (~EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r | |
1409 | } else {\r | |
1410 | return EFI_UNSUPPORTED;\r | |
1411 | }\r | |
1412 | \r | |
1413 | }\r | |
1414 | \r | |
1415 | return EFI_SUCCESS;\r | |
1416 | }\r | |
1417 | \r | |
1418 | /**\r | |
1419 | Performs an operation on the attributes that this PCI controller supports. The operations include\r | |
1420 | getting the set of supported attributes, retrieving the current attributes, setting the current\r | |
1421 | attributes, enabling attributes, and disabling attributes.\r | |
1422 | \r | |
1423 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
1424 | @param Operation The operation to perform on the attributes for this PCI controller.\r | |
1425 | @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r | |
1426 | operations.\r | |
1427 | @param Result A pointer to the result mask of attributes that are returned for the Get\r | |
1428 | and Supported operations.\r | |
1429 | \r | |
1430 | @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r | |
1431 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
1432 | @retval EFI_UNSUPPORTED one or more of the bits set in\r | |
1433 | Attributes are not supported by this PCI controller or one of\r | |
1434 | its parent bridges when Operation is Set, Enable or Disable.\r | |
1435 | \r | |
1436 | **/\r | |
1437 | EFI_STATUS\r | |
1438 | EFIAPI\r | |
1439 | PciIoAttributes (\r | |
1440 | IN EFI_PCI_IO_PROTOCOL * This,\r | |
1441 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r | |
1442 | IN UINT64 Attributes,\r | |
1443 | OUT UINT64 *Result OPTIONAL\r | |
1444 | )\r | |
1445 | {\r | |
1446 | EFI_STATUS Status;\r | |
1447 | \r | |
1448 | PCI_IO_DEVICE *PciIoDevice;\r | |
1449 | PCI_IO_DEVICE *UpStreamBridge;\r | |
1450 | PCI_IO_DEVICE *Temp;\r | |
1451 | \r | |
1452 | UINT64 Supports;\r | |
1453 | UINT64 UpStreamAttributes;\r | |
1454 | UINT16 BridgeControl;\r | |
1455 | UINT16 Command;\r | |
1456 | \r | |
1457 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
1458 | \r | |
1459 | switch (Operation) {\r | |
1460 | case EfiPciIoAttributeOperationGet:\r | |
1461 | if (Result == NULL) {\r | |
1462 | return EFI_INVALID_PARAMETER;\r | |
1463 | }\r | |
1464 | \r | |
1465 | *Result = PciIoDevice->Attributes;\r | |
1466 | return EFI_SUCCESS;\r | |
1467 | \r | |
1468 | case EfiPciIoAttributeOperationSupported:\r | |
1469 | if (Result == NULL) {\r | |
1470 | return EFI_INVALID_PARAMETER;\r | |
1471 | }\r | |
1472 | \r | |
1473 | *Result = PciIoDevice->Supports;\r | |
1474 | return EFI_SUCCESS;\r | |
1475 | \r | |
1476 | case EfiPciIoAttributeOperationSet:\r | |
1477 | Status = PciIoDevice->PciIo.Attributes (\r | |
1478 | &(PciIoDevice->PciIo),\r | |
1479 | EfiPciIoAttributeOperationEnable,\r | |
1480 | Attributes,\r | |
1481 | NULL\r | |
1482 | );\r | |
1483 | if (EFI_ERROR (Status)) {\r | |
1484 | return EFI_UNSUPPORTED;\r | |
1485 | }\r | |
1486 | \r | |
1487 | Status = PciIoDevice->PciIo.Attributes (\r | |
1488 | &(PciIoDevice->PciIo),\r | |
1489 | EfiPciIoAttributeOperationDisable,\r | |
1490 | (~Attributes) & (PciIoDevice->Supports),\r | |
1491 | NULL\r | |
1492 | );\r | |
1493 | if (EFI_ERROR (Status)) {\r | |
1494 | return EFI_UNSUPPORTED;\r | |
1495 | }\r | |
1496 | \r | |
1497 | return EFI_SUCCESS;\r | |
1498 | \r | |
1499 | case EfiPciIoAttributeOperationEnable:\r | |
1500 | case EfiPciIoAttributeOperationDisable:\r | |
1501 | break;\r | |
1502 | \r | |
1503 | default:\r | |
1504 | return EFI_INVALID_PARAMETER;\r | |
1505 | }\r | |
1506 | //\r | |
1507 | // Just a trick for ENABLE attribute\r | |
1508 | // EFI_PCI_DEVICE_ENABLE is not defined in UEFI spec, which is the internal usage.\r | |
1509 | // So, this logic doesn't confrom to UEFI spec, which should be removed.\r | |
1510 | // But this trick logic is still kept for some binary drivers that depend on it.\r | |
1511 | //\r | |
1512 | if ((Attributes & EFI_PCI_DEVICE_ENABLE) == EFI_PCI_DEVICE_ENABLE) {\r | |
1513 | Attributes &= (PciIoDevice->Supports);\r | |
1514 | \r | |
1515 | //\r | |
1516 | // Raise the EFI_P_PC_ENABLE Status code\r | |
1517 | //\r | |
1518 | REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r | |
1519 | EFI_PROGRESS_CODE,\r | |
1520 | EFI_IO_BUS_PCI | EFI_P_PC_ENABLE,\r | |
1521 | PciIoDevice->DevicePath\r | |
1522 | );\r | |
1523 | }\r | |
1524 | \r | |
1525 | //\r | |
1526 | // If no attributes can be supported, then return.\r | |
1527 | // Otherwise, set the attributes that it can support.\r | |
1528 | //\r | |
1529 | Supports = (PciIoDevice->Supports) & Attributes;\r | |
1530 | if (Supports != Attributes) {\r | |
1531 | return EFI_UNSUPPORTED;\r | |
1532 | }\r | |
1533 | \r | |
1534 | //\r | |
1535 | // For Root Bridge, just call RootBridgeIo to set attributes;\r | |
1536 | //\r | |
1537 | if (PciIoDevice->Parent == NULL) {\r | |
1538 | Status = ModifyRootBridgeAttributes (PciIoDevice, Attributes, Operation);\r | |
1539 | return Status;\r | |
1540 | }\r | |
1541 | \r | |
1542 | Command = 0;\r | |
1543 | BridgeControl = 0;\r | |
1544 | \r | |
1545 | //\r | |
1546 | // Check VGA and VGA16, they can not be set at the same time\r | |
1547 | //\r | |
1548 | if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&\r | |
1549 | (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||\r | |
1550 | ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&\r | |
1551 | (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ||\r | |
1552 | ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&\r | |
1553 | (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||\r | |
1554 | ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&\r | |
1555 | (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ) {\r | |
1556 | return EFI_UNSUPPORTED;\r | |
1557 | }\r | |
1558 | \r | |
1559 | //\r | |
1560 | // For PPB & P2C, set relevant attribute bits\r | |
1561 | //\r | |
1562 | if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r | |
1563 | \r | |
1564 | if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {\r | |
1565 | BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA;\r | |
1566 | }\r | |
1567 | \r | |
1568 | if ((Attributes & EFI_PCI_IO_ATTRIBUTE_ISA_IO) != 0) {\r | |
1569 | BridgeControl |= EFI_PCI_BRIDGE_CONTROL_ISA;\r | |
1570 | }\r | |
1571 | \r | |
1572 | if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {\r | |
1573 | Command |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;\r | |
1574 | }\r | |
1575 | \r | |
1576 | if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {\r | |
1577 | BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA_16;\r | |
1578 | }\r | |
1579 | \r | |
1580 | } else {\r | |
1581 | //\r | |
1582 | // Do with the attributes on VGA\r | |
1583 | // Only for VGA's legacy resource, we just can enable once.\r | |
1584 | //\r | |
1585 | if ((Attributes &\r | |
1586 | (EFI_PCI_IO_ATTRIBUTE_VGA_IO |\r | |
1587 | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 |\r | |
1588 | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY)) != 0) {\r | |
1589 | //\r | |
1590 | // Check if a VGA has been enabled before enabling a new one\r | |
1591 | //\r | |
1592 | if (Operation == EfiPciIoAttributeOperationEnable) {\r | |
1593 | //\r | |
1594 | // Check if there have been an active VGA device on the same segment\r | |
1595 | //\r | |
1596 | Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);\r | |
1597 | if (Temp != NULL && Temp != PciIoDevice) {\r | |
1598 | //\r | |
1599 | // An active VGA has been detected, so can not enable another\r | |
1600 | //\r | |
1601 | return EFI_UNSUPPORTED;\r | |
1602 | }\r | |
1603 | }\r | |
1604 | }\r | |
1605 | \r | |
1606 | //\r | |
1607 | // Do with the attributes on GFX\r | |
1608 | //\r | |
1609 | if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {\r | |
1610 | \r | |
1611 | if (Operation == EfiPciIoAttributeOperationEnable) {\r | |
1612 | //\r | |
1613 | // Check if snoop can be enabled in current configuration\r | |
1614 | //\r | |
1615 | Status = SupportPaletteSnoopAttributes (PciIoDevice, Operation);\r | |
1616 | \r | |
1617 | if (EFI_ERROR (Status)) {\r | |
1618 | \r | |
1619 | //\r | |
1620 | // Enable operation is forbidden, so mask the bit in attributes\r | |
1621 | // so as to keep consistent with the actual Status\r | |
1622 | //\r | |
1623 | // Attributes &= (~EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO);\r | |
1624 | //\r | |
1625 | //\r | |
1626 | //\r | |
1627 | return EFI_UNSUPPORTED;\r | |
1628 | \r | |
1629 | }\r | |
1630 | }\r | |
1631 | \r | |
1632 | //\r | |
1633 | // It can be supported, so get ready to set the bit\r | |
1634 | //\r | |
1635 | Command |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;\r | |
1636 | }\r | |
1637 | }\r | |
1638 | \r | |
1639 | if ((Attributes & EFI_PCI_IO_ATTRIBUTE_IO) != 0) {\r | |
1640 | Command |= EFI_PCI_COMMAND_IO_SPACE;\r | |
1641 | }\r | |
1642 | \r | |
1643 | if ((Attributes & EFI_PCI_IO_ATTRIBUTE_MEMORY) != 0) {\r | |
1644 | Command |= EFI_PCI_COMMAND_MEMORY_SPACE;\r | |
1645 | }\r | |
1646 | \r | |
1647 | if ((Attributes & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) != 0) {\r | |
1648 | Command |= EFI_PCI_COMMAND_BUS_MASTER;\r | |
1649 | }\r | |
1650 | //\r | |
1651 | // The upstream bridge should be also set to revelant attribute\r | |
1652 | // expect for IO, Mem and BusMaster\r | |
1653 | //\r | |
1654 | UpStreamAttributes = Attributes &\r | |
1655 | (~(EFI_PCI_IO_ATTRIBUTE_IO |\r | |
1656 | EFI_PCI_IO_ATTRIBUTE_MEMORY |\r | |
1657 | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER\r | |
1658 | )\r | |
1659 | );\r | |
1660 | UpStreamBridge = PciIoDevice->Parent;\r | |
1661 | \r | |
1662 | if (Operation == EfiPciIoAttributeOperationEnable) {\r | |
1663 | //\r | |
1664 | // Enable relevant attributes to command register and bridge control register\r | |
1665 | //\r | |
1666 | Status = PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, Command);\r | |
1667 | if (BridgeControl != 0) {\r | |
1668 | Status = PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);\r | |
1669 | }\r | |
1670 | \r | |
1671 | PciIoDevice->Attributes |= Attributes;\r | |
1672 | \r | |
1673 | //\r | |
1674 | // Enable attributes of the upstream bridge\r | |
1675 | //\r | |
1676 | Status = UpStreamBridge->PciIo.Attributes (\r | |
1677 | &(UpStreamBridge->PciIo),\r | |
1678 | EfiPciIoAttributeOperationEnable,\r | |
1679 | UpStreamAttributes,\r | |
1680 | NULL\r | |
1681 | );\r | |
1682 | } else {\r | |
1683 | \r | |
1684 | //\r | |
1685 | // Disable relevant attributes to command register and bridge control register\r | |
1686 | //\r | |
1687 | Status = PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, Command);\r | |
1688 | if (BridgeControl != 0) {\r | |
1689 | Status = PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);\r | |
1690 | }\r | |
1691 | \r | |
1692 | PciIoDevice->Attributes &= (~Attributes);\r | |
1693 | Status = EFI_SUCCESS;\r | |
1694 | \r | |
1695 | }\r | |
1696 | \r | |
1697 | if (EFI_ERROR (Status)) {\r | |
1698 | ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r | |
1699 | }\r | |
1700 | \r | |
1701 | return Status;\r | |
1702 | }\r | |
1703 | \r | |
1704 | /**\r | |
1705 | Gets the attributes that this PCI controller supports setting on a BAR using\r | |
1706 | SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r | |
1707 | \r | |
1708 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
1709 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
1710 | base address for resource range. The legal range for this field is 0..5.\r | |
1711 | @param Supports A pointer to the mask of attributes that this PCI controller supports\r | |
1712 | setting for this BAR with SetBarAttributes().\r | |
1713 | @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current\r | |
1714 | configuration of this BAR of the PCI controller.\r | |
1715 | \r | |
1716 | @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI\r | |
1717 | controller supports are returned in Supports. If Resources\r | |
1718 | is not NULL, then the ACPI 2.0 resource descriptors that the PCI\r | |
1719 | controller is currently using are returned in Resources.\r | |
1720 | @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r | |
1721 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
1722 | @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r | |
1723 | Resources.\r | |
1724 | \r | |
1725 | **/\r | |
1726 | EFI_STATUS\r | |
1727 | EFIAPI\r | |
1728 | PciIoGetBarAttributes (\r | |
1729 | IN EFI_PCI_IO_PROTOCOL * This,\r | |
1730 | IN UINT8 BarIndex,\r | |
1731 | OUT UINT64 *Supports, OPTIONAL\r | |
1732 | OUT VOID **Resources OPTIONAL\r | |
1733 | )\r | |
1734 | {\r | |
1735 | \r | |
1736 | UINT8 *Configuration;\r | |
1737 | UINT8 NumConfig;\r | |
1738 | PCI_IO_DEVICE *PciIoDevice;\r | |
1739 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r | |
1740 | EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;\r | |
1741 | \r | |
1742 | NumConfig = 0;\r | |
1743 | \r | |
1744 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
1745 | \r | |
1746 | if (Supports == NULL && Resources == NULL) {\r | |
1747 | return EFI_INVALID_PARAMETER;\r | |
1748 | }\r | |
1749 | \r | |
1750 | if (BarIndex >= PCI_MAX_BAR) {\r | |
1751 | return EFI_UNSUPPORTED;\r | |
1752 | }\r | |
1753 | \r | |
1754 | //\r | |
1755 | // This driver does not support modifications to the WRITE_COMBINE or\r | |
1756 | // CACHED attributes for BAR ranges.\r | |
1757 | //\r | |
1758 | if (Supports != NULL) {\r | |
1759 | *Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;\r | |
1760 | }\r | |
1761 | \r | |
1762 | if (Resources != NULL) {\r | |
1763 | \r | |
1764 | if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeUnknown) {\r | |
1765 | NumConfig = 1;\r | |
1766 | }\r | |
1767 | \r | |
1768 | Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r | |
1769 | if (Configuration == NULL) {\r | |
1770 | return EFI_OUT_OF_RESOURCES;\r | |
1771 | }\r | |
1772 | \r | |
1773 | Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r | |
1774 | \r | |
1775 | if (NumConfig == 1) {\r | |
1776 | Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r | |
c9325700 | 1777 | Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r |
9060e3ec | 1778 | \r |
1779 | Ptr->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;\r | |
1780 | Ptr->AddrLen = PciIoDevice->PciBar[BarIndex].Length;\r | |
1781 | Ptr->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;\r | |
1782 | \r | |
1783 | switch (PciIoDevice->PciBar[BarIndex].BarType) {\r | |
1784 | case PciBarTypeIo16:\r | |
1785 | case PciBarTypeIo32:\r | |
1786 | //\r | |
1787 | // Io\r | |
1788 | //\r | |
1789 | Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r | |
1790 | break;\r | |
1791 | \r | |
1792 | case PciBarTypeMem32:\r | |
1793 | //\r | |
1794 | // Mem\r | |
1795 | //\r | |
1796 | Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r | |
1797 | //\r | |
1798 | // 32 bit\r | |
1799 | //\r | |
1800 | Ptr->AddrSpaceGranularity = 32;\r | |
1801 | break;\r | |
1802 | \r | |
1803 | case PciBarTypePMem32:\r | |
1804 | //\r | |
1805 | // Mem\r | |
1806 | //\r | |
1807 | Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r | |
1808 | //\r | |
1809 | // prefechable\r | |
1810 | //\r | |
1811 | Ptr->SpecificFlag = 0x6;\r | |
1812 | //\r | |
1813 | // 32 bit\r | |
1814 | //\r | |
1815 | Ptr->AddrSpaceGranularity = 32;\r | |
1816 | break;\r | |
1817 | \r | |
1818 | case PciBarTypeMem64:\r | |
1819 | //\r | |
1820 | // Mem\r | |
1821 | //\r | |
1822 | Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r | |
1823 | //\r | |
1824 | // 64 bit\r | |
1825 | //\r | |
1826 | Ptr->AddrSpaceGranularity = 64;\r | |
1827 | break;\r | |
1828 | \r | |
1829 | case PciBarTypePMem64:\r | |
1830 | //\r | |
1831 | // Mem\r | |
1832 | //\r | |
1833 | Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r | |
1834 | //\r | |
1835 | // prefechable\r | |
1836 | //\r | |
1837 | Ptr->SpecificFlag = 0x6;\r | |
1838 | //\r | |
1839 | // 64 bit\r | |
1840 | //\r | |
1841 | Ptr->AddrSpaceGranularity = 64;\r | |
1842 | break;\r | |
1843 | \r | |
1844 | default:\r | |
1845 | break;\r | |
1846 | }\r | |
1847 | \r | |
1848 | Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r | |
1849 | }\r | |
1850 | \r | |
1851 | //\r | |
1852 | // put the checksum\r | |
1853 | //\r | |
1854 | PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) ((UINT8 *) Ptr);\r | |
1855 | PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r | |
1856 | PtrEnd->Checksum = 0;\r | |
1857 | \r | |
1858 | *Resources = Configuration;\r | |
1859 | }\r | |
1860 | \r | |
1861 | return EFI_SUCCESS;\r | |
1862 | }\r | |
1863 | \r | |
1864 | /**\r | |
1865 | Sets the attributes for a range of a BAR on a PCI controller.\r | |
1866 | \r | |
1867 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
1868 | @param Attributes The mask of attributes to set for the resource range specified by\r | |
1869 | BarIndex, Offset, and Length.\r | |
1870 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
1871 | base address for resource range. The legal range for this field is 0..5.\r | |
1872 | @param Offset A pointer to the BAR relative base address of the resource range to be\r | |
1873 | modified by the attributes specified by Attributes.\r | |
1874 | @param Length A pointer to the length of the resource range to be modified by the\r | |
1875 | attributes specified by Attributes.\r | |
1876 | \r | |
1877 | @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource\r | |
1878 | range specified by BarIndex, Offset, and Length were\r | |
1879 | set on the PCI controller, and the actual resource range is returned\r | |
1880 | in Offset and Length.\r | |
1881 | @retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r | |
1882 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
1883 | @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r | |
1884 | resource range specified by BarIndex, Offset, and\r | |
1885 | Length.\r | |
1886 | \r | |
1887 | **/\r | |
1888 | EFI_STATUS\r | |
1889 | EFIAPI\r | |
1890 | PciIoSetBarAttributes (\r | |
1891 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
1892 | IN UINT64 Attributes,\r | |
1893 | IN UINT8 BarIndex,\r | |
1894 | IN OUT UINT64 *Offset,\r | |
1895 | IN OUT UINT64 *Length\r | |
1896 | )\r | |
1897 | {\r | |
1898 | EFI_STATUS Status;\r | |
1899 | PCI_IO_DEVICE *PciIoDevice;\r | |
1900 | UINT64 NonRelativeOffset;\r | |
1901 | UINT64 Supports;\r | |
1902 | \r | |
1903 | PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r | |
1904 | \r | |
1905 | //\r | |
1906 | // Make sure Offset and Length are not NULL\r | |
1907 | //\r | |
1908 | if (Offset == NULL || Length == NULL) {\r | |
1909 | return EFI_INVALID_PARAMETER;\r | |
1910 | }\r | |
1911 | \r | |
1912 | if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown) {\r | |
1913 | return EFI_UNSUPPORTED;\r | |
1914 | }\r | |
1915 | //\r | |
1916 | // This driver does not support setting the WRITE_COMBINE or the CACHED attributes.\r | |
1917 | // If Attributes is not 0, then return EFI_UNSUPPORTED.\r | |
1918 | //\r | |
1919 | Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;\r | |
1920 | \r | |
1921 | if (Attributes != (Attributes & Supports)) {\r | |
1922 | return EFI_UNSUPPORTED;\r | |
1923 | }\r | |
1924 | //\r | |
1925 | // Attributes must be supported. Make sure the BAR range describd by BarIndex, Offset, and\r | |
1926 | // Length are valid for this PCI device.\r | |
1927 | //\r | |
1928 | NonRelativeOffset = *Offset;\r | |
1929 | Status = PciIoVerifyBarAccess (\r | |
1930 | PciIoDevice,\r | |
1931 | BarIndex,\r | |
1932 | PciBarTypeMem,\r | |
1933 | EfiPciIoWidthUint8,\r | |
1934 | (UINT32) *Length,\r | |
1935 | &NonRelativeOffset\r | |
1936 | );\r | |
1937 | if (EFI_ERROR (Status)) {\r | |
1938 | return EFI_UNSUPPORTED;\r | |
1939 | }\r | |
1940 | \r | |
1941 | return EFI_SUCCESS;\r | |
1942 | }\r | |
1943 | \r | |
1944 | /**\r | |
1945 | Program parent bridge's attribute recurrently.\r | |
1946 | \r | |
1947 | @param PciIoDevice Child Pci device instance\r | |
1948 | @param Operation The operation to perform on the attributes for this PCI controller.\r | |
1949 | @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r | |
1950 | operations.\r | |
1951 | \r | |
1952 | @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r | |
1953 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
1954 | @retval EFI_UNSUPPORTED one or more of the bits set in\r | |
1955 | Attributes are not supported by this PCI controller or one of\r | |
1956 | its parent bridges when Operation is Set, Enable or Disable.\r | |
1957 | \r | |
1958 | **/\r | |
1959 | EFI_STATUS\r | |
1960 | UpStreamBridgesAttributes (\r | |
1961 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
1962 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r | |
1963 | IN UINT64 Attributes\r | |
1964 | )\r | |
1965 | {\r | |
1966 | PCI_IO_DEVICE *Parent;\r | |
1967 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1968 | \r | |
1969 | Parent = PciIoDevice->Parent;\r | |
1970 | \r | |
1971 | while (Parent != NULL && IS_PCI_BRIDGE (&Parent->Pci)) {\r | |
1972 | \r | |
1973 | //\r | |
1974 | // Get the PciIo Protocol\r | |
1975 | //\r | |
1976 | PciIo = &Parent->PciIo;\r | |
1977 | \r | |
1978 | PciIo->Attributes (PciIo, Operation, Attributes, NULL);\r | |
1979 | \r | |
1980 | Parent = Parent->Parent;\r | |
1981 | }\r | |
1982 | \r | |
1983 | return EFI_SUCCESS;\r | |
1984 | }\r | |
1985 | \r | |
1986 | /**\r | |
1987 | Test whether two Pci devices has same parent bridge.\r | |
1988 | \r | |
1989 | @param PciDevice1 The first pci device for testing.\r | |
1990 | @param PciDevice2 The second pci device for testing.\r | |
1991 | \r | |
1992 | @retval TRUE Two Pci device has the same parent bridge.\r | |
1993 | @retval FALSE Two Pci device has not the same parent bridge.\r | |
1994 | \r | |
1995 | **/\r | |
1996 | BOOLEAN\r | |
1997 | PciDevicesOnTheSamePath (\r | |
1998 | IN PCI_IO_DEVICE *PciDevice1,\r | |
1999 | IN PCI_IO_DEVICE *PciDevice2\r | |
2000 | )\r | |
2001 | {\r | |
2002 | BOOLEAN Existed1;\r | |
2003 | BOOLEAN Existed2;\r | |
2004 | \r | |
2005 | if (PciDevice1->Parent == PciDevice2->Parent) {\r | |
2006 | return TRUE;\r | |
2007 | }\r | |
2008 | \r | |
2009 | Existed1 = PciDeviceExisted (PciDevice1->Parent, PciDevice2);\r | |
2010 | Existed2 = PciDeviceExisted (PciDevice2->Parent, PciDevice1);\r | |
2011 | \r | |
2012 | return (BOOLEAN) (Existed1 || Existed2);\r | |
2013 | }\r | |
2014 | \r |