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Use a local variable and assign 0 to it, then use it as legacy interrupt table base...
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciIo.c
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9060e3ec 1/** @file\r
2 EFI PCI IO protocol functions implementation for PCI Bus module.\r
3\r
250057b5 4Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
cd5ebaa0 5This program and the accompanying materials\r
9060e3ec 6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include "PciBus.h"\r
16\r
17//\r
18// Pci Io Protocol Interface\r
19//\r
20EFI_PCI_IO_PROTOCOL mPciIoInterface = {\r
21 PciIoPollMem,\r
22 PciIoPollIo,\r
23 {\r
24 PciIoMemRead,\r
25 PciIoMemWrite\r
26 },\r
27 {\r
28 PciIoIoRead,\r
29 PciIoIoWrite\r
30 },\r
31 {\r
32 PciIoConfigRead,\r
33 PciIoConfigWrite\r
34 },\r
35 PciIoCopyMem,\r
36 PciIoMap,\r
37 PciIoUnmap,\r
38 PciIoAllocateBuffer,\r
39 PciIoFreeBuffer,\r
40 PciIoFlush,\r
41 PciIoGetLocation,\r
42 PciIoAttributes,\r
43 PciIoGetBarAttributes,\r
44 PciIoSetBarAttributes,\r
45 0,\r
46 NULL\r
47};\r
48\r
9060e3ec 49/**\r
50 Initializes a PCI I/O Instance.\r
51\r
52 @param PciIoDevice Pci device instance.\r
53\r
54**/\r
55VOID\r
56InitializePciIoInstance (\r
57 IN PCI_IO_DEVICE *PciIoDevice\r
58 )\r
59{\r
60 CopyMem (&PciIoDevice->PciIo, &mPciIoInterface, sizeof (EFI_PCI_IO_PROTOCOL));\r
61}\r
62\r
63/**\r
64 Verifies access to a PCI Base Address Register (BAR).\r
65\r
66 @param PciIoDevice Pci device instance.\r
67 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
68 base address for the memory or I/O operation to perform.\r
69 @param Type Operation type could be memory or I/O.\r
70 @param Width Signifies the width of the memory or I/O operations.\r
71 @param Count The number of memory or I/O operations to perform.\r
72 @param Offset The offset within the PCI configuration space for the PCI controller.\r
73\r
74 @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.\r
75 @retval EFI_SUCCESS Successfully verified.\r
76\r
77**/\r
78EFI_STATUS\r
79PciIoVerifyBarAccess (\r
80 IN PCI_IO_DEVICE *PciIoDevice,\r
81 IN UINT8 BarIndex,\r
82 IN PCI_BAR_TYPE Type,\r
83 IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
84 IN IN UINTN Count,\r
85 IN UINT64 *Offset\r
86 )\r
87{\r
88 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
89 return EFI_INVALID_PARAMETER;\r
90 }\r
91\r
92 if (BarIndex == EFI_PCI_IO_PASS_THROUGH_BAR) {\r
93 return EFI_SUCCESS;\r
94 }\r
95\r
96 //\r
97 // BarIndex 0-5 is legal\r
98 //\r
99 if (BarIndex >= PCI_MAX_BAR) {\r
100 return EFI_INVALID_PARAMETER;\r
101 }\r
102\r
103 if (!CheckBarType (PciIoDevice, BarIndex, Type)) {\r
104 return EFI_INVALID_PARAMETER;\r
105 }\r
106\r
107 //\r
108 // If Width is EfiPciIoWidthFifoUintX then convert to EfiPciIoWidthUintX\r
109 // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX\r
110 //\r
815119f3 111 if (Width >= EfiPciIoWidthFifoUint8 && Width <= EfiPciIoWidthFifoUint64) {\r
9060e3ec 112 Count = 1;\r
113 }\r
114\r
115 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
116\r
117 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PciIoDevice->PciBar[BarIndex].Length) {\r
118 return EFI_INVALID_PARAMETER;\r
119 }\r
120\r
121 *Offset = *Offset + PciIoDevice->PciBar[BarIndex].BaseAddress;\r
122\r
123 return EFI_SUCCESS;\r
124}\r
125\r
126/**\r
127 Verifies access to a PCI Configuration Header.\r
128\r
129 @param PciIoDevice Pci device instance.\r
130 @param Width Signifies the width of the memory or I/O operations.\r
131 @param Count The number of memory or I/O operations to perform.\r
132 @param Offset The offset within the PCI configuration space for the PCI controller.\r
133\r
134 @retval EFI_INVALID_PARAMETER Invalid Width\r
135 @retval EFI_UNSUPPORTED Offset overflowed.\r
136 @retval EFI_SUCCESS Successfully verified.\r
137\r
138**/\r
139EFI_STATUS\r
140PciIoVerifyConfigAccess (\r
141 IN PCI_IO_DEVICE *PciIoDevice,\r
142 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
143 IN UINTN Count,\r
144 IN UINT64 *Offset\r
145 )\r
146{\r
147 UINT64 ExtendOffset;\r
148\r
149 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
150 return EFI_INVALID_PARAMETER;\r
151 }\r
152\r
153 //\r
154 // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX\r
155 //\r
156 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
157\r
158 if (PciIoDevice->IsPciExp) {\r
159 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_EXP_MAX_CONFIG_OFFSET) {\r
160 return EFI_UNSUPPORTED;\r
161 }\r
162\r
163 ExtendOffset = LShiftU64 (*Offset, 32);\r
164 *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);\r
165 *Offset = (*Offset) | ExtendOffset;\r
166\r
167 } else {\r
168 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_MAX_CONFIG_OFFSET) {\r
169 return EFI_UNSUPPORTED;\r
170 }\r
171\r
172 *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, *Offset);\r
173 }\r
174\r
175 return EFI_SUCCESS;\r
176}\r
177\r
178/**\r
179 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
180 satisfied or after a defined duration.\r
181\r
182 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
183 @param Width Signifies the width of the memory or I/O operations.\r
184 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
185 base address for the memory operation to perform.\r
186 @param Offset The offset within the selected BAR to start the memory operation.\r
187 @param Mask Mask used for the polling criteria.\r
188 @param Value The comparison value used for the polling exit criteria.\r
189 @param Delay The number of 100 ns units to poll.\r
190 @param Result Pointer to the last value read from the memory location.\r
191\r
192 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
193 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
194 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
195 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
196 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
197 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
198\r
199**/\r
200EFI_STATUS\r
201EFIAPI\r
202PciIoPollMem (\r
203 IN EFI_PCI_IO_PROTOCOL *This,\r
204 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
205 IN UINT8 BarIndex,\r
206 IN UINT64 Offset,\r
207 IN UINT64 Mask,\r
208 IN UINT64 Value,\r
209 IN UINT64 Delay,\r
210 OUT UINT64 *Result\r
211 )\r
212{\r
213 EFI_STATUS Status;\r
214 PCI_IO_DEVICE *PciIoDevice;\r
215\r
216 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
217\r
218 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
219 return EFI_INVALID_PARAMETER;\r
220 }\r
221\r
222 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, 1, &Offset);\r
223 if (EFI_ERROR (Status)) {\r
224 return EFI_UNSUPPORTED;\r
225 }\r
226\r
227 if (Width > EfiPciIoWidthUint64) {\r
228 return EFI_INVALID_PARAMETER;\r
229 }\r
230\r
aeeb84ba 231 //\r
232 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
233 // \r
234 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
235 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
236 Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);\r
237 if (EFI_ERROR (Status)) {\r
238 return Status;\r
239 }\r
240 if ((*Result & Mask) == Value || Delay == 0) {\r
241 return EFI_SUCCESS;\r
242 }\r
243 do {\r
244 //\r
245 // Stall 10 us = 100 * 100ns\r
246 //\r
247 gBS->Stall (10);\r
248\r
249 Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);\r
250 if (EFI_ERROR (Status)) {\r
251 return Status;\r
252 }\r
253 if ((*Result & Mask) == Value) {\r
254 return EFI_SUCCESS;\r
255 }\r
256 if (Delay <= 100) {\r
257 return EFI_TIMEOUT;\r
258 }\r
259 Delay -= 100;\r
260 } while (TRUE);\r
261 }\r
262 }\r
263 \r
9060e3ec 264 Status = PciIoDevice->PciRootBridgeIo->PollMem (\r
265 PciIoDevice->PciRootBridgeIo,\r
266 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
267 Offset,\r
268 Mask,\r
269 Value,\r
270 Delay,\r
271 Result\r
272 );\r
273\r
274 if (EFI_ERROR (Status)) {\r
250057b5 275 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
276 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
277 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
278 PciIoDevice->DevicePath\r
279 );\r
9060e3ec 280 }\r
281\r
282 return Status;\r
283}\r
284\r
285/**\r
286 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
287 satisfied or after a defined duration.\r
288\r
289 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
290 @param Width Signifies the width of the memory or I/O operations.\r
291 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
292 base address for the memory operation to perform.\r
293 @param Offset The offset within the selected BAR to start the memory operation.\r
294 @param Mask Mask used for the polling criteria.\r
295 @param Value The comparison value used for the polling exit criteria.\r
296 @param Delay The number of 100 ns units to poll.\r
297 @param Result Pointer to the last value read from the memory location.\r
298\r
299 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
300 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
301 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
302 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
303 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
304 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
305\r
306**/\r
307EFI_STATUS\r
308EFIAPI\r
309PciIoPollIo (\r
310 IN EFI_PCI_IO_PROTOCOL *This,\r
311 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
312 IN UINT8 BarIndex,\r
313 IN UINT64 Offset,\r
314 IN UINT64 Mask,\r
315 IN UINT64 Value,\r
316 IN UINT64 Delay,\r
317 OUT UINT64 *Result\r
318 )\r
319{\r
320 EFI_STATUS Status;\r
321 PCI_IO_DEVICE *PciIoDevice;\r
322\r
323 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
324\r
325 if (Width < 0 || Width > EfiPciIoWidthUint64) {\r
326 return EFI_INVALID_PARAMETER;\r
327 }\r
328\r
329 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, 1, &Offset);\r
330 if (EFI_ERROR (Status)) {\r
331 return EFI_UNSUPPORTED;\r
332 }\r
333\r
aeeb84ba 334 //\r
335 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
336 // \r
337 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
338 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
339 Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);\r
340 if (EFI_ERROR (Status)) {\r
341 return Status;\r
342 }\r
343 if ((*Result & Mask) == Value || Delay == 0) {\r
344 return EFI_SUCCESS;\r
345 }\r
346 do {\r
347 //\r
348 // Stall 10 us = 100 * 100ns\r
349 //\r
350 gBS->Stall (10);\r
351\r
352 Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);\r
353 if (EFI_ERROR (Status)) {\r
354 return Status;\r
355 }\r
356 if ((*Result & Mask) == Value) {\r
357 return EFI_SUCCESS;\r
358 }\r
359 if (Delay <= 100) {\r
360 return EFI_TIMEOUT;\r
361 }\r
362 Delay -= 100;\r
363 } while (TRUE);\r
364 }\r
365 }\r
366 \r
9060e3ec 367 Status = PciIoDevice->PciRootBridgeIo->PollIo (\r
368 PciIoDevice->PciRootBridgeIo,\r
369 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
370 Offset,\r
371 Mask,\r
372 Value,\r
373 Delay,\r
374 Result\r
375 );\r
376\r
377 if (EFI_ERROR (Status)) {\r
250057b5 378 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
379 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
380 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
381 PciIoDevice->DevicePath\r
382 );\r
9060e3ec 383 }\r
384\r
385 return Status;\r
386}\r
387\r
388/**\r
389 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
390\r
391 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
392 @param Width Signifies the width of the memory or I/O operations.\r
393 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
394 base address for the memory or I/O operation to perform.\r
395 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
396 @param Count The number of memory or I/O operations to perform.\r
397 @param Buffer For read operations, the destination buffer to store the results. For write\r
398 operations, the source buffer to write data from.\r
399\r
400 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
401 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
402 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
403 valid for the PCI BAR specified by BarIndex.\r
404 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
405 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
406\r
407**/\r
408EFI_STATUS\r
409EFIAPI\r
410PciIoMemRead (\r
411 IN EFI_PCI_IO_PROTOCOL *This,\r
412 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
413 IN UINT8 BarIndex,\r
414 IN UINT64 Offset,\r
415 IN UINTN Count,\r
416 IN OUT VOID *Buffer\r
417 )\r
418{\r
419 EFI_STATUS Status;\r
420 PCI_IO_DEVICE *PciIoDevice;\r
421\r
422 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
423\r
424 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
425 return EFI_INVALID_PARAMETER;\r
426 }\r
427\r
428 if (Buffer == NULL) {\r
429 return EFI_INVALID_PARAMETER;\r
430 }\r
431\r
432 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);\r
433 if (EFI_ERROR (Status)) {\r
434 return EFI_UNSUPPORTED;\r
435 }\r
436\r
aeeb84ba 437 //\r
438 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
439 // \r
440 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
441 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
aeeb84ba 442 Count *= (UINTN)(1 << (Width & 0x03));\r
c1450e16 443 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
aeeb84ba 444 }\r
445 } \r
446 \r
447\r
9060e3ec 448 Status = PciIoDevice->PciRootBridgeIo->Mem.Read (\r
449 PciIoDevice->PciRootBridgeIo,\r
450 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
451 Offset,\r
452 Count,\r
453 Buffer\r
454 );\r
455\r
456 if (EFI_ERROR (Status)) {\r
250057b5 457 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
458 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
459 EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,\r
460 PciIoDevice->DevicePath\r
461 );\r
9060e3ec 462 }\r
463\r
464 return Status;\r
465}\r
466\r
467/**\r
468 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
469\r
470 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
471 @param Width Signifies the width of the memory or I/O operations.\r
472 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
473 base address for the memory or I/O operation to perform.\r
474 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
475 @param Count The number of memory or I/O operations to perform.\r
476 @param Buffer For read operations, the destination buffer to store the results. For write\r
477 operations, the source buffer to write data from.\r
478\r
479 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
480 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
481 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
482 valid for the PCI BAR specified by BarIndex.\r
483 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
484 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
485\r
486**/\r
487EFI_STATUS\r
488EFIAPI\r
489PciIoMemWrite (\r
490 IN EFI_PCI_IO_PROTOCOL *This,\r
491 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
492 IN UINT8 BarIndex,\r
493 IN UINT64 Offset,\r
494 IN UINTN Count,\r
495 IN OUT VOID *Buffer\r
496 )\r
497{\r
498 EFI_STATUS Status;\r
499 PCI_IO_DEVICE *PciIoDevice;\r
500\r
501 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
502\r
503 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
504 return EFI_INVALID_PARAMETER;\r
505 }\r
506\r
507 if (Buffer == NULL) {\r
508 return EFI_INVALID_PARAMETER;\r
509 }\r
510\r
511 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);\r
512 if (EFI_ERROR (Status)) {\r
513 return EFI_UNSUPPORTED;\r
514 }\r
515\r
aeeb84ba 516 //\r
517 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
518 // \r
519 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
520 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
aeeb84ba 521 Count *= (UINTN)(1 << (Width & 0x03));\r
c1450e16 522 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
aeeb84ba 523 }\r
524 }\r
525\r
9060e3ec 526 Status = PciIoDevice->PciRootBridgeIo->Mem.Write (\r
527 PciIoDevice->PciRootBridgeIo,\r
528 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
529 Offset,\r
530 Count,\r
531 Buffer\r
532 );\r
533\r
534 if (EFI_ERROR (Status)) {\r
250057b5 535 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
536 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
537 EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,\r
538 PciIoDevice->DevicePath\r
539 );\r
9060e3ec 540 }\r
541\r
542 return Status;\r
543}\r
544\r
545/**\r
546 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
547\r
548 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
549 @param Width Signifies the width of the memory or I/O operations.\r
550 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
551 base address for the memory or I/O operation to perform.\r
552 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
553 @param Count The number of memory or I/O operations to perform.\r
554 @param Buffer For read operations, the destination buffer to store the results. For write\r
555 operations, the source buffer to write data from.\r
556\r
557 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
558 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
559 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
560 valid for the PCI BAR specified by BarIndex.\r
561 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
562 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
563\r
564**/\r
565EFI_STATUS\r
566EFIAPI\r
567PciIoIoRead (\r
568 IN EFI_PCI_IO_PROTOCOL *This,\r
569 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
570 IN UINT8 BarIndex,\r
571 IN UINT64 Offset,\r
572 IN UINTN Count,\r
573 IN OUT VOID *Buffer\r
574 )\r
575{\r
576 EFI_STATUS Status;\r
577 PCI_IO_DEVICE *PciIoDevice;\r
578\r
579 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
580\r
581 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
582 return EFI_INVALID_PARAMETER;\r
583 }\r
584\r
585 if (Buffer == NULL) {\r
586 return EFI_INVALID_PARAMETER;\r
587 }\r
588\r
589 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);\r
590 if (EFI_ERROR (Status)) {\r
591 return EFI_UNSUPPORTED;\r
592 }\r
593\r
aeeb84ba 594 //\r
595 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
596 // \r
597 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
598 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
aeeb84ba 599 Count *= (UINTN)(1 << (Width & 0x03));\r
c1450e16 600 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
aeeb84ba 601 }\r
602 } \r
603\r
9060e3ec 604 Status = PciIoDevice->PciRootBridgeIo->Io.Read (\r
605 PciIoDevice->PciRootBridgeIo,\r
606 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
607 Offset,\r
608 Count,\r
609 Buffer\r
610 );\r
611\r
612 if (EFI_ERROR (Status)) {\r
250057b5 613 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
614 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
615 EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,\r
616 PciIoDevice->DevicePath\r
617 );\r
9060e3ec 618 }\r
619\r
620 return Status;\r
621}\r
622\r
623/**\r
624 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
625\r
626 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
627 @param Width Signifies the width of the memory or I/O operations.\r
628 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
629 base address for the memory or I/O operation to perform.\r
630 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
631 @param Count The number of memory or I/O operations to perform.\r
632 @param Buffer For read operations, the destination buffer to store the results. For write\r
633 operations, the source buffer to write data from.\r
634\r
635 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
636 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
637 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
638 valid for the PCI BAR specified by BarIndex.\r
639 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
640 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
641\r
642**/\r
643EFI_STATUS\r
644EFIAPI\r
645PciIoIoWrite (\r
646 IN EFI_PCI_IO_PROTOCOL *This,\r
647 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
648 IN UINT8 BarIndex,\r
649 IN UINT64 Offset,\r
650 IN UINTN Count,\r
651 IN OUT VOID *Buffer\r
652 )\r
653{\r
654 EFI_STATUS Status;\r
655 PCI_IO_DEVICE *PciIoDevice;\r
656\r
657 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
658\r
659 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
660 return EFI_INVALID_PARAMETER;\r
661 }\r
662\r
663 if (Buffer == NULL) {\r
664 return EFI_INVALID_PARAMETER;\r
665 }\r
666\r
667 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);\r
668 if (EFI_ERROR (Status)) {\r
669 return EFI_UNSUPPORTED;\r
670 }\r
671\r
aeeb84ba 672 //\r
673 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
674 // \r
675 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
676 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
aeeb84ba 677 Count *= (UINTN)(1 << (Width & 0x03));\r
c1450e16 678 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
aeeb84ba 679 }\r
680 } \r
681\r
9060e3ec 682 Status = PciIoDevice->PciRootBridgeIo->Io.Write (\r
683 PciIoDevice->PciRootBridgeIo,\r
684 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
685 Offset,\r
686 Count,\r
687 Buffer\r
688 );\r
689\r
690 if (EFI_ERROR (Status)) {\r
250057b5 691 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
692 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
693 EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,\r
694 PciIoDevice->DevicePath\r
695 );\r
9060e3ec 696 }\r
697\r
698 return Status;\r
699}\r
700\r
701/**\r
702 Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
703\r
704 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
705 @param Width Signifies the width of the memory operations.\r
706 @param Offset The offset within the PCI configuration space for the PCI controller.\r
707 @param Count The number of PCI configuration operations to perform.\r
708 @param Buffer For read operations, the destination buffer to store the results. For write\r
709 operations, the source buffer to write data from.\r
710\r
711\r
712 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
713 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
714 valid for the PCI configuration header of the PCI controller.\r
715 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
716 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
717\r
718**/\r
719EFI_STATUS\r
720EFIAPI\r
721PciIoConfigRead (\r
722 IN EFI_PCI_IO_PROTOCOL *This,\r
723 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
724 IN UINT32 Offset,\r
725 IN UINTN Count,\r
726 IN OUT VOID *Buffer\r
727 )\r
728{\r
729 EFI_STATUS Status;\r
730 PCI_IO_DEVICE *PciIoDevice;\r
731 UINT64 Address;\r
732\r
733 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
734\r
735 Address = Offset;\r
736 Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);\r
737 if (EFI_ERROR (Status)) {\r
738 return Status;\r
739 }\r
aeeb84ba 740 \r
741 //\r
742 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
743 // \r
744 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
745 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
aeeb84ba 746 Count *= (UINTN)(1 << (Width & 0x03));\r
c1450e16 747 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
aeeb84ba 748 }\r
749 } \r
9060e3ec 750\r
751 Status = PciIoDevice->PciRootBridgeIo->Pci.Read (\r
752 PciIoDevice->PciRootBridgeIo,\r
753 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
754 Address,\r
755 Count,\r
756 Buffer\r
757 );\r
758\r
759 if (EFI_ERROR (Status)) {\r
250057b5 760 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
761 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
762 EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,\r
763 PciIoDevice->DevicePath\r
764 );\r
9060e3ec 765 }\r
766\r
767 return Status;\r
768}\r
769\r
770/**\r
771 Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
772\r
773 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
774 @param Width Signifies the width of the memory operations.\r
775 @param Offset The offset within the PCI configuration space for the PCI controller.\r
776 @param Count The number of PCI configuration operations to perform.\r
777 @param Buffer For read operations, the destination buffer to store the results. For write\r
778 operations, the source buffer to write data from.\r
779\r
780\r
781 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
782 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
783 valid for the PCI configuration header of the PCI controller.\r
784 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
785 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
786\r
787**/\r
788EFI_STATUS\r
789EFIAPI\r
790PciIoConfigWrite (\r
791 IN EFI_PCI_IO_PROTOCOL *This,\r
792 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
793 IN UINT32 Offset,\r
794 IN UINTN Count,\r
795 IN OUT VOID *Buffer\r
796 )\r
797{\r
798 EFI_STATUS Status;\r
799 PCI_IO_DEVICE *PciIoDevice;\r
800 UINT64 Address;\r
801\r
802 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
803\r
804 Address = Offset;\r
805 Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);\r
806 if (EFI_ERROR (Status)) {\r
807 return Status;\r
808 }\r
809\r
aeeb84ba 810 //\r
811 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
812 // \r
813 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
814 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
aeeb84ba 815 Count *= (UINTN)(1 << (Width & 0x03));\r
c1450e16 816 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
aeeb84ba 817 }\r
818 } \r
819 \r
9060e3ec 820 Status = PciIoDevice->PciRootBridgeIo->Pci.Write (\r
821 PciIoDevice->PciRootBridgeIo,\r
822 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
823 Address,\r
824 Count,\r
825 Buffer\r
826 );\r
827\r
828 if (EFI_ERROR (Status)) {\r
250057b5 829 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
830 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
831 EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,\r
832 PciIoDevice->DevicePath\r
833 );\r
9060e3ec 834 }\r
835\r
836 return Status;\r
837}\r
838\r
839/**\r
840 Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r
841 memory space.\r
842\r
843 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
844 @param Width Signifies the width of the memory operations.\r
845 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r
846 base address for the memory operation to perform.\r
847 @param DestOffset The destination offset within the BAR specified by DestBarIndex to\r
848 start the memory writes for the copy operation.\r
849 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r
850 base address for the memory operation to perform.\r
851 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r
852 the memory reads for the copy operation.\r
853 @param Count The number of memory operations to perform. Bytes moved is Width\r
854 size * Count, starting at DestOffset and SrcOffset.\r
855\r
856 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
857 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r
858 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r
859 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r
860 is not valid for the PCI BAR specified by DestBarIndex.\r
861 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r
862 not valid for the PCI BAR specified by SrcBarIndex.\r
863 @retval EFI_INVALID_PARAMETER Width is invalid.\r
864 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
865\r
866**/\r
867EFI_STATUS\r
868EFIAPI\r
869PciIoCopyMem (\r
870 IN EFI_PCI_IO_PROTOCOL *This,\r
871 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
872 IN UINT8 DestBarIndex,\r
873 IN UINT64 DestOffset,\r
874 IN UINT8 SrcBarIndex,\r
875 IN UINT64 SrcOffset,\r
876 IN UINTN Count\r
877 )\r
878{\r
879 EFI_STATUS Status;\r
880 PCI_IO_DEVICE *PciIoDevice;\r
881\r
882 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
883\r
884 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
885 return EFI_INVALID_PARAMETER;\r
886 }\r
887\r
888 if (Width == EfiPciIoWidthFifoUint8 ||\r
889 Width == EfiPciIoWidthFifoUint16 ||\r
890 Width == EfiPciIoWidthFifoUint32 ||\r
891 Width == EfiPciIoWidthFifoUint64 ||\r
892 Width == EfiPciIoWidthFillUint8 ||\r
893 Width == EfiPciIoWidthFillUint16 ||\r
894 Width == EfiPciIoWidthFillUint32 ||\r
895 Width == EfiPciIoWidthFillUint64) {\r
896 return EFI_INVALID_PARAMETER;\r
897 }\r
898\r
899 Status = PciIoVerifyBarAccess (PciIoDevice, DestBarIndex, PciBarTypeMem, Width, Count, &DestOffset);\r
900 if (EFI_ERROR (Status)) {\r
901 return EFI_UNSUPPORTED;\r
902 }\r
903\r
904 Status = PciIoVerifyBarAccess (PciIoDevice, SrcBarIndex, PciBarTypeMem, Width, Count, &SrcOffset);\r
905 if (EFI_ERROR (Status)) {\r
906 return EFI_UNSUPPORTED;\r
907 }\r
908\r
aeeb84ba 909 //\r
910 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
911 // \r
912 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
913 if ((SrcOffset & ((1 << (Width & 0x03)) - 1)) != 0 || (DestOffset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
aeeb84ba 914 Count *= (UINTN)(1 << (Width & 0x03));\r
c1450e16 915 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
aeeb84ba 916 }\r
917 } \r
918\r
9060e3ec 919 Status = PciIoDevice->PciRootBridgeIo->CopyMem (\r
920 PciIoDevice->PciRootBridgeIo,\r
921 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
922 DestOffset,\r
923 SrcOffset,\r
924 Count\r
925 );\r
926\r
927 if (EFI_ERROR (Status)) {\r
250057b5 928 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
929 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
930 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
931 PciIoDevice->DevicePath\r
932 );\r
9060e3ec 933 }\r
934\r
935 return Status;\r
936}\r
937\r
938/**\r
939 Provides the PCI controller-specific addresses needed to access system memory.\r
940\r
941 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
942 @param Operation Indicates if the bus master is going to read or write to system memory.\r
943 @param HostAddress The system memory address to map to the PCI controller.\r
944 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
945 that were mapped.\r
946 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
947 access the hosts HostAddress.\r
948 @param Mapping A resulting value to pass to Unmap().\r
949\r
950 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
951 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
952 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
953 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
954 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
955\r
956**/\r
957EFI_STATUS\r
958EFIAPI\r
959PciIoMap (\r
960 IN EFI_PCI_IO_PROTOCOL *This,\r
961 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r
962 IN VOID *HostAddress,\r
963 IN OUT UINTN *NumberOfBytes,\r
964 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
965 OUT VOID **Mapping\r
966 )\r
967{\r
968 EFI_STATUS Status;\r
969 PCI_IO_DEVICE *PciIoDevice;\r
970\r
971 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
972\r
973 if (Operation < 0 || Operation >= EfiPciIoOperationMaximum) {\r
974 return EFI_INVALID_PARAMETER;\r
975 }\r
976\r
977 if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {\r
978 return EFI_INVALID_PARAMETER;\r
979 }\r
980\r
981 if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {\r
982 Operation = (EFI_PCI_IO_PROTOCOL_OPERATION) (Operation + EfiPciOperationBusMasterRead64);\r
983 }\r
984\r
985 Status = PciIoDevice->PciRootBridgeIo->Map (\r
986 PciIoDevice->PciRootBridgeIo,\r
987 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) Operation,\r
988 HostAddress,\r
989 NumberOfBytes,\r
990 DeviceAddress,\r
991 Mapping\r
992 );\r
993\r
994 if (EFI_ERROR (Status)) {\r
250057b5 995 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
996 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
997 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
998 PciIoDevice->DevicePath\r
999 );\r
9060e3ec 1000 }\r
1001\r
1002 return Status;\r
1003}\r
1004\r
1005/**\r
1006 Completes the Map() operation and releases any corresponding resources.\r
1007\r
1008 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1009 @param Mapping The mapping value returned from Map().\r
1010\r
1011 @retval EFI_SUCCESS The range was unmapped.\r
1012 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
1013\r
1014**/\r
1015EFI_STATUS\r
1016EFIAPI\r
1017PciIoUnmap (\r
1018 IN EFI_PCI_IO_PROTOCOL *This,\r
1019 IN VOID *Mapping\r
1020 )\r
1021{\r
1022 EFI_STATUS Status;\r
1023 PCI_IO_DEVICE *PciIoDevice;\r
1024\r
1025 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1026\r
1027 Status = PciIoDevice->PciRootBridgeIo->Unmap (\r
1028 PciIoDevice->PciRootBridgeIo,\r
1029 Mapping\r
1030 );\r
1031\r
1032 if (EFI_ERROR (Status)) {\r
250057b5 1033 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
1034 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
1035 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
1036 PciIoDevice->DevicePath\r
1037 );\r
9060e3ec 1038 }\r
1039\r
1040 return Status;\r
1041}\r
1042\r
1043/**\r
1044 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
1045 mapping.\r
1046\r
1047 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1048 @param Type This parameter is not used and must be ignored.\r
1049 @param MemoryType The type of memory to allocate, EfiBootServicesData or\r
1050 EfiRuntimeServicesData.\r
1051 @param Pages The number of pages to allocate.\r
1052 @param HostAddress A pointer to store the base system memory address of the\r
1053 allocated range.\r
1054 @param Attributes The requested bit mask of attributes for the allocated range.\r
1055\r
1056 @retval EFI_SUCCESS The requested memory pages were allocated.\r
1057 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
1058 MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
1059 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
1060 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
1061\r
1062**/\r
1063EFI_STATUS\r
1064EFIAPI\r
1065PciIoAllocateBuffer (\r
1066 IN EFI_PCI_IO_PROTOCOL *This,\r
1067 IN EFI_ALLOCATE_TYPE Type,\r
1068 IN EFI_MEMORY_TYPE MemoryType,\r
1069 IN UINTN Pages,\r
1070 OUT VOID **HostAddress,\r
1071 IN UINT64 Attributes\r
1072 )\r
1073{\r
1074 EFI_STATUS Status;\r
1075 PCI_IO_DEVICE *PciIoDevice;\r
1076\r
1077 if ((Attributes &\r
1078 (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) != 0){\r
1079 return EFI_UNSUPPORTED;\r
1080 }\r
1081\r
1082 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1083\r
1084 if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {\r
1085 Attributes |= EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE;\r
1086 }\r
1087\r
1088 Status = PciIoDevice->PciRootBridgeIo->AllocateBuffer (\r
1089 PciIoDevice->PciRootBridgeIo,\r
1090 Type,\r
1091 MemoryType,\r
1092 Pages,\r
1093 HostAddress,\r
1094 Attributes\r
1095 );\r
1096\r
1097 if (EFI_ERROR (Status)) {\r
250057b5 1098 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
1099 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
1100 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
1101 PciIoDevice->DevicePath\r
1102 );\r
9060e3ec 1103 }\r
1104\r
1105 return Status;\r
1106}\r
1107\r
1108/**\r
1109 Frees memory that was allocated with AllocateBuffer().\r
1110\r
1111 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1112 @param Pages The number of pages to free.\r
1113 @param HostAddress The base system memory address of the allocated range.\r
1114\r
1115 @retval EFI_SUCCESS The requested memory pages were freed.\r
1116 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
1117 was not allocated with AllocateBuffer().\r
1118\r
1119**/\r
1120EFI_STATUS\r
1121EFIAPI\r
1122PciIoFreeBuffer (\r
1123 IN EFI_PCI_IO_PROTOCOL *This,\r
1124 IN UINTN Pages,\r
1125 IN VOID *HostAddress\r
1126 )\r
1127{\r
1128 EFI_STATUS Status;\r
1129 PCI_IO_DEVICE *PciIoDevice;\r
1130\r
1131 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1132\r
1133 Status = PciIoDevice->PciRootBridgeIo->FreeBuffer (\r
1134 PciIoDevice->PciRootBridgeIo,\r
1135 Pages,\r
1136 HostAddress\r
1137 );\r
1138\r
1139 if (EFI_ERROR (Status)) {\r
250057b5 1140 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
1141 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
1142 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
1143 PciIoDevice->DevicePath\r
1144 );\r
9060e3ec 1145 }\r
1146\r
1147 return Status;\r
1148}\r
1149\r
1150/**\r
1151 Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
1152\r
1153 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1154\r
1155 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
1156 bridge to system memory.\r
1157 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
1158 host bridge due to a hardware error.\r
1159\r
1160**/\r
1161EFI_STATUS\r
1162EFIAPI\r
1163PciIoFlush (\r
1164 IN EFI_PCI_IO_PROTOCOL *This\r
1165 )\r
1166{\r
1167 EFI_STATUS Status;\r
1168 PCI_IO_DEVICE *PciIoDevice;\r
1169\r
1170 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1171\r
1172 Status = PciIoDevice->PciRootBridgeIo->Flush (\r
1173 PciIoDevice->PciRootBridgeIo\r
1174 );\r
1175 if (EFI_ERROR (Status)) {\r
250057b5 1176 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
1177 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
1178 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
1179 PciIoDevice->DevicePath\r
1180 );\r
9060e3ec 1181 }\r
1182\r
1183 return Status;\r
1184}\r
1185\r
1186/**\r
1187 Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
1188\r
1189 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1190 @param SegmentNumber The PCI controller's current PCI segment number.\r
1191 @param BusNumber The PCI controller's current PCI bus number.\r
1192 @param DeviceNumber The PCI controller's current PCI device number.\r
1193 @param FunctionNumber The PCI controller's current PCI function number.\r
1194\r
1195 @retval EFI_SUCCESS The PCI controller location was returned.\r
1196 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
1197\r
1198**/\r
1199EFI_STATUS\r
1200EFIAPI\r
1201PciIoGetLocation (\r
1202 IN EFI_PCI_IO_PROTOCOL *This,\r
1203 OUT UINTN *Segment,\r
1204 OUT UINTN *Bus,\r
1205 OUT UINTN *Device,\r
1206 OUT UINTN *Function\r
1207 )\r
1208{\r
1209 PCI_IO_DEVICE *PciIoDevice;\r
1210\r
1211 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1212\r
1213 if (Segment == NULL || Bus == NULL || Device == NULL || Function == NULL) {\r
1214 return EFI_INVALID_PARAMETER;\r
1215 }\r
1216\r
1217 *Segment = PciIoDevice->PciRootBridgeIo->SegmentNumber;\r
1218 *Bus = PciIoDevice->BusNumber;\r
1219 *Device = PciIoDevice->DeviceNumber;\r
1220 *Function = PciIoDevice->FunctionNumber;\r
1221\r
1222 return EFI_SUCCESS;\r
1223}\r
1224\r
1225/**\r
1226 Check BAR type for PCI resource.\r
1227\r
1228 @param PciIoDevice PCI device instance.\r
1229 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
1230 base address for the memory or I/O operation to perform.\r
1231 @param BarType Memory or I/O.\r
1232\r
1233 @retval TRUE Pci device's bar type is same with input BarType.\r
1234 @retval TRUE Pci device's bar type is not same with input BarType.\r
1235\r
1236**/\r
1237BOOLEAN\r
1238CheckBarType (\r
1239 IN PCI_IO_DEVICE *PciIoDevice,\r
1240 IN UINT8 BarIndex,\r
1241 IN PCI_BAR_TYPE BarType\r
1242 )\r
1243{\r
1244 switch (BarType) {\r
1245\r
1246 case PciBarTypeMem:\r
1247\r
1248 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem32 &&\r
1249 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem32 &&\r
1250 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem64 &&\r
1251 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem64 ) {\r
1252 return FALSE;\r
1253 }\r
1254\r
1255 return TRUE;\r
1256\r
1257 case PciBarTypeIo:\r
1258 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo32 &&\r
1259 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo16){\r
1260 return FALSE;\r
1261 }\r
1262\r
1263 return TRUE;\r
1264\r
1265 default:\r
1266 break;\r
1267 }\r
1268\r
1269 return FALSE;\r
1270}\r
1271\r
1272/**\r
1273 Set/Disable new attributes to a Root Bridge.\r
1274\r
1275 @param PciIoDevice Pci device instance.\r
1276 @param Attributes New attribute want to be set.\r
1277 @param Operation Set or Disable.\r
1278\r
1279 @retval EFI_UNSUPPORTED If root bridge does not support change attribute.\r
1280 @retval EFI_SUCCESS Successfully set new attributs.\r
1281\r
1282**/\r
1283EFI_STATUS\r
1284ModifyRootBridgeAttributes (\r
1285 IN PCI_IO_DEVICE *PciIoDevice,\r
1286 IN UINT64 Attributes,\r
1287 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
1288 )\r
1289{\r
1290 UINT64 PciRootBridgeSupports;\r
1291 UINT64 PciRootBridgeAttributes;\r
1292 UINT64 NewPciRootBridgeAttributes;\r
1293 EFI_STATUS Status;\r
1294\r
1295 //\r
1296 // Get the current attributes of this PCI device's PCI Root Bridge\r
1297 //\r
1298 Status = PciIoDevice->PciRootBridgeIo->GetAttributes (\r
1299 PciIoDevice->PciRootBridgeIo,\r
1300 &PciRootBridgeSupports,\r
1301 &PciRootBridgeAttributes\r
1302 );\r
1303 if (EFI_ERROR (Status)) {\r
1304 return EFI_UNSUPPORTED;\r
1305 }\r
1306\r
7afa5ea8 1307 //\r
1308 // Mask off EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE & \r
1309 // EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM, which are not supported by PCI root bridge.\r
1310 //\r
1311 Attributes &= ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |\r
1312 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM);\r
1313\r
9060e3ec 1314 //\r
1315 // Record the new attribute of the Root Bridge\r
1316 //\r
1317 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1318 NewPciRootBridgeAttributes = PciRootBridgeAttributes | Attributes;\r
1319 } else {\r
1320 NewPciRootBridgeAttributes = PciRootBridgeAttributes & (~Attributes);\r
1321 }\r
1322\r
1323 //\r
1324 // Call the PCI Root Bridge to attempt to modify the attributes\r
1325 //\r
1326 if ((NewPciRootBridgeAttributes ^ PciRootBridgeAttributes) != 0) {\r
1327\r
1328 Status = PciIoDevice->PciRootBridgeIo->SetAttributes (\r
1329 PciIoDevice->PciRootBridgeIo,\r
1330 NewPciRootBridgeAttributes,\r
1331 NULL,\r
1332 NULL\r
1333 );\r
1334 if (EFI_ERROR (Status)) {\r
1335 //\r
1336 // The PCI Root Bridge could not modify the attributes, so return the error.\r
1337 //\r
1338 return EFI_UNSUPPORTED;\r
1339 }\r
1340 }\r
1341\r
1342 //\r
1343 // Also update the attributes for this Root Bridge structure\r
1344 //\r
1345 PciIoDevice->Attributes = NewPciRootBridgeAttributes;\r
1346\r
1347 return EFI_SUCCESS;\r
1348}\r
1349\r
1350/**\r
1351 Check whether this device can be enable/disable to snoop.\r
1352\r
1353 @param PciIoDevice Pci device instance.\r
1354 @param Operation Enable/Disable.\r
1355\r
1356 @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop.\r
1357 @retval EFI_SUCCESS Snoop can be supported.\r
1358\r
1359**/\r
1360EFI_STATUS\r
1361SupportPaletteSnoopAttributes (\r
1362 IN PCI_IO_DEVICE *PciIoDevice,\r
1363 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
1364 )\r
1365{\r
1366 PCI_IO_DEVICE *Temp;\r
1367 UINT16 VGACommand;\r
1368\r
1369 //\r
1370 // Snoop attribute can be only modified by GFX\r
1371 //\r
1372 if (!IS_PCI_GFX (&PciIoDevice->Pci)) {\r
1373 return EFI_UNSUPPORTED;\r
1374 }\r
1375\r
1376 //\r
1377 // Get the boot VGA on the same segement\r
1378 //\r
1379 Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);\r
1380\r
1381 if (Temp == NULL) {\r
1382 //\r
1383 // If there is no VGA device on the segement, set\r
1384 // this graphics card to decode the palette range\r
1385 //\r
1386 return EFI_SUCCESS;\r
1387 }\r
1388\r
1389 //\r
1390 // Check these two agents are on the same path\r
1391 //\r
1392 if (!PciDevicesOnTheSamePath (Temp, PciIoDevice)) {\r
1393 //\r
1394 // they are not on the same path, so snoop can be enabled or disabled\r
1395 //\r
1396 return EFI_SUCCESS;\r
1397 }\r
1398 //\r
1399 // Check if they are on the same bus\r
1400 //\r
1401 if (Temp->Parent == PciIoDevice->Parent) {\r
1402\r
1403 PCI_READ_COMMAND_REGISTER (Temp, &VGACommand);\r
1404\r
1405 //\r
1406 // If they are on the same bus, either one can\r
1407 // be set to snoop, the other set to decode\r
1408 //\r
1409 if ((VGACommand & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {\r
1410 //\r
1411 // VGA has set to snoop, so GFX can be only set to disable snoop\r
1412 //\r
1413 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1414 return EFI_UNSUPPORTED;\r
1415 }\r
1416 } else {\r
1417 //\r
1418 // VGA has disabled to snoop, so GFX can be only enabled\r
1419 //\r
1420 if (Operation == EfiPciIoAttributeOperationDisable) {\r
1421 return EFI_UNSUPPORTED;\r
1422 }\r
1423 }\r
1424\r
1425 return EFI_SUCCESS;\r
1426 }\r
1427\r
1428 //\r
1429 // If they are on the same path but on the different bus\r
1430 // The first agent is set to snoop, the second one set to\r
1431 // decode\r
1432 //\r
1433\r
1434 if (Temp->BusNumber < PciIoDevice->BusNumber) {\r
1435 //\r
1436 // GFX should be set to decode\r
1437 //\r
1438 if (Operation == EfiPciIoAttributeOperationDisable) {\r
1439 PCI_ENABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r
1440 Temp->Attributes |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;\r
1441 } else {\r
1442 return EFI_UNSUPPORTED;\r
1443 }\r
1444\r
1445 } else {\r
1446 //\r
1447 // GFX should be set to snoop\r
1448 //\r
1449 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1450 PCI_DISABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r
1451 Temp->Attributes &= (~EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r
1452 } else {\r
1453 return EFI_UNSUPPORTED;\r
1454 }\r
1455\r
1456 }\r
1457\r
1458 return EFI_SUCCESS;\r
1459}\r
1460\r
1461/**\r
1462 Performs an operation on the attributes that this PCI controller supports. The operations include\r
1463 getting the set of supported attributes, retrieving the current attributes, setting the current\r
1464 attributes, enabling attributes, and disabling attributes.\r
1465\r
1466 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1467 @param Operation The operation to perform on the attributes for this PCI controller.\r
1468 @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
1469 operations.\r
1470 @param Result A pointer to the result mask of attributes that are returned for the Get\r
1471 and Supported operations.\r
1472\r
1473 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
1474 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
1475 @retval EFI_UNSUPPORTED one or more of the bits set in\r
1476 Attributes are not supported by this PCI controller or one of\r
1477 its parent bridges when Operation is Set, Enable or Disable.\r
1478\r
1479**/\r
1480EFI_STATUS\r
1481EFIAPI\r
1482PciIoAttributes (\r
1483 IN EFI_PCI_IO_PROTOCOL * This,\r
1484 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
1485 IN UINT64 Attributes,\r
1486 OUT UINT64 *Result OPTIONAL\r
1487 )\r
1488{\r
1489 EFI_STATUS Status;\r
1490\r
1491 PCI_IO_DEVICE *PciIoDevice;\r
1492 PCI_IO_DEVICE *UpStreamBridge;\r
1493 PCI_IO_DEVICE *Temp;\r
1494\r
1495 UINT64 Supports;\r
1496 UINT64 UpStreamAttributes;\r
1497 UINT16 BridgeControl;\r
1498 UINT16 Command;\r
1499\r
1500 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1501\r
1502 switch (Operation) {\r
1503 case EfiPciIoAttributeOperationGet:\r
1504 if (Result == NULL) {\r
1505 return EFI_INVALID_PARAMETER;\r
1506 }\r
1507\r
1508 *Result = PciIoDevice->Attributes;\r
1509 return EFI_SUCCESS;\r
1510\r
1511 case EfiPciIoAttributeOperationSupported:\r
1512 if (Result == NULL) {\r
1513 return EFI_INVALID_PARAMETER;\r
1514 }\r
1515\r
1516 *Result = PciIoDevice->Supports;\r
1517 return EFI_SUCCESS;\r
1518\r
1519 case EfiPciIoAttributeOperationSet:\r
1520 Status = PciIoDevice->PciIo.Attributes (\r
1521 &(PciIoDevice->PciIo),\r
1522 EfiPciIoAttributeOperationEnable,\r
1523 Attributes,\r
1524 NULL\r
1525 );\r
1526 if (EFI_ERROR (Status)) {\r
1527 return EFI_UNSUPPORTED;\r
1528 }\r
1529\r
1530 Status = PciIoDevice->PciIo.Attributes (\r
1531 &(PciIoDevice->PciIo),\r
1532 EfiPciIoAttributeOperationDisable,\r
1533 (~Attributes) & (PciIoDevice->Supports),\r
1534 NULL\r
1535 );\r
1536 if (EFI_ERROR (Status)) {\r
1537 return EFI_UNSUPPORTED;\r
1538 }\r
1539\r
1540 return EFI_SUCCESS;\r
1541\r
1542 case EfiPciIoAttributeOperationEnable:\r
1543 case EfiPciIoAttributeOperationDisable:\r
1544 break;\r
1545\r
1546 default:\r
1547 return EFI_INVALID_PARAMETER;\r
1548 }\r
1549 //\r
1550 // Just a trick for ENABLE attribute\r
1551 // EFI_PCI_DEVICE_ENABLE is not defined in UEFI spec, which is the internal usage.\r
1552 // So, this logic doesn't confrom to UEFI spec, which should be removed.\r
1553 // But this trick logic is still kept for some binary drivers that depend on it.\r
1554 //\r
1555 if ((Attributes & EFI_PCI_DEVICE_ENABLE) == EFI_PCI_DEVICE_ENABLE) {\r
1556 Attributes &= (PciIoDevice->Supports);\r
1557\r
1558 //\r
1559 // Raise the EFI_P_PC_ENABLE Status code\r
1560 //\r
1561 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
1562 EFI_PROGRESS_CODE,\r
1563 EFI_IO_BUS_PCI | EFI_P_PC_ENABLE,\r
1564 PciIoDevice->DevicePath\r
1565 );\r
1566 }\r
1567\r
e0ee9d93 1568 //\r
1569 // Check VGA and VGA16, they can not be set at the same time\r
1570 //\r
1571 if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&\r
1572 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||\r
1573 ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&\r
1574 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ||\r
1575 ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&\r
1576 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||\r
1577 ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&\r
1578 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ) {\r
1579 return EFI_UNSUPPORTED;\r
1580 }\r
1581\r
1582 //\r
1583 // workaround for PCI drivers which always set ISA_IO or VGA_IO attribute without detecting support of\r
1584 // ISA_IO/ISA_IO_16 or VGA_IO/VGA_IO_16 to maintain backward-compatibility.\r
1585 //\r
1586 if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0) && \r
1587 ((PciIoDevice->Supports & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) \\r
1588 == EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) {\r
1589 Attributes &= ~(UINT64)EFI_PCI_IO_ATTRIBUTE_VGA_IO;\r
1590 Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_IO_16;\r
1591 }\r
1592\r
1593 if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0) && \r
1594 ((PciIoDevice->Supports & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) \\r
1595 == EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) {\r
1596 Attributes &= ~(UINT64)EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;\r
1597 Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16;\r
1598 }\r
1599\r
9060e3ec 1600 //\r
1601 // If no attributes can be supported, then return.\r
1602 // Otherwise, set the attributes that it can support.\r
1603 //\r
1604 Supports = (PciIoDevice->Supports) & Attributes;\r
1605 if (Supports != Attributes) {\r
1606 return EFI_UNSUPPORTED;\r
1607 }\r
1608\r
1609 //\r
1610 // For Root Bridge, just call RootBridgeIo to set attributes;\r
1611 //\r
1612 if (PciIoDevice->Parent == NULL) {\r
1613 Status = ModifyRootBridgeAttributes (PciIoDevice, Attributes, Operation);\r
1614 return Status;\r
1615 }\r
1616\r
1617 Command = 0;\r
1618 BridgeControl = 0;\r
1619\r
9060e3ec 1620 //\r
1621 // For PPB & P2C, set relevant attribute bits\r
1622 //\r
1623 if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r
1624\r
1625 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {\r
1626 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA;\r
1627 }\r
1628\r
1629 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_ISA_IO) != 0) {\r
1630 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_ISA;\r
1631 }\r
1632\r
1633 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {\r
1634 Command |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;\r
1635 }\r
1636\r
1637 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {\r
1638 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA_16;\r
1639 }\r
1640\r
1641 } else {\r
1642 //\r
1643 // Do with the attributes on VGA\r
1644 // Only for VGA's legacy resource, we just can enable once.\r
1645 //\r
1646 if ((Attributes &\r
1647 (EFI_PCI_IO_ATTRIBUTE_VGA_IO |\r
1648 EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 |\r
1649 EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY)) != 0) {\r
1650 //\r
1651 // Check if a VGA has been enabled before enabling a new one\r
1652 //\r
1653 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1654 //\r
1655 // Check if there have been an active VGA device on the same segment\r
1656 //\r
1657 Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);\r
1658 if (Temp != NULL && Temp != PciIoDevice) {\r
1659 //\r
1660 // An active VGA has been detected, so can not enable another\r
1661 //\r
1662 return EFI_UNSUPPORTED;\r
1663 }\r
1664 }\r
1665 }\r
1666\r
1667 //\r
1668 // Do with the attributes on GFX\r
1669 //\r
1670 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {\r
1671\r
1672 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1673 //\r
1674 // Check if snoop can be enabled in current configuration\r
1675 //\r
1676 Status = SupportPaletteSnoopAttributes (PciIoDevice, Operation);\r
1677\r
1678 if (EFI_ERROR (Status)) {\r
1679\r
1680 //\r
1681 // Enable operation is forbidden, so mask the bit in attributes\r
1682 // so as to keep consistent with the actual Status\r
1683 //\r
1684 // Attributes &= (~EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO);\r
1685 //\r
1686 //\r
1687 //\r
1688 return EFI_UNSUPPORTED;\r
1689\r
1690 }\r
1691 }\r
1692\r
1693 //\r
1694 // It can be supported, so get ready to set the bit\r
1695 //\r
1696 Command |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;\r
1697 }\r
1698 }\r
1699\r
1700 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_IO) != 0) {\r
1701 Command |= EFI_PCI_COMMAND_IO_SPACE;\r
1702 }\r
1703\r
1704 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_MEMORY) != 0) {\r
1705 Command |= EFI_PCI_COMMAND_MEMORY_SPACE;\r
1706 }\r
1707\r
1708 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) != 0) {\r
1709 Command |= EFI_PCI_COMMAND_BUS_MASTER;\r
1710 }\r
1711 //\r
1712 // The upstream bridge should be also set to revelant attribute\r
1713 // expect for IO, Mem and BusMaster\r
1714 //\r
1715 UpStreamAttributes = Attributes &\r
1716 (~(EFI_PCI_IO_ATTRIBUTE_IO |\r
1717 EFI_PCI_IO_ATTRIBUTE_MEMORY |\r
1718 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER\r
1719 )\r
1720 );\r
1721 UpStreamBridge = PciIoDevice->Parent;\r
1722\r
1723 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1724 //\r
1725 // Enable relevant attributes to command register and bridge control register\r
1726 //\r
1727 Status = PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, Command);\r
1728 if (BridgeControl != 0) {\r
1729 Status = PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);\r
1730 }\r
1731\r
1732 PciIoDevice->Attributes |= Attributes;\r
1733\r
1734 //\r
1735 // Enable attributes of the upstream bridge\r
1736 //\r
1737 Status = UpStreamBridge->PciIo.Attributes (\r
1738 &(UpStreamBridge->PciIo),\r
1739 EfiPciIoAttributeOperationEnable,\r
1740 UpStreamAttributes,\r
1741 NULL\r
1742 );\r
1743 } else {\r
1744\r
1745 //\r
1746 // Disable relevant attributes to command register and bridge control register\r
1747 //\r
1748 Status = PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, Command);\r
1749 if (BridgeControl != 0) {\r
1750 Status = PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);\r
1751 }\r
1752\r
1753 PciIoDevice->Attributes &= (~Attributes);\r
1754 Status = EFI_SUCCESS;\r
1755\r
1756 }\r
1757\r
1758 if (EFI_ERROR (Status)) {\r
250057b5 1759 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
1760 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
1761 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
1762 PciIoDevice->DevicePath\r
1763 );\r
9060e3ec 1764 }\r
1765\r
1766 return Status;\r
1767}\r
1768\r
1769/**\r
1770 Gets the attributes that this PCI controller supports setting on a BAR using\r
1771 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r
1772\r
1773 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1774 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
1775 base address for resource range. The legal range for this field is 0..5.\r
1776 @param Supports A pointer to the mask of attributes that this PCI controller supports\r
1777 setting for this BAR with SetBarAttributes().\r
1778 @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current\r
1779 configuration of this BAR of the PCI controller.\r
1780\r
1781 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI\r
1782 controller supports are returned in Supports. If Resources\r
1783 is not NULL, then the ACPI 2.0 resource descriptors that the PCI\r
1784 controller is currently using are returned in Resources.\r
1785 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
1786 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
1787 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r
1788 Resources.\r
1789\r
1790**/\r
1791EFI_STATUS\r
1792EFIAPI\r
1793PciIoGetBarAttributes (\r
1794 IN EFI_PCI_IO_PROTOCOL * This,\r
1795 IN UINT8 BarIndex,\r
1796 OUT UINT64 *Supports, OPTIONAL\r
1797 OUT VOID **Resources OPTIONAL\r
1798 )\r
1799{\r
1800\r
1801 UINT8 *Configuration;\r
1802 UINT8 NumConfig;\r
1803 PCI_IO_DEVICE *PciIoDevice;\r
1804 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
1805 EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;\r
1806\r
1807 NumConfig = 0;\r
1808\r
1809 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1810\r
1811 if (Supports == NULL && Resources == NULL) {\r
1812 return EFI_INVALID_PARAMETER;\r
1813 }\r
1814\r
1815 if (BarIndex >= PCI_MAX_BAR) {\r
1816 return EFI_UNSUPPORTED;\r
1817 }\r
1818\r
1819 //\r
1820 // This driver does not support modifications to the WRITE_COMBINE or\r
1821 // CACHED attributes for BAR ranges.\r
1822 //\r
1823 if (Supports != NULL) {\r
1824 *Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;\r
1825 }\r
1826\r
1827 if (Resources != NULL) {\r
1828\r
1829 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeUnknown) {\r
1830 NumConfig = 1;\r
1831 }\r
1832\r
1833 Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
1834 if (Configuration == NULL) {\r
1835 return EFI_OUT_OF_RESOURCES;\r
1836 }\r
1837\r
1838 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
1839\r
1840 if (NumConfig == 1) {\r
1841 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
c9325700 1842 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1843\r
1844 Ptr->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;\r
1845 Ptr->AddrLen = PciIoDevice->PciBar[BarIndex].Length;\r
1846 Ptr->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;\r
1847\r
1848 switch (PciIoDevice->PciBar[BarIndex].BarType) {\r
1849 case PciBarTypeIo16:\r
1850 case PciBarTypeIo32:\r
1851 //\r
1852 // Io\r
1853 //\r
1854 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
1855 break;\r
1856\r
1857 case PciBarTypeMem32:\r
1858 //\r
1859 // Mem\r
1860 //\r
1861 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1862 //\r
1863 // 32 bit\r
1864 //\r
1865 Ptr->AddrSpaceGranularity = 32;\r
1866 break;\r
1867\r
1868 case PciBarTypePMem32:\r
1869 //\r
1870 // Mem\r
1871 //\r
1872 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1873 //\r
1874 // prefechable\r
1875 //\r
1876 Ptr->SpecificFlag = 0x6;\r
1877 //\r
1878 // 32 bit\r
1879 //\r
1880 Ptr->AddrSpaceGranularity = 32;\r
1881 break;\r
1882\r
1883 case PciBarTypeMem64:\r
1884 //\r
1885 // Mem\r
1886 //\r
1887 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1888 //\r
1889 // 64 bit\r
1890 //\r
1891 Ptr->AddrSpaceGranularity = 64;\r
1892 break;\r
1893\r
1894 case PciBarTypePMem64:\r
1895 //\r
1896 // Mem\r
1897 //\r
1898 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1899 //\r
1900 // prefechable\r
1901 //\r
1902 Ptr->SpecificFlag = 0x6;\r
1903 //\r
1904 // 64 bit\r
1905 //\r
1906 Ptr->AddrSpaceGranularity = 64;\r
1907 break;\r
1908\r
1909 default:\r
1910 break;\r
1911 }\r
1912\r
1913 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
1914 }\r
1915\r
1916 //\r
1917 // put the checksum\r
1918 //\r
1919 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) ((UINT8 *) Ptr);\r
1920 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
1921 PtrEnd->Checksum = 0;\r
1922\r
1923 *Resources = Configuration;\r
1924 }\r
1925\r
1926 return EFI_SUCCESS;\r
1927}\r
1928\r
1929/**\r
1930 Sets the attributes for a range of a BAR on a PCI controller.\r
1931\r
1932 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1933 @param Attributes The mask of attributes to set for the resource range specified by\r
1934 BarIndex, Offset, and Length.\r
1935 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
1936 base address for resource range. The legal range for this field is 0..5.\r
1937 @param Offset A pointer to the BAR relative base address of the resource range to be\r
1938 modified by the attributes specified by Attributes.\r
1939 @param Length A pointer to the length of the resource range to be modified by the\r
1940 attributes specified by Attributes.\r
1941\r
1942 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource\r
1943 range specified by BarIndex, Offset, and Length were\r
1944 set on the PCI controller, and the actual resource range is returned\r
1945 in Offset and Length.\r
1946 @retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r
1947 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
1948 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r
1949 resource range specified by BarIndex, Offset, and\r
1950 Length.\r
1951\r
1952**/\r
1953EFI_STATUS\r
1954EFIAPI\r
1955PciIoSetBarAttributes (\r
1956 IN EFI_PCI_IO_PROTOCOL *This,\r
1957 IN UINT64 Attributes,\r
1958 IN UINT8 BarIndex,\r
1959 IN OUT UINT64 *Offset,\r
1960 IN OUT UINT64 *Length\r
1961 )\r
1962{\r
1963 EFI_STATUS Status;\r
1964 PCI_IO_DEVICE *PciIoDevice;\r
1965 UINT64 NonRelativeOffset;\r
1966 UINT64 Supports;\r
1967\r
1968 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1969\r
1970 //\r
1971 // Make sure Offset and Length are not NULL\r
1972 //\r
1973 if (Offset == NULL || Length == NULL) {\r
1974 return EFI_INVALID_PARAMETER;\r
1975 }\r
1976\r
1977 if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown) {\r
1978 return EFI_UNSUPPORTED;\r
1979 }\r
1980 //\r
1981 // This driver does not support setting the WRITE_COMBINE or the CACHED attributes.\r
1982 // If Attributes is not 0, then return EFI_UNSUPPORTED.\r
1983 //\r
1984 Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;\r
1985\r
1986 if (Attributes != (Attributes & Supports)) {\r
1987 return EFI_UNSUPPORTED;\r
1988 }\r
1989 //\r
1990 // Attributes must be supported. Make sure the BAR range describd by BarIndex, Offset, and\r
1991 // Length are valid for this PCI device.\r
1992 //\r
1993 NonRelativeOffset = *Offset;\r
1994 Status = PciIoVerifyBarAccess (\r
1995 PciIoDevice,\r
1996 BarIndex,\r
1997 PciBarTypeMem,\r
1998 EfiPciIoWidthUint8,\r
1999 (UINT32) *Length,\r
2000 &NonRelativeOffset\r
2001 );\r
2002 if (EFI_ERROR (Status)) {\r
2003 return EFI_UNSUPPORTED;\r
2004 }\r
2005\r
2006 return EFI_SUCCESS;\r
2007}\r
2008\r
2009/**\r
2010 Program parent bridge's attribute recurrently.\r
2011\r
2012 @param PciIoDevice Child Pci device instance\r
2013 @param Operation The operation to perform on the attributes for this PCI controller.\r
2014 @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
2015 operations.\r
2016\r
2017 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
2018 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
2019 @retval EFI_UNSUPPORTED one or more of the bits set in\r
2020 Attributes are not supported by this PCI controller or one of\r
2021 its parent bridges when Operation is Set, Enable or Disable.\r
2022\r
2023**/\r
2024EFI_STATUS\r
2025UpStreamBridgesAttributes (\r
2026 IN PCI_IO_DEVICE *PciIoDevice,\r
2027 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
2028 IN UINT64 Attributes\r
2029 )\r
2030{\r
2031 PCI_IO_DEVICE *Parent;\r
2032 EFI_PCI_IO_PROTOCOL *PciIo;\r
2033\r
2034 Parent = PciIoDevice->Parent;\r
2035\r
2036 while (Parent != NULL && IS_PCI_BRIDGE (&Parent->Pci)) {\r
2037\r
2038 //\r
2039 // Get the PciIo Protocol\r
2040 //\r
2041 PciIo = &Parent->PciIo;\r
2042\r
2043 PciIo->Attributes (PciIo, Operation, Attributes, NULL);\r
2044\r
2045 Parent = Parent->Parent;\r
2046 }\r
2047\r
2048 return EFI_SUCCESS;\r
2049}\r
2050\r
2051/**\r
2052 Test whether two Pci devices has same parent bridge.\r
2053\r
2054 @param PciDevice1 The first pci device for testing.\r
2055 @param PciDevice2 The second pci device for testing.\r
2056\r
2057 @retval TRUE Two Pci device has the same parent bridge.\r
2058 @retval FALSE Two Pci device has not the same parent bridge.\r
2059\r
2060**/\r
2061BOOLEAN\r
2062PciDevicesOnTheSamePath (\r
2063 IN PCI_IO_DEVICE *PciDevice1,\r
2064 IN PCI_IO_DEVICE *PciDevice2\r
2065 )\r
2066{\r
2067 BOOLEAN Existed1;\r
2068 BOOLEAN Existed2;\r
2069\r
2070 if (PciDevice1->Parent == PciDevice2->Parent) {\r
2071 return TRUE;\r
2072 }\r
2073\r
2074 Existed1 = PciDeviceExisted (PciDevice1->Parent, PciDevice2);\r
2075 Existed2 = PciDeviceExisted (PciDevice2->Parent, PciDevice1);\r
2076\r
2077 return (BOOLEAN) (Existed1 || Existed2);\r
2078}\r
2079\r
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