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9060e3ec 1/** @file\r
2 PCI resouces support functions implemntation for PCI Bus module.\r
3\r
cd5ebaa0
HT		 4Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
5This program and the accompanying materials\r
9060e3ec 6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include "PciBus.h"\r
16\r
17/**\r
18 The function is used to skip VGA range.\r
19\r
20 @param Start Returned start address including VGA range.\r
21 @param Length The length of VGA range.\r
22\r
23**/\r
24VOID\r
25SkipVGAAperture (\r
26 OUT UINT64 *Start,\r
27 IN UINT64 Length\r
28 )\r
29{\r
30 UINT64 Original;\r
31 UINT64 Mask;\r
32 UINT64 StartOffset;\r
33 UINT64 LimitOffset;\r
34\r
35 ASSERT (Start != NULL);\r
36 //\r
37 // For legacy VGA, bit 10 to bit 15 is not decoded\r
38 //\r
39 Mask = 0x3FF;\r
40\r
41 Original = *Start;\r
42 StartOffset = Original & Mask;\r
43 LimitOffset = ((*Start) + Length - 1) & Mask;\r
44 if (LimitOffset >= VGABASE1) {\r
45 *Start = *Start - StartOffset + VGALIMIT2 + 1;\r
46 }\r
47}\r
48\r
49/**\r
50 This function is used to skip ISA aliasing aperture.\r
51\r
52 @param Start Returned start address including ISA aliasing aperture.\r
53 @param Length The length of ISA aliasing aperture.\r
54\r
55**/\r
56VOID\r
57SkipIsaAliasAperture (\r
58 OUT UINT64 *Start,\r
59 IN UINT64 Length\r
60 )\r
61{\r
62\r
63 UINT64 Original;\r
64 UINT64 Mask;\r
65 UINT64 StartOffset;\r
66 UINT64 LimitOffset;\r
67\r
68 ASSERT (Start != NULL);\r
69\r
70 //\r
71 // For legacy ISA, bit 10 to bit 15 is not decoded\r
72 //\r
73 Mask = 0x3FF;\r
74\r
75 Original = *Start;\r
76 StartOffset = Original & Mask;\r
77 LimitOffset = ((*Start) + Length - 1) & Mask;\r
78\r
79 if (LimitOffset >= ISABASE) {\r
80 *Start = *Start - StartOffset + ISALIMIT + 1;\r
81 }\r
82}\r
83\r
84/**\r
85 This function inserts a resource node into the resource list.\r
86 The resource list is sorted in descend order.\r
87\r
88 @param Bridge PCI resource node for bridge.\r
89 @param ResNode Resource node want to be inserted.\r
90\r
91**/\r
92VOID\r
93InsertResourceNode (\r
94 IN OUT PCI_RESOURCE_NODE *Bridge,\r
95 IN PCI_RESOURCE_NODE *ResNode\r
96 )\r
97{\r
98 LIST_ENTRY *CurrentLink;\r
99 PCI_RESOURCE_NODE *Temp;\r
100 UINT64 ResNodeAlignRest;\r
101 UINT64 TempAlignRest;\r
102\r
103 ASSERT (Bridge != NULL);\r
104 ASSERT (ResNode != NULL);\r
105\r
106 InsertHeadList (&Bridge->ChildList, &ResNode->Link);\r
107\r
108 CurrentLink = Bridge->ChildList.ForwardLink->ForwardLink;\r
109 while (CurrentLink != &Bridge->ChildList) {\r
110 Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
111\r
112 if (ResNode->Alignment > Temp->Alignment) {\r
113 break;\r
114 } else if (ResNode->Alignment == Temp->Alignment) {\r
115 ResNodeAlignRest = ResNode->Length & ResNode->Alignment;\r
116 TempAlignRest = Temp->Length & Temp->Alignment;\r
117 if ((ResNodeAlignRest == 0) || (ResNodeAlignRest >= TempAlignRest)) {\r
118 break;\r
119 }\r
120 }\r
121\r
122 SwapListEntries (&ResNode->Link, CurrentLink);\r
123\r
124 CurrentLink = ResNode->Link.ForwardLink;\r
125 }\r
126}\r
127\r
128/**\r
129 This routine is used to merge two different resource trees in need of\r
130 resoure degradation.\r
131\r
132 For example, if an upstream PPB doesn't support,\r
133 prefetchable memory decoding, the PCI bus driver will choose to call this function\r
134 to merge prefectchable memory resource list into normal memory list.\r
135\r
136 If the TypeMerge is TRUE, Res resource type is changed to the type of destination resource\r
137 type.\r
138 If Dst is NULL or Res is NULL, ASSERT ().\r
139\r
140 @param Dst Point to destination resource tree.\r
141 @param Res Point to source resource tree.\r
142 @param TypeMerge If the TypeMerge is TRUE, Res resource type is changed to the type of\r
143 destination resource type.\r
144\r
145**/\r
146VOID\r
147MergeResourceTree (\r
148 IN PCI_RESOURCE_NODE *Dst,\r
149 IN PCI_RESOURCE_NODE *Res,\r
150 IN BOOLEAN TypeMerge\r
151 )\r
152{\r
153\r
154 LIST_ENTRY *CurrentLink;\r
155 PCI_RESOURCE_NODE *Temp;\r
156\r
157 ASSERT (Dst != NULL);\r
158 ASSERT (Res != NULL);\r
159\r
160 while (!IsListEmpty (&Res->ChildList)) {\r
161 CurrentLink = Res->ChildList.ForwardLink;\r
162\r
163 Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
164\r
165 if (TypeMerge) {\r
166 Temp->ResType = Dst->ResType;\r
167 }\r
168\r
169 RemoveEntryList (CurrentLink);\r
170 InsertResourceNode (Dst, Temp);\r
171 }\r
172}\r
173\r
174/**\r
175 This function is used to calculate the IO16 aperture\r
176 for a bridge.\r
177\r
178 @param Bridge PCI resource node for bridge.\r
179\r
180**/\r
181VOID\r
182CalculateApertureIo16 (\r
183 IN PCI_RESOURCE_NODE *Bridge\r
184 )\r
185{\r
186 EFI_STATUS Status;\r
187 UINT64 Aperture;\r
188 LIST_ENTRY *CurrentLink;\r
189 PCI_RESOURCE_NODE *Node;\r
190 UINT64 Offset;\r
191 BOOLEAN IsaEnable;\r
192 BOOLEAN VGAEnable;\r
193 EFI_PCI_PLATFORM_POLICY PciPolicy;\r
194\r
195 //\r
196 // Always assume there is ISA device and VGA device on the platform\r
197 // will be customized later\r
198 //\r
199 IsaEnable = FALSE;\r
200 VGAEnable = FALSE;\r
201\r
202 //\r
203 // Check PciPlatform policy\r
204 //\r
205 if (gPciPlatformProtocol != NULL) {\r
206 Status = gPciPlatformProtocol->GetPlatformPolicy (\r
207 gPciPlatformProtocol,\r
208 &PciPolicy\r
209 );\r
210 if (!EFI_ERROR (Status)) {\r
211 if ((PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) != 0) {\r
212 IsaEnable = TRUE;\r
213 }\r
214 if ((PciPolicy & EFI_RESERVE_VGA_IO_ALIAS) != 0) {\r
215 VGAEnable = TRUE;\r
216 }\r
217 }\r
218 } else if (gPciOverrideProtocol != NULL) {\r
219 Status = gPciOverrideProtocol->GetPlatformPolicy (\r
220 gPciOverrideProtocol,\r
221 &PciPolicy\r
222 );\r
223 if (!EFI_ERROR (Status)) {\r
224 if ((PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) != 0) {\r
225 IsaEnable = TRUE;\r
226 }\r
227 if ((PciPolicy & EFI_RESERVE_VGA_IO_ALIAS) != 0) {\r
228 VGAEnable = TRUE;\r
229 }\r
230 }\r
231 }\r
232\r
233 Aperture = 0;\r
234\r
235 if (Bridge == NULL) {\r
236 return ;\r
237 }\r
238\r
239 CurrentLink = Bridge->ChildList.ForwardLink;\r
240\r
241 //\r
242 // Assume the bridge is aligned\r
243 //\r
244 while (CurrentLink != &Bridge->ChildList) {\r
245\r
246 Node = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
247\r
248 //\r
249 // Consider the aperture alignment\r
250 //\r
251 Offset = Aperture & (Node->Alignment);\r
252\r
253 if (Offset != 0) {\r
254\r
255 Aperture = Aperture + (Node->Alignment + 1) - Offset;\r
256\r
257 }\r
258\r
259 //\r
260 // IsaEnable and VGAEnable can not be implemented now.\r
261 // If both of them are enabled, then the IO resource would\r
262 // become too limited to meet the requirement of most of devices.\r
263 //\r
264 if (IsaEnable || VGAEnable) {\r
265 if (!IS_PCI_BRIDGE (&(Node->PciDev->Pci)) && !IS_CARDBUS_BRIDGE (&(Node->PciDev->Pci))) {\r
266 //\r
267 // Check if there is need to support ISA/VGA decoding\r
268 // If so, we need to avoid isa/vga aliasing range\r
269 //\r
270 if (IsaEnable) {\r
271 SkipIsaAliasAperture (\r
272 &Aperture,\r
273 Node->Length\r
274 );\r
275 Offset = Aperture & (Node->Alignment);\r
276 if (Offset != 0) {\r
277 Aperture = Aperture + (Node->Alignment + 1) - Offset;\r
278 }\r
279 } else if (VGAEnable) {\r
280 SkipVGAAperture (\r
281 &Aperture,\r
282 Node->Length\r
283 );\r
284 Offset = Aperture & (Node->Alignment);\r
285 if (Offset != 0) {\r
286 Aperture = Aperture + (Node->Alignment + 1) - Offset;\r
287 }\r
288 }\r
289 }\r
290 }\r
291\r
292 Node->Offset = Aperture;\r
293\r
294 //\r
295 // Increment aperture by the length of node\r
296 //\r
297 Aperture += Node->Length;\r
298\r
299 CurrentLink = CurrentLink->ForwardLink;\r
300 }\r
301\r
302 //\r
303 // At last, adjust the aperture with the bridge's\r
304 // alignment\r
305 //\r
306 Offset = Aperture & (Bridge->Alignment);\r
307\r
308 if (Offset != 0) {\r
309 Aperture = Aperture + (Bridge->Alignment + 1) - Offset;\r
310 }\r
311\r
312 Bridge->Length = Aperture;\r
313 //\r
314 // At last, adjust the bridge's alignment to the first child's alignment\r
315 // if the bridge has at least one child\r
316 //\r
317 CurrentLink = Bridge->ChildList.ForwardLink;\r
318 if (CurrentLink != &Bridge->ChildList) {\r
319 Node = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
320 if (Node->Alignment > Bridge->Alignment) {\r
321 Bridge->Alignment = Node->Alignment;\r
322 }\r
323 }\r
324}\r
325\r
326/**\r
327 This function is used to calculate the resource aperture\r
328 for a given bridge device.\r
329\r
330 @param Bridge PCI resouce node for given bridge device.\r
331\r
332**/\r
333VOID\r
334CalculateResourceAperture (\r
335 IN PCI_RESOURCE_NODE *Bridge\r
336 )\r
337{\r
338 UINT64 Aperture;\r
339 LIST_ENTRY *CurrentLink;\r
340 PCI_RESOURCE_NODE *Node;\r
341\r
342 UINT64 Offset;\r
343\r
344 Aperture = 0;\r
345\r
346 if (Bridge == NULL) {\r
347 return ;\r
348 }\r
349\r
350 if (Bridge->ResType == PciBarTypeIo16) {\r
351\r
352 CalculateApertureIo16 (Bridge);\r
353 return ;\r
354 }\r
355\r
356 CurrentLink = Bridge->ChildList.ForwardLink;\r
357\r
358 //\r
359 // Assume the bridge is aligned\r
360 //\r
361 while (CurrentLink != &Bridge->ChildList) {\r
362\r
363 Node = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
364\r
365 //\r
366 // Apply padding resource if available\r
367 //\r
368 Offset = Aperture & (Node->Alignment);\r
369\r
370 if (Offset != 0) {\r
371\r
372 Aperture = Aperture + (Node->Alignment + 1) - Offset;\r
373\r
374 }\r
375\r
376 //\r
377 // Recode current aperture as a offset\r
378 // this offset will be used in future real allocation\r
379 //\r
380 Node->Offset = Aperture;\r
381\r
382 //\r
383 // Increment aperture by the length of node\r
384 //\r
385 Aperture += Node->Length;\r
386\r
387 //\r
388 // Consider the aperture alignment\r
389 //\r
390 CurrentLink = CurrentLink->ForwardLink;\r
391 }\r
392\r
393 //\r
394 // At last, adjust the aperture with the bridge's\r
395 // alignment\r
396 //\r
397 Offset = Aperture & (Bridge->Alignment);\r
398 if (Offset != 0) {\r
399 Aperture = Aperture + (Bridge->Alignment + 1) - Offset;\r
400 }\r
401\r
402 //\r
403 // If the bridge has already padded the resource and the\r
404 // amount of padded resource is larger, then keep the\r
405 // padded resource\r
406 //\r
407 if (Bridge->Length < Aperture) {\r
408 Bridge->Length = Aperture;\r
409 }\r
410\r
411 //\r
412 // At last, adjust the bridge's alignment to the first child's alignment\r
413 // if the bridge has at least one child\r
414 //\r
415 CurrentLink = Bridge->ChildList.ForwardLink;\r
416 if (CurrentLink != &Bridge->ChildList) {\r
417 Node = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
418 if (Node->Alignment > Bridge->Alignment) {\r
419 Bridge->Alignment = Node->Alignment;\r
420 }\r
421 }\r
422}\r
423\r
424/**\r
425 Get IO/Memory resource infor for given PCI device.\r
426\r
427 @param PciDev Pci device instance.\r
428 @param IoNode Resource info node for IO .\r
429 @param Mem32Node Resource info node for 32-bit memory.\r
430 @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
431 @param Mem64Node Resource info node for 64-bit memory.\r
432 @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
433\r
434**/\r
435VOID\r
436GetResourceFromDevice (\r
437 IN PCI_IO_DEVICE *PciDev,\r
438 IN OUT PCI_RESOURCE_NODE *IoNode,\r
439 IN OUT PCI_RESOURCE_NODE *Mem32Node,\r
440 IN OUT PCI_RESOURCE_NODE *PMem32Node,\r
441 IN OUT PCI_RESOURCE_NODE *Mem64Node,\r
442 IN OUT PCI_RESOURCE_NODE *PMem64Node\r
443 )\r
444{\r
445\r
446 UINT8 Index;\r
447 PCI_RESOURCE_NODE *Node;\r
448 BOOLEAN ResourceRequested;\r
449\r
450 Node = NULL;\r
451 ResourceRequested = FALSE;\r
452\r
453 for (Index = 0; Index < PCI_MAX_BAR; Index++) {\r
454\r
455 switch ((PciDev->PciBar)[Index].BarType) {\r
456\r
457 case PciBarTypeMem32:\r
458\r
459 Node = CreateResourceNode (\r
460 PciDev,\r
461 (PciDev->PciBar)[Index].Length,\r
462 (PciDev->PciBar)[Index].Alignment,\r
463 Index,\r
464 PciBarTypeMem32,\r
465 PciResUsageTypical\r
466 );\r
467\r
468 InsertResourceNode (\r
469 Mem32Node,\r
470 Node\r
471 );\r
472\r
473 ResourceRequested = TRUE;\r
474 break;\r
475\r
476 case PciBarTypeMem64:\r
477\r
478 Node = CreateResourceNode (\r
479 PciDev,\r
480 (PciDev->PciBar)[Index].Length,\r
481 (PciDev->PciBar)[Index].Alignment,\r
482 Index,\r
483 PciBarTypeMem64,\r
484 PciResUsageTypical\r
485 );\r
486\r
487 InsertResourceNode (\r
488 Mem64Node,\r
489 Node\r
490 );\r
491\r
492 ResourceRequested = TRUE;\r
493 break;\r
494\r
495 case PciBarTypePMem64:\r
496\r
497 Node = CreateResourceNode (\r
498 PciDev,\r
499 (PciDev->PciBar)[Index].Length,\r
500 (PciDev->PciBar)[Index].Alignment,\r
501 Index,\r
502 PciBarTypePMem64,\r
503 PciResUsageTypical\r
504 );\r
505\r
506 InsertResourceNode (\r
507 PMem64Node,\r
508 Node\r
509 );\r
510\r
511 ResourceRequested = TRUE;\r
512 break;\r
513\r
514 case PciBarTypePMem32:\r
515\r
516 Node = CreateResourceNode (\r
517 PciDev,\r
518 (PciDev->PciBar)[Index].Length,\r
519 (PciDev->PciBar)[Index].Alignment,\r
520 Index,\r
521 PciBarTypePMem32,\r
522 PciResUsageTypical\r
523 );\r
524\r
525 InsertResourceNode (\r
526 PMem32Node,\r
527 Node\r
528 );\r
529 ResourceRequested = TRUE;\r
530 break;\r
531\r
532 case PciBarTypeIo16:\r
533 case PciBarTypeIo32:\r
534\r
535 Node = CreateResourceNode (\r
536 PciDev,\r
537 (PciDev->PciBar)[Index].Length,\r
538 (PciDev->PciBar)[Index].Alignment,\r
539 Index,\r
540 PciBarTypeIo16,\r
541 PciResUsageTypical\r
542 );\r
543\r
544 InsertResourceNode (\r
545 IoNode,\r
546 Node\r
547 );\r
548 ResourceRequested = TRUE;\r
549 break;\r
550\r
551 case PciBarTypeUnknown:\r
552 break;\r
553\r
554 default:\r
555 break;\r
556 }\r
557 }\r
558\r
559 //\r
560 // Add VF resource\r
561 //\r
562 for (Index = 0; Index < PCI_MAX_BAR; Index++) {\r
563\r
564 switch ((PciDev->VfPciBar)[Index].BarType) {\r
565\r
566 case PciBarTypeMem32:\r
567\r
568 Node = CreateVfResourceNode (\r
569 PciDev,\r
570 (PciDev->VfPciBar)[Index].Length,\r
571 (PciDev->VfPciBar)[Index].Alignment,\r
572 Index,\r
573 PciBarTypeMem32,\r
574 PciResUsageTypical\r
575 );\r
576\r
577 InsertResourceNode (\r
578 Mem32Node,\r
579 Node\r
580 );\r
581\r
582 break;\r
583\r
584 case PciBarTypeMem64:\r
585\r
586 Node = CreateVfResourceNode (\r
587 PciDev,\r
588 (PciDev->VfPciBar)[Index].Length,\r
589 (PciDev->VfPciBar)[Index].Alignment,\r
590 Index,\r
591 PciBarTypeMem64,\r
592 PciResUsageTypical\r
593 );\r
594\r
595 InsertResourceNode (\r
596 Mem64Node,\r
597 Node\r
598 );\r
599\r
600 break;\r
601\r
602 case PciBarTypePMem64:\r
603\r
604 Node = CreateVfResourceNode (\r
605 PciDev,\r
606 (PciDev->VfPciBar)[Index].Length,\r
607 (PciDev->VfPciBar)[Index].Alignment,\r
608 Index,\r
609 PciBarTypePMem64,\r
610 PciResUsageTypical\r
611 );\r
612\r
613 InsertResourceNode (\r
614 PMem64Node,\r
615 Node\r
616 );\r
617\r
618 break;\r
619\r
620 case PciBarTypePMem32:\r
621\r
622 Node = CreateVfResourceNode (\r
623 PciDev,\r
624 (PciDev->VfPciBar)[Index].Length,\r
625 (PciDev->VfPciBar)[Index].Alignment,\r
626 Index,\r
627 PciBarTypePMem32,\r
628 PciResUsageTypical\r
629 );\r
630\r
631 InsertResourceNode (\r
632 PMem32Node,\r
633 Node\r
634 );\r
635 break;\r
636\r
637 case PciBarTypeIo16:\r
638 case PciBarTypeIo32:\r
639 break;\r
640\r
641 case PciBarTypeUnknown:\r
642 break;\r
643\r
644 default:\r
645 break;\r
646 }\r
647 }\r
648 // If there is no resource requested from this device,\r
649 // then we indicate this device has been allocated naturally.\r
650 //\r
651 if (!ResourceRequested) {\r
652 PciDev->Allocated = TRUE;\r
653 }\r
654}\r
655\r
656/**\r
657 This function is used to create a resource node.\r
658\r
659 @param PciDev Pci device instance.\r
660 @param Length Length of Io/Memory resource.\r
661 @param Alignment Alignment of resource.\r
662 @param Bar Bar index.\r
663 @param ResType Type of resource: IO/Memory.\r
664 @param ResUsage Resource usage.\r
665\r
666 @return PCI resource node created for given PCI device.\r
667 NULL means PCI resource node is not created.\r
668\r
669**/\r
670PCI_RESOURCE_NODE *\r
671CreateResourceNode (\r
672 IN PCI_IO_DEVICE *PciDev,\r
673 IN UINT64 Length,\r
674 IN UINT64 Alignment,\r
675 IN UINT8 Bar,\r
676 IN PCI_BAR_TYPE ResType,\r
677 IN PCI_RESOURCE_USAGE ResUsage\r
678 )\r
679{\r
680 PCI_RESOURCE_NODE *Node;\r
681\r
682 Node = NULL;\r
683\r
684 Node = AllocateZeroPool (sizeof (PCI_RESOURCE_NODE));\r
685 ASSERT (Node != NULL);\r
686 if (Node == NULL) {\r
687 return NULL;\r
688 }\r
689\r
690 Node->Signature = PCI_RESOURCE_SIGNATURE;\r
691 Node->PciDev = PciDev;\r
692 Node->Length = Length;\r
693 Node->Alignment = Alignment;\r
694 Node->Bar = Bar;\r
695 Node->ResType = ResType;\r
696 Node->Reserved = FALSE;\r
697 Node->ResourceUsage = ResUsage;\r
698 InitializeListHead (&Node->ChildList);\r
699\r
700 return Node;\r
701}\r
702\r
703/**\r
704 This function is used to create a IOV VF resource node.\r
705\r
706 @param PciDev Pci device instance.\r
707 @param Length Length of Io/Memory resource.\r
708 @param Alignment Alignment of resource.\r
709 @param Bar Bar index.\r
710 @param ResType Type of resource: IO/Memory.\r
711 @param ResUsage Resource usage.\r
712\r
713 @return PCI resource node created for given VF PCI device.\r
714 NULL means PCI resource node is not created.\r
715\r
716**/\r
717PCI_RESOURCE_NODE *\r
718CreateVfResourceNode (\r
719 IN PCI_IO_DEVICE *PciDev,\r
720 IN UINT64 Length,\r
721 IN UINT64 Alignment,\r
722 IN UINT8 Bar,\r
723 IN PCI_BAR_TYPE ResType,\r
724 IN PCI_RESOURCE_USAGE ResUsage\r
725 )\r
726{\r
727 PCI_RESOURCE_NODE *Node;\r
728\r
729 DEBUG ((\r
730 EFI_D_INFO,\r
731 "PCI-IOV B%x.D%x.F%x - VfResource (Bar - 0x%x) (Type - 0x%x) (Length - 0x%x)\n",\r
732 (UINTN)PciDev->BusNumber,\r
733 (UINTN)PciDev->DeviceNumber,\r
734 (UINTN)PciDev->FunctionNumber,\r
735 (UINTN)Bar,\r
736 (UINTN)ResType,\r
737 (UINTN)Length\r
738 ));\r
739\r
740 Node = CreateResourceNode (PciDev, Length, Alignment, Bar, ResType, ResUsage);\r
741 if (Node == NULL) {\r
742 return Node;\r
743 }\r
744\r
745 Node->Virtual = TRUE;\r
746\r
747 return Node;\r
748}\r
749\r
750/**\r
751 This function is used to extract resource request from\r
752 device node list.\r
753\r
754 @param Bridge Pci device instance.\r
755 @param IoNode Resource info node for IO.\r
756 @param Mem32Node Resource info node for 32-bit memory.\r
757 @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
758 @param Mem64Node Resource info node for 64-bit memory.\r
759 @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
760\r
761**/\r
762VOID\r
763CreateResourceMap (\r
764 IN PCI_IO_DEVICE *Bridge,\r
765 IN OUT PCI_RESOURCE_NODE *IoNode,\r
766 IN OUT PCI_RESOURCE_NODE *Mem32Node,\r
767 IN OUT PCI_RESOURCE_NODE *PMem32Node,\r
768 IN OUT PCI_RESOURCE_NODE *Mem64Node,\r
769 IN OUT PCI_RESOURCE_NODE *PMem64Node\r
770 )\r
771{\r
772 PCI_IO_DEVICE *Temp;\r
773 PCI_RESOURCE_NODE *IoBridge;\r
774 PCI_RESOURCE_NODE *Mem32Bridge;\r
775 PCI_RESOURCE_NODE *PMem32Bridge;\r
776 PCI_RESOURCE_NODE *Mem64Bridge;\r
777 PCI_RESOURCE_NODE *PMem64Bridge;\r
778 LIST_ENTRY *CurrentLink;\r
779\r
780 CurrentLink = Bridge->ChildList.ForwardLink;\r
781\r
782 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
783\r
784 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
785\r
786 //\r
787 // Create resource nodes for this device by scanning the\r
788 // Bar array in the device private data\r
789 // If the upstream bridge doesn't support this device,\r
790 // no any resource node will be created for this device\r
791 //\r
792 GetResourceFromDevice (\r
793 Temp,\r
794 IoNode,\r
795 Mem32Node,\r
796 PMem32Node,\r
797 Mem64Node,\r
798 PMem64Node\r
799 );\r
800\r
801 if (IS_PCI_BRIDGE (&Temp->Pci)) {\r
802\r
803 //\r
804 // If the device has children, create a bridge resource node for this PPB\r
805 // Note: For PPB, memory aperture is aligned with 1MB and IO aperture\r
1ef26783 806 // is aligned with 4KB (smaller alignments may be supported).\r
9060e3ec 807 //\r
808 IoBridge = CreateResourceNode (\r
809 Temp,\r
810 0,\r
1ef26783 811 Temp->BridgeIoAlignment,\r
9060e3ec 812 PPB_IO_RANGE,\r
813 PciBarTypeIo16,\r
814 PciResUsageTypical\r
815 );\r
816\r
817 Mem32Bridge = CreateResourceNode (\r
818 Temp,\r
819 0,\r
820 0xFFFFF,\r
821 PPB_MEM32_RANGE,\r
822 PciBarTypeMem32,\r
823 PciResUsageTypical\r
824 );\r
825\r
826 PMem32Bridge = CreateResourceNode (\r
827 Temp,\r
828 0,\r
829 0xFFFFF,\r
830 PPB_PMEM32_RANGE,\r
831 PciBarTypePMem32,\r
832 PciResUsageTypical\r
833 );\r
834\r
835 Mem64Bridge = CreateResourceNode (\r
836 Temp,\r
837 0,\r
838 0xFFFFF,\r
839 PPB_MEM64_RANGE,\r
840 PciBarTypeMem64,\r
841 PciResUsageTypical\r
842 );\r
843\r
844 PMem64Bridge = CreateResourceNode (\r
845 Temp,\r
846 0,\r
847 0xFFFFF,\r
848 PPB_PMEM64_RANGE,\r
849 PciBarTypePMem64,\r
850 PciResUsageTypical\r
851 );\r
852\r
853 //\r
854 // Recursively create resouce map on this bridge\r
855 //\r
856 CreateResourceMap (\r
857 Temp,\r
858 IoBridge,\r
859 Mem32Bridge,\r
860 PMem32Bridge,\r
861 Mem64Bridge,\r
862 PMem64Bridge\r
863 );\r
864\r
865 if (ResourceRequestExisted (IoBridge)) {\r
866 InsertResourceNode (\r
867 IoNode,\r
868 IoBridge\r
869 );\r
870 } else {\r
871 FreePool (IoBridge);\r
872 IoBridge = NULL;\r
873 }\r
874\r
875 //\r
876 // If there is node under this resource bridge,\r
877 // then calculate bridge's aperture of this type\r
878 // and insert it into the respective resource tree.\r
879 // If no, delete this resource bridge\r
880 //\r
881 if (ResourceRequestExisted (Mem32Bridge)) {\r
882 InsertResourceNode (\r
883 Mem32Node,\r
884 Mem32Bridge\r
885 );\r
886 } else {\r
887 FreePool (Mem32Bridge);\r
888 Mem32Bridge = NULL;\r
889 }\r
890\r
891 //\r
892 // If there is node under this resource bridge,\r
893 // then calculate bridge's aperture of this type\r
894 // and insert it into the respective resource tree.\r
895 // If no, delete this resource bridge\r
896 //\r
897 if (ResourceRequestExisted (PMem32Bridge)) {\r
898 InsertResourceNode (\r
899 PMem32Node,\r
900 PMem32Bridge\r
901 );\r
902 } else {\r
903 FreePool (PMem32Bridge);\r
904 PMem32Bridge = NULL;\r
905 }\r
906\r
907 //\r
908 // If there is node under this resource bridge,\r
909 // then calculate bridge's aperture of this type\r
910 // and insert it into the respective resource tree.\r
911 // If no, delete this resource bridge\r
912 //\r
913 if (ResourceRequestExisted (Mem64Bridge)) {\r
914 InsertResourceNode (\r
915 Mem64Node,\r
916 Mem64Bridge\r
917 );\r
918 } else {\r
919 FreePool (Mem64Bridge);\r
920 Mem64Bridge = NULL;\r
921 }\r
922\r
923 //\r
924 // If there is node under this resource bridge,\r
925 // then calculate bridge's aperture of this type\r
926 // and insert it into the respective resource tree.\r
927 // If no, delete this resource bridge\r
928 //\r
929 if (ResourceRequestExisted (PMem64Bridge)) {\r
930 InsertResourceNode (\r
931 PMem64Node,\r
932 PMem64Bridge\r
933 );\r
934 } else {\r
935 FreePool (PMem64Bridge);\r
936 PMem64Bridge = NULL;\r
937 }\r
938\r
939 }\r
940\r
941 //\r
942 // If it is P2C, apply hard coded resource padding\r
943 //\r
944 if (IS_CARDBUS_BRIDGE (&Temp->Pci)) {\r
945 ResourcePaddingForCardBusBridge (\r
946 Temp,\r
947 IoNode,\r
948 Mem32Node,\r
949 PMem32Node,\r
950 Mem64Node,\r
951 PMem64Node\r
952 );\r
953 }\r
954\r
955 CurrentLink = CurrentLink->ForwardLink;\r
956 }\r
957\r
958 //\r
959 // To do some platform specific resource padding ...\r
960 //\r
961 ResourcePaddingPolicy (\r
962 Bridge,\r
963 IoNode,\r
964 Mem32Node,\r
965 PMem32Node,\r
966 Mem64Node,\r
967 PMem64Node\r
968 );\r
969\r
970 //\r
971 // Degrade resource if necessary\r
972 //\r
973 DegradeResource (\r
974 Bridge,\r
975 Mem32Node,\r
976 PMem32Node,\r
977 Mem64Node,\r
978 PMem64Node\r
979 );\r
980\r
981 //\r
982 // Calculate resource aperture for this bridge device\r
983 //\r
984 CalculateResourceAperture (Mem32Node);\r
985 CalculateResourceAperture (PMem32Node);\r
986 CalculateResourceAperture (Mem64Node);\r
987 CalculateResourceAperture (PMem64Node);\r
988 CalculateResourceAperture (IoNode);\r
989}\r
990\r
991/**\r
992 This function is used to do the resource padding for a specific platform.\r
993\r
994 @param PciDev Pci device instance.\r
995 @param IoNode Resource info node for IO.\r
996 @param Mem32Node Resource info node for 32-bit memory.\r
997 @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
998 @param Mem64Node Resource info node for 64-bit memory.\r
999 @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
1000\r
1001**/\r
1002VOID\r
1003ResourcePaddingPolicy (\r
1004 IN PCI_IO_DEVICE *PciDev,\r
1005 IN PCI_RESOURCE_NODE *IoNode,\r
1006 IN PCI_RESOURCE_NODE *Mem32Node,\r
1007 IN PCI_RESOURCE_NODE *PMem32Node,\r
1008 IN PCI_RESOURCE_NODE *Mem64Node,\r
1009 IN PCI_RESOURCE_NODE *PMem64Node\r
1010 )\r
1011{\r
1012 //\r
1013 // Create padding resource node\r
1014 //\r
1015 if (PciDev->ResourcePaddingDescriptors != NULL) {\r
1016 ApplyResourcePadding (\r
1017 PciDev,\r
1018 IoNode,\r
1019 Mem32Node,\r
1020 PMem32Node,\r
1021 Mem64Node,\r
1022 PMem64Node\r
1023 );\r
1024 }\r
1025}\r
1026\r
1027/**\r
1028 This function is used to degrade resource if the upstream bridge\r
1029 doesn't support certain resource. Degradation path is\r
1030 PMEM64 -> MEM64 -> MEM32\r
1031 PMEM64 -> PMEM32 -> MEM32\r
1032 IO32 -> IO16.\r
1033\r
1034 @param Bridge Pci device instance.\r
1035 @param Mem32Node Resource info node for 32-bit memory.\r
1036 @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
1037 @param Mem64Node Resource info node for 64-bit memory.\r
1038 @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
1039\r
1040**/\r
1041VOID\r
1042DegradeResource (\r
1043 IN PCI_IO_DEVICE *Bridge,\r
1044 IN PCI_RESOURCE_NODE *Mem32Node,\r
1045 IN PCI_RESOURCE_NODE *PMem32Node,\r
1046 IN PCI_RESOURCE_NODE *Mem64Node,\r
1047 IN PCI_RESOURCE_NODE *PMem64Node\r
1048 )\r
1049{\r
9060e3ec 1050 PCI_IO_DEVICE *Temp;\r
de028a62 1051 LIST_ENTRY *ChildDeviceLink;\r
1052 LIST_ENTRY *ChildNodeLink;\r
4661d5df 1053 LIST_ENTRY *NextChildNodeLink;\r
60516202 1054 PCI_RESOURCE_NODE *TempNode;\r
9060e3ec 1055\r
1056 //\r
60516202 1057 // If any child device has both option ROM and 64-bit BAR, degrade its PMEM64/MEM64\r
1058 // requests in case that if a legacy option ROM image can not access 64-bit resources.\r
9060e3ec 1059 //\r
de028a62 1060 ChildDeviceLink = Bridge->ChildList.ForwardLink;\r
1061 while (ChildDeviceLink != NULL && ChildDeviceLink != &Bridge->ChildList) {\r
1062 Temp = PCI_IO_DEVICE_FROM_LINK (ChildDeviceLink);\r
9060e3ec 1063 if (Temp->RomSize != 0) {\r
60516202 1064 if (!IsListEmpty (&Mem64Node->ChildList)) { \r
de028a62 1065 ChildNodeLink = Mem64Node->ChildList.ForwardLink;\r
1066 while (ChildNodeLink != &Mem64Node->ChildList) {\r
1067 TempNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink);\r
4661d5df 1068 NextChildNodeLink = ChildNodeLink->ForwardLink;\r
60516202 1069\r
1070 if (TempNode->PciDev == Temp) {\r
de028a62 1071 RemoveEntryList (ChildNodeLink);\r
60516202 1072 InsertResourceNode (Mem32Node, TempNode);\r
1073 }\r
4661d5df 1074 ChildNodeLink = NextChildNodeLink;\r
60516202 1075 } \r
1076 }\r
1077\r
1078 if (!IsListEmpty (&PMem64Node->ChildList)) { \r
de028a62 1079 ChildNodeLink = PMem64Node->ChildList.ForwardLink;\r
1080 while (ChildNodeLink != &PMem64Node->ChildList) {\r
1081 TempNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink);\r
4661d5df 1082 NextChildNodeLink = ChildNodeLink->ForwardLink;\r
60516202 1083\r
1084 if (TempNode->PciDev == Temp) {\r
de028a62 1085 RemoveEntryList (ChildNodeLink);\r
60516202 1086 InsertResourceNode (PMem32Node, TempNode);\r
1087 }\r
4661d5df 1088 ChildNodeLink = NextChildNodeLink;\r
60516202 1089 } \r
1090 }\r
1091\r
9060e3ec 1092 }\r
de028a62 1093 ChildDeviceLink = ChildDeviceLink->ForwardLink;\r
9060e3ec 1094 }\r
1095\r
1096 //\r
60516202 1097 // If firmware is in 32-bit mode,\r
1098 // then degrade PMEM64/MEM64 requests\r
9060e3ec 1099 //\r
60516202 1100 if (sizeof (UINTN) <= 4) {\r
1101 MergeResourceTree (\r
1102 Mem32Node,\r
1103 Mem64Node,\r
1104 TRUE\r
1105 );\r
1106\r
9060e3ec 1107 MergeResourceTree (\r
1108 PMem32Node,\r
1109 PMem64Node,\r
1110 TRUE\r
1111 );\r
1112 } else {\r
1113 //\r
60516202 1114 // if the bridge does not support MEM64, degrade MEM64 to MEM32\r
9060e3ec 1115 //\r
60516202 1116 if (!BridgeSupportResourceDecode (Bridge, EFI_BRIDGE_MEM64_DECODE_SUPPORTED)) {\r
1117 MergeResourceTree (\r
1118 Mem32Node,\r
1119 Mem64Node,\r
1120 TRUE\r
1121 );\r
1122 }\r
1123\r
1124 //\r
1125 // if the bridge does not support PMEM64, degrade PMEM64 to PMEM32\r
1126 //\r
1127 if (!BridgeSupportResourceDecode (Bridge, EFI_BRIDGE_PMEM64_DECODE_SUPPORTED)) {\r
9060e3ec 1128 MergeResourceTree (\r
1129 PMem32Node,\r
1130 PMem64Node,\r
1131 TRUE\r
1132 );\r
60516202 1133 } \r
9060e3ec 1134\r
60516202 1135 //\r
1136 // if both PMEM64 and PMEM32 requests from child devices, which can not be satisfied\r
1137 // by a P2P bridge simultaneously, keep PMEM64 and degrade PMEM32 to MEM32.\r
1138 //\r
1139 if (!IsListEmpty (&PMem64Node->ChildList) && Bridge->Parent != NULL) {\r
1140 MergeResourceTree (\r
1141 Mem32Node,\r
1142 PMem32Node,\r
1143 TRUE\r
1144 );\r
1145 }\r
9060e3ec 1146 }\r
1147\r
1148 //\r
1149 // If bridge doesn't support Pmem32\r
1150 // degrade it to mem32\r
1151 //\r
1152 if (!BridgeSupportResourceDecode (Bridge, EFI_BRIDGE_PMEM32_DECODE_SUPPORTED)) {\r
1153 MergeResourceTree (\r
1154 Mem32Node,\r
1155 PMem32Node,\r
1156 TRUE\r
1157 );\r
1158 }\r
1159\r
1160 //\r
60516202 1161 // if root bridge supports combined Pmem Mem decoding\r
9060e3ec 1162 // merge these two type of resource\r
1163 //\r
1164 if (BridgeSupportResourceDecode (Bridge, EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED)) {\r
1165 MergeResourceTree (\r
1166 Mem32Node,\r
1167 PMem32Node,\r
1168 FALSE\r
1169 );\r
1170\r
60516202 1171 //\r
1172 // No need to check if to degrade MEM64 after merge, because\r
1173 // if there are PMEM64 still here, 64-bit decode should be supported\r
1174 // by the root bride.\r
1175 //\r
9060e3ec 1176 MergeResourceTree (\r
1177 Mem64Node,\r
1178 PMem64Node,\r
1179 FALSE\r
1180 );\r
1181 }\r
1182}\r
1183\r
1184/**\r
1185 Test whether bridge device support decode resource.\r
1186\r
1187 @param Bridge Bridge device instance.\r
1188 @param Decode Decode type according to resource type.\r
1189\r
1190 @return TRUE The bridge device support decode resource.\r
1191 @return FALSE The bridge device don't support decode resource.\r
1192\r
1193**/\r
1194BOOLEAN\r
1195BridgeSupportResourceDecode (\r
1196 IN PCI_IO_DEVICE *Bridge,\r
1197 IN UINT32 Decode\r
1198 )\r
1199{\r
1200 if (((Bridge->Decodes) & Decode) != 0) {\r
1201 return TRUE;\r
1202 }\r
1203\r
1204 return FALSE;\r
1205}\r
1206\r
1207/**\r
1208 This function is used to program the resource allocated\r
1209 for each resource node under specified bridge.\r
1210\r
1211 @param Base Base address of resource to be progammed.\r
1212 @param Bridge PCI resource node for the bridge device.\r
1213\r
1214 @retval EFI_SUCCESS Successfully to program all resouces\r
1215 on given PCI bridge device.\r
1216 @retval EFI_OUT_OF_RESOURCES Base is all one.\r
1217\r
1218**/\r
1219EFI_STATUS\r
1220ProgramResource (\r
1221 IN UINT64 Base,\r
1222 IN PCI_RESOURCE_NODE *Bridge\r
1223 )\r
1224{\r
1225 LIST_ENTRY *CurrentLink;\r
1226 PCI_RESOURCE_NODE *Node;\r
1227 EFI_STATUS Status;\r
1228\r
1229 if (Base == gAllOne) {\r
1230 return EFI_OUT_OF_RESOURCES;\r
1231 }\r
1232\r
1233 CurrentLink = Bridge->ChildList.ForwardLink;\r
1234\r
1235 while (CurrentLink != &Bridge->ChildList) {\r
1236\r
1237 Node = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
1238\r
1239 if (!IS_PCI_BRIDGE (&(Node->PciDev->Pci))) {\r
1240\r
1241 if (IS_CARDBUS_BRIDGE (&(Node->PciDev->Pci))) {\r
1242 //\r
1243 // Program the PCI Card Bus device\r
1244 //\r
1245 ProgramP2C (Base, Node);\r
1246 } else {\r
1247 //\r
1248 // Program the PCI device BAR\r
1249 //\r
1250 ProgramBar (Base, Node);\r
1251 }\r
1252 } else {\r
1253 //\r
1254 // Program the PCI devices under this bridge\r
1255 //\r
1256 Status = ProgramResource (Base + Node->Offset, Node);\r
1257 if (EFI_ERROR (Status)) {\r
1258 return Status;\r
1259 }\r
1260\r
1261 ProgramPpbApperture (Base, Node);\r
1262 }\r
1263\r
1264 CurrentLink = CurrentLink->ForwardLink;\r
1265 }\r
1266\r
1267 return EFI_SUCCESS;\r
1268}\r
1269\r
1270/**\r
1271 Program Bar register for PCI device.\r
1272\r
1273 @param Base Base address for PCI device resource to be progammed.\r
1274 @param Node Point to resoure node structure.\r
1275\r
1276**/\r
1277VOID\r
1278ProgramBar (\r
1279 IN UINT64 Base,\r
1280 IN PCI_RESOURCE_NODE *Node\r
1281 )\r
1282{\r
1283 EFI_PCI_IO_PROTOCOL *PciIo;\r
1284 UINT64 Address;\r
1285 UINT32 Address32;\r
1286\r
1287 ASSERT (Node->Bar < PCI_MAX_BAR);\r
1288\r
1289 //\r
1290 // Check VF BAR\r
1291 //\r
1292 if (Node->Virtual) {\r
1293 ProgramVfBar (Base, Node);\r
1294 }\r
1295\r
1296 Address = 0;\r
1297 PciIo = &(Node->PciDev->PciIo);\r
1298\r
1299 Address = Base + Node->Offset;\r
1300\r
1301 //\r
1302 // Indicate pci bus driver has allocated\r
1303 // resource for this device\r
1304 // It might be a temporary solution here since\r
1305 // pci device could have multiple bar\r
1306 //\r
1307 Node->PciDev->Allocated = TRUE;\r
1308\r
1309 switch ((Node->PciDev->PciBar[Node->Bar]).BarType) {\r
1310\r
1311 case PciBarTypeIo16:\r
1312 case PciBarTypeIo32:\r
1313 case PciBarTypeMem32:\r
1314 case PciBarTypePMem32:\r
1315\r
1316 PciIo->Pci.Write (\r
1317 PciIo,\r
1318 EfiPciIoWidthUint32,\r
1319 (Node->PciDev->PciBar[Node->Bar]).Offset,\r
1320 1,\r
1321 &Address\r
1322 );\r
1323\r
1324 Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
1325\r
1326 break;\r
1327\r
1328 case PciBarTypeMem64:\r
1329 case PciBarTypePMem64:\r
1330\r
1331 Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);\r
1332\r
1333 PciIo->Pci.Write (\r
1334 PciIo,\r
1335 EfiPciIoWidthUint32,\r
1336 (Node->PciDev->PciBar[Node->Bar]).Offset,\r
1337 1,\r
1338 &Address32\r
1339 );\r
1340\r
1341 Address32 = (UINT32) RShiftU64 (Address, 32);\r
1342\r
1343 PciIo->Pci.Write (\r
1344 PciIo,\r
1345 EfiPciIoWidthUint32,\r
1346 (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),\r
1347 1,\r
1348 &Address32\r
1349 );\r
1350\r
1351 Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
1352\r
1353 break;\r
1354\r
1355 default:\r
1356 break;\r
1357 }\r
1358}\r
1359\r
1360/**\r
1361 Program IOV VF Bar register for PCI device.\r
1362\r
1363 @param Base Base address for PCI device resource to be progammed.\r
1364 @param Node Point to resoure node structure.\r
1365\r
1366**/\r
1367EFI_STATUS\r
1368ProgramVfBar (\r
1369 IN UINT64 Base,\r
1370 IN PCI_RESOURCE_NODE *Node\r
1371 )\r
1372{\r
1373 EFI_PCI_IO_PROTOCOL *PciIo;\r
1374 UINT64 Address;\r
1375 UINT32 Address32;\r
1376\r
1377 ASSERT (Node->Bar < PCI_MAX_BAR);\r
1378 ASSERT (Node->Virtual);\r
1379\r
1380 Address = 0;\r
1381 PciIo = &(Node->PciDev->PciIo);\r
1382\r
1383 Address = Base + Node->Offset;\r
1384\r
1385 //\r
1386 // Indicate pci bus driver has allocated\r
1387 // resource for this device\r
1388 // It might be a temporary solution here since\r
1389 // pci device could have multiple bar\r
1390 //\r
1391 Node->PciDev->Allocated = TRUE;\r
1392\r
1393 switch ((Node->PciDev->VfPciBar[Node->Bar]).BarType) {\r
1394\r
1395 case PciBarTypeMem32:\r
1396 case PciBarTypePMem32:\r
1397\r
1398 PciIo->Pci.Write (\r
1399 PciIo,\r
1400 EfiPciIoWidthUint32,\r
1401 (Node->PciDev->VfPciBar[Node->Bar]).Offset,\r
1402 1,\r
1403 &Address\r
1404 );\r
1405\r
1406 Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;\r
1407\r
1408 DEBUG ((\r
1409 EFI_D_INFO,\r
1410 "PCI-IOV B%x.D%x.F%x - VF Bar (Offset - 0x%x) 32Mem (Address - 0x%x)\n",\r
1411 (UINTN)Node->PciDev->BusNumber,\r
1412 (UINTN)Node->PciDev->DeviceNumber,\r
1413 (UINTN)Node->PciDev->FunctionNumber,\r
1414 (UINTN)(Node->PciDev->VfPciBar[Node->Bar]).Offset,\r
1415 (UINTN)Address\r
1416 ));\r
1417\r
1418 break;\r
1419\r
1420 case PciBarTypeMem64:\r
1421 case PciBarTypePMem64:\r
1422\r
1423 Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);\r
1424\r
1425 PciIo->Pci.Write (\r
1426 PciIo,\r
1427 EfiPciIoWidthUint32,\r
1428 (Node->PciDev->VfPciBar[Node->Bar]).Offset,\r
1429 1,\r
1430 &Address32\r
1431 );\r
1432\r
1433 Address32 = (UINT32) RShiftU64 (Address, 32);\r
1434\r
1435 PciIo->Pci.Write (\r
1436 PciIo,\r
1437 EfiPciIoWidthUint32,\r
1438 ((Node->PciDev->VfPciBar[Node->Bar]).Offset + 4),\r
1439 1,\r
1440 &Address32\r
1441 );\r
1442\r
1443 Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;\r
1444\r
1445 DEBUG ((\r
1446 EFI_D_INFO,\r
1447 "PCI-IOV B%x.D%x.F%x - VF Bar (Offset - 0x%x) 64Mem (Address - 0x%lx)\n",\r
1448 (UINTN)Node->PciDev->BusNumber,\r
1449 (UINTN)Node->PciDev->DeviceNumber,\r
1450 (UINTN)Node->PciDev->FunctionNumber,\r
1451 (UINTN)(Node->PciDev->VfPciBar[Node->Bar]).Offset,\r
1452 (UINT64)Address\r
1453 ));\r
1454\r
1455 break;\r
1456\r
1457 case PciBarTypeIo16:\r
1458 case PciBarTypeIo32:\r
1459 break;\r
1460\r
1461 default:\r
1462 break;\r
1463 }\r
1464\r
1465 return EFI_SUCCESS;\r
1466}\r
1467\r
1468/**\r
1469 Program PCI-PCI bridge apperture.\r
1470\r
1471 @param Base Base address for resource.\r
1472 @param Node Point to resoure node structure.\r
1473\r
1474**/\r
1475VOID\r
1476ProgramPpbApperture (\r
1477 IN UINT64 Base,\r
1478 IN PCI_RESOURCE_NODE *Node\r
1479 )\r
1480{\r
1481 EFI_PCI_IO_PROTOCOL *PciIo;\r
1482 UINT64 Address;\r
1483 UINT32 Address32;\r
1484\r
1485 Address = 0;\r
1486 //\r
1487 // If no device resource of this PPB, return anyway\r
1488 // Apperture is set default in the initialization code\r
1489 //\r
1490 if (Node->Length == 0 || Node->ResourceUsage == PciResUsagePadding) {\r
1491 //\r
1492 // For padding resource node, just ignore when programming\r
1493 //\r
1494 return ;\r
1495 }\r
1496\r
1497 PciIo = &(Node->PciDev->PciIo);\r
1498 Address = Base + Node->Offset;\r
1499\r
1500 //\r
1501 // Indicate the PPB resource has been allocated\r
1502 //\r
1503 Node->PciDev->Allocated = TRUE;\r
1504\r
1505 switch (Node->Bar) {\r
1506\r
1507 case PPB_BAR_0:\r
1508 case PPB_BAR_1:\r
1509 PciIo->Pci.Write (\r
1510 PciIo,\r
1511 EfiPciIoWidthUint32,\r
1512 (Node->PciDev->PciBar[Node->Bar]).Offset,\r
1513 1,\r
1514 &Address\r
1515 );\r
1516\r
1517 Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
1518 Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
1519\r
1520 break;\r
1521\r
1522 case PPB_IO_RANGE:\r
1523\r
1524 Address32 = ((UINT32) (Address)) >> 8;\r
1525 PciIo->Pci.Write (\r
1526 PciIo,\r
1527 EfiPciIoWidthUint8,\r
1528 0x1C,\r
1529 1,\r
1530 &Address32\r
1531 );\r
1532\r
1533 Address32 >>= 8;\r
1534 PciIo->Pci.Write (\r
1535 PciIo,\r
1536 EfiPciIoWidthUint16,\r
1537 0x30,\r
1538 1,\r
1539 &Address32\r
1540 );\r
1541\r
1542 Address32 = (UINT32) (Address + Node->Length - 1);\r
1543 Address32 = ((UINT32) (Address32)) >> 8;\r
1544 PciIo->Pci.Write (\r
1545 PciIo,\r
1546 EfiPciIoWidthUint8,\r
1547 0x1D,\r
1548 1,\r
1549 &Address32\r
1550 );\r
1551\r
1552 Address32 >>= 8;\r
1553 PciIo->Pci.Write (\r
1554 PciIo,\r
1555 EfiPciIoWidthUint16,\r
1556 0x32,\r
1557 1,\r
1558 &Address32\r
1559 );\r
1560\r
1561 Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
1562 Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
1563 break;\r
1564\r
1565 case PPB_MEM32_RANGE:\r
1566\r
1567 Address32 = ((UINT32) (Address)) >> 16;\r
1568 PciIo->Pci.Write (\r
1569 PciIo,\r
1570 EfiPciIoWidthUint16,\r
1571 0x20,\r
1572 1,\r
1573 &Address32\r
1574 );\r
1575\r
1576 Address32 = (UINT32) (Address + Node->Length - 1);\r
1577 Address32 = ((UINT32) (Address32)) >> 16;\r
1578 PciIo->Pci.Write (\r
1579 PciIo,\r
1580 EfiPciIoWidthUint16,\r
1581 0x22,\r
1582 1,\r
1583 &Address32\r
1584 );\r
1585\r
1586 Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
1587 Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
1588 break;\r
1589\r
1590 case PPB_PMEM32_RANGE:\r
1591 case PPB_PMEM64_RANGE:\r
1592\r
1593 Address32 = ((UINT32) (Address)) >> 16;\r
1594 PciIo->Pci.Write (\r
1595 PciIo,\r
1596 EfiPciIoWidthUint16,\r
1597 0x24,\r
1598 1,\r
1599 &Address32\r
1600 );\r
1601\r
1602 Address32 = (UINT32) (Address + Node->Length - 1);\r
1603 Address32 = ((UINT32) (Address32)) >> 16;\r
1604 PciIo->Pci.Write (\r
1605 PciIo,\r
1606 EfiPciIoWidthUint16,\r
1607 0x26,\r
1608 1,\r
1609 &Address32\r
1610 );\r
1611\r
1612 Address32 = (UINT32) RShiftU64 (Address, 32);\r
1613 PciIo->Pci.Write (\r
1614 PciIo,\r
1615 EfiPciIoWidthUint32,\r
1616 0x28,\r
1617 1,\r
1618 &Address32\r
1619 );\r
1620\r
1621 Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32);\r
1622 PciIo->Pci.Write (\r
1623 PciIo,\r
1624 EfiPciIoWidthUint32,\r
1625 0x2C,\r
1626 1,\r
1627 &Address32\r
1628 );\r
1629\r
1630 Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
1631 Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
1632 break;\r
1633\r
1634 default:\r
1635 break;\r
1636 }\r
1637}\r
1638\r
1639/**\r
1640 Program parent bridge for Option Rom.\r
1641\r
1642 @param PciDevice Pci deivce instance.\r
1643 @param OptionRomBase Base address for Optiona Rom.\r
1644 @param Enable Enable or disable PCI memory.\r
1645\r
1646**/\r
1647VOID\r
1648ProgrameUpstreamBridgeForRom (\r
1649 IN PCI_IO_DEVICE *PciDevice,\r
1650 IN UINT32 OptionRomBase,\r
1651 IN BOOLEAN Enable\r
1652 )\r
1653{\r
1654 PCI_IO_DEVICE *Parent;\r
1655 PCI_RESOURCE_NODE Node;\r
1656 //\r
1657 // For root bridge, just return.\r
1658 //\r
1659 Parent = PciDevice->Parent;\r
1660 ZeroMem (&Node, sizeof (Node));\r
1661 while (Parent != NULL) {\r
1662 if (!IS_PCI_BRIDGE (&Parent->Pci)) {\r
1663 break;\r
1664 }\r
1665\r
1666 Node.PciDev = Parent;\r
1667 Node.Length = PciDevice->RomSize;\r
1668 Node.Alignment = 0;\r
1669 Node.Bar = PPB_MEM32_RANGE;\r
1670 Node.ResType = PciBarTypeMem32;\r
1671 Node.Offset = 0;\r
1672\r
1673 //\r
1674 // Program PPB to only open a single <= 16MB apperture\r
1675 //\r
1676 if (Enable) {\r
1677 ProgramPpbApperture (OptionRomBase, &Node);\r
1678 PCI_ENABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
1679 } else {\r
1680 InitializePpb (Parent);\r
1681 PCI_DISABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
1682 }\r
1683\r
1684 Parent = Parent->Parent;\r
1685 }\r
1686}\r
1687\r
1688/**\r
1689 Test whether resource exists for a bridge.\r
1690\r
1691 @param Bridge Point to resource node for a bridge.\r
1692\r
1693 @retval TRUE There is resource on the given bridge.\r
1694 @retval FALSE There isn't resource on the given bridge.\r
1695\r
1696**/\r
1697BOOLEAN\r
1698ResourceRequestExisted (\r
1699 IN PCI_RESOURCE_NODE *Bridge\r
1700 )\r
1701{\r
1702 if (Bridge != NULL) {\r
1703 if (!IsListEmpty (&Bridge->ChildList) || Bridge->Length != 0) {\r
1704 return TRUE;\r
1705 }\r
1706 }\r
1707\r
1708 return FALSE;\r
1709}\r
1710\r
1711/**\r
1712 Initialize resource pool structure.\r
1713\r
1714 @param ResourcePool Point to resource pool structure. This pool\r
1715 is reset to all zero when returned.\r
1716 @param ResourceType Type of resource.\r
1717\r
1718**/\r
1719VOID\r
1720InitializeResourcePool (\r
1721 IN OUT PCI_RESOURCE_NODE *ResourcePool,\r
1722 IN PCI_BAR_TYPE ResourceType\r
1723 )\r
1724{\r
1725 ZeroMem (ResourcePool, sizeof (PCI_RESOURCE_NODE));\r
1726 ResourcePool->ResType = ResourceType;\r
1727 ResourcePool->Signature = PCI_RESOURCE_SIGNATURE;\r
1728 InitializeListHead (&ResourcePool->ChildList);\r
1729}\r
1730\r
1731\r
1732/**\r
1733 Get all resource information for given Pci device.\r
1734\r
1735 @param PciDev Pci device instance.\r
1736 @param IoBridge Io resource node.\r
1737 @param Mem32Bridge 32-bit memory node.\r
1738 @param PMem32Bridge 32-bit Pmemory node.\r
1739 @param Mem64Bridge 64-bit memory node.\r
1740 @param PMem64Bridge 64-bit PMemory node.\r
1741 @param IoPool Link list header for Io resource.\r
1742 @param Mem32Pool Link list header for 32-bit memory.\r
1743 @param PMem32Pool Link list header for 32-bit Prefetchable memory.\r
1744 @param Mem64Pool Link list header for 64-bit memory.\r
1745 @param PMem64Pool Link list header for 64-bit Prefetchable memory.\r
1746\r
1747**/\r
1748VOID\r
1749GetResourceMap (\r
1750 IN PCI_IO_DEVICE *PciDev,\r
1751 IN PCI_RESOURCE_NODE **IoBridge,\r
1752 IN PCI_RESOURCE_NODE **Mem32Bridge,\r
1753 IN PCI_RESOURCE_NODE **PMem32Bridge,\r
1754 IN PCI_RESOURCE_NODE **Mem64Bridge,\r
1755 IN PCI_RESOURCE_NODE **PMem64Bridge,\r
1756 IN PCI_RESOURCE_NODE *IoPool,\r
1757 IN PCI_RESOURCE_NODE *Mem32Pool,\r
1758 IN PCI_RESOURCE_NODE *PMem32Pool,\r
1759 IN PCI_RESOURCE_NODE *Mem64Pool,\r
1760 IN PCI_RESOURCE_NODE *PMem64Pool\r
1761 )\r
1762{\r
1763\r
1764 PCI_RESOURCE_NODE *Temp;\r
1765 LIST_ENTRY *CurrentLink;\r
1766\r
1767 CurrentLink = IoPool->ChildList.ForwardLink;\r
1768\r
1769 //\r
1770 // Get Io resource map\r
1771 //\r
1772 while (CurrentLink != &IoPool->ChildList) {\r
1773\r
1774 Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
1775\r
1776 if (Temp->PciDev == PciDev) {\r
1777 *IoBridge = Temp;\r
1778 }\r
1779\r
1780 CurrentLink = CurrentLink->ForwardLink;\r
1781 }\r
1782\r
1783 //\r
1784 // Get Mem32 resource map\r
1785 //\r
1786 CurrentLink = Mem32Pool->ChildList.ForwardLink;\r
1787\r
1788 while (CurrentLink != &Mem32Pool->ChildList) {\r
1789\r
1790 Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
1791\r
1792 if (Temp->PciDev == PciDev) {\r
1793 *Mem32Bridge = Temp;\r
1794 }\r
1795\r
1796 CurrentLink = CurrentLink->ForwardLink;\r
1797 }\r
1798\r
1799 //\r
1800 // Get Pmem32 resource map\r
1801 //\r
1802 CurrentLink = PMem32Pool->ChildList.ForwardLink;\r
1803\r
1804 while (CurrentLink != &PMem32Pool->ChildList) {\r
1805\r
1806 Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
1807\r
1808 if (Temp->PciDev == PciDev) {\r
1809 *PMem32Bridge = Temp;\r
1810 }\r
1811\r
1812 CurrentLink = CurrentLink->ForwardLink;\r
1813 }\r
1814\r
1815 //\r
1816 // Get Mem64 resource map\r
1817 //\r
1818 CurrentLink = Mem64Pool->ChildList.ForwardLink;\r
1819\r
1820 while (CurrentLink != &Mem64Pool->ChildList) {\r
1821\r
1822 Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
1823\r
1824 if (Temp->PciDev == PciDev) {\r
1825 *Mem64Bridge = Temp;\r
1826 }\r
1827\r
1828 CurrentLink = CurrentLink->ForwardLink;\r
1829 }\r
1830\r
1831 //\r
1832 // Get Pmem64 resource map\r
1833 //\r
1834 CurrentLink = PMem64Pool->ChildList.ForwardLink;\r
1835\r
1836 while (CurrentLink != &PMem64Pool->ChildList) {\r
1837\r
1838 Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
1839\r
1840 if (Temp->PciDev == PciDev) {\r
1841 *PMem64Bridge = Temp;\r
1842 }\r
1843\r
1844 CurrentLink = CurrentLink->ForwardLink;\r
1845 }\r
1846}\r
1847\r
1848/**\r
1849 Destory given resource tree.\r
1850\r
1851 @param Bridge PCI resource root node of resource tree.\r
1852\r
1853**/\r
1854VOID\r
1855DestroyResourceTree (\r
1856 IN PCI_RESOURCE_NODE *Bridge\r
1857 )\r
1858{\r
1859 PCI_RESOURCE_NODE *Temp;\r
1860 LIST_ENTRY *CurrentLink;\r
1861\r
1862 while (!IsListEmpty (&Bridge->ChildList)) {\r
1863\r
1864 CurrentLink = Bridge->ChildList.ForwardLink;\r
1865\r
1866 Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
1867 ASSERT (Temp);\r
1868\r
1869 RemoveEntryList (CurrentLink);\r
1870\r
1871 if (IS_PCI_BRIDGE (&(Temp->PciDev->Pci))) {\r
1872 DestroyResourceTree (Temp);\r
1873 }\r
1874\r
1875 FreePool (Temp);\r
1876 }\r
1877}\r
1878\r
1879/**\r
1880 Insert resource padding for P2C.\r
1881\r
1882 @param PciDev Pci device instance.\r
1883 @param IoNode Resource info node for IO.\r
1884 @param Mem32Node Resource info node for 32-bit memory.\r
1885 @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
1886 @param Mem64Node Resource info node for 64-bit memory.\r
1887 @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
1888\r
1889**/\r
1890VOID\r
1891ResourcePaddingForCardBusBridge (\r
1892 IN PCI_IO_DEVICE *PciDev,\r
1893 IN PCI_RESOURCE_NODE *IoNode,\r
1894 IN PCI_RESOURCE_NODE *Mem32Node,\r
1895 IN PCI_RESOURCE_NODE *PMem32Node,\r
1896 IN PCI_RESOURCE_NODE *Mem64Node,\r
1897 IN PCI_RESOURCE_NODE *PMem64Node\r
1898 )\r
1899{\r
1900 PCI_RESOURCE_NODE *Node;\r
1901\r
1902 Node = NULL;\r
1903\r
1904 //\r
1905 // Memory Base/Limit Register 0\r
1906 // Bar 1 denodes memory range 0\r
1907 //\r
1908 Node = CreateResourceNode (\r
1909 PciDev,\r
1910 0x2000000,\r
1911 0x1ffffff,\r
1912 1,\r
1913 PciBarTypeMem32,\r
1914 PciResUsagePadding\r
1915 );\r
1916\r
1917 InsertResourceNode (\r
1918 Mem32Node,\r
1919 Node\r
1920 );\r
1921\r
1922 //\r
1923 // Memory Base/Limit Register 1\r
1924 // Bar 2 denodes memory range1\r
1925 //\r
1926 Node = CreateResourceNode (\r
1927 PciDev,\r
1928 0x2000000,\r
1929 0x1ffffff,\r
1930 2,\r
1931 PciBarTypePMem32,\r
1932 PciResUsagePadding\r
1933 );\r
1934\r
1935 InsertResourceNode (\r
1936 PMem32Node,\r
1937 Node\r
1938 );\r
1939\r
1940 //\r
1941 // Io Base/Limit\r
1942 // Bar 3 denodes io range 0\r
1943 //\r
1944 Node = CreateResourceNode (\r
1945 PciDev,\r
1946 0x100,\r
1947 0xff,\r
1948 3,\r
1949 PciBarTypeIo16,\r
1950 PciResUsagePadding\r
1951 );\r
1952\r
1953 InsertResourceNode (\r
1954 IoNode,\r
1955 Node\r
1956 );\r
1957\r
1958 //\r
1959 // Io Base/Limit\r
1960 // Bar 4 denodes io range 0\r
1961 //\r
1962 Node = CreateResourceNode (\r
1963 PciDev,\r
1964 0x100,\r
1965 0xff,\r
1966 4,\r
1967 PciBarTypeIo16,\r
1968 PciResUsagePadding\r
1969 );\r
1970\r
1971 InsertResourceNode (\r
1972 IoNode,\r
1973 Node\r
1974 );\r
1975}\r
1976\r
1977/**\r
1978 Program PCI Card device register for given resource node.\r
1979\r
1980 @param Base Base address of PCI Card device to be programmed.\r
1981 @param Node Given resource node.\r
1982\r
1983**/\r
1984VOID\r
1985ProgramP2C (\r
1986 IN UINT64 Base,\r
1987 IN PCI_RESOURCE_NODE *Node\r
1988 )\r
1989{\r
1990 EFI_PCI_IO_PROTOCOL *PciIo;\r
1991 UINT64 Address;\r
1992 UINT64 TempAddress;\r
1993 UINT16 BridgeControl;\r
1994\r
1995 Address = 0;\r
1996 PciIo = &(Node->PciDev->PciIo);\r
1997\r
1998 Address = Base + Node->Offset;\r
1999\r
2000 //\r
2001 // Indicate pci bus driver has allocated\r
2002 // resource for this device\r
2003 // It might be a temporary solution here since\r
2004 // pci device could have multiple bar\r
2005 //\r
2006 Node->PciDev->Allocated = TRUE;\r
2007\r
2008 switch (Node->Bar) {\r
2009\r
2010 case P2C_BAR_0:\r
2011 PciIo->Pci.Write (\r
2012 PciIo,\r
2013 EfiPciIoWidthUint32,\r
2014 (Node->PciDev->PciBar[Node->Bar]).Offset,\r
2015 1,\r
2016 &Address\r
2017 );\r
2018\r
2019 Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
2020 Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
2021 break;\r
2022\r
2023 case P2C_MEM_1:\r
2024 PciIo->Pci.Write (\r
2025 PciIo,\r
2026 EfiPciIoWidthUint32,\r
2027 PCI_CARD_MEMORY_BASE_0,\r
2028 1,\r
2029 &Address\r
2030 );\r
2031\r
2032 TempAddress = Address + Node->Length - 1;\r
2033 PciIo->Pci.Write (\r
2034 PciIo,\r
2035 EfiPciIoWidthUint32,\r
2036 PCI_CARD_MEMORY_LIMIT_0,\r
2037 1,\r
2038 &TempAddress\r
2039 );\r
2040\r
2041 if (Node->ResType == PciBarTypeMem32) {\r
2042 //\r
2043 // Set non-prefetchable bit\r
2044 //\r
2045 PciIo->Pci.Read (\r
2046 PciIo,\r
2047 EfiPciIoWidthUint16,\r
2048 PCI_CARD_BRIDGE_CONTROL,\r
2049 1,\r
2050 &BridgeControl\r
2051 );\r
2052\r
2053 BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;\r
2054 PciIo->Pci.Write (\r
2055 PciIo,\r
2056 EfiPciIoWidthUint16,\r
2057 PCI_CARD_BRIDGE_CONTROL,\r
2058 1,\r
2059 &BridgeControl\r
2060 );\r
2061\r
2062 } else {\r
2063 //\r
2064 // Set pre-fetchable bit\r
2065 //\r
2066 PciIo->Pci.Read (\r
2067 PciIo,\r
2068 EfiPciIoWidthUint16,\r
2069 PCI_CARD_BRIDGE_CONTROL,\r
2070 1,\r
2071 &BridgeControl\r
2072 );\r
2073\r
2074 BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;\r
2075 PciIo->Pci.Write (\r
2076 PciIo,\r
2077 EfiPciIoWidthUint16,\r
2078 PCI_CARD_BRIDGE_CONTROL,\r
2079 1,\r
2080 &BridgeControl\r
2081 );\r
2082 }\r
2083\r
2084 Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
2085 Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
2086 Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;\r
2087\r
2088 break;\r
2089\r
2090 case P2C_MEM_2:\r
2091 PciIo->Pci.Write (\r
2092 PciIo,\r
2093 EfiPciIoWidthUint32,\r
2094 PCI_CARD_MEMORY_BASE_1,\r
2095 1,\r
2096 &Address\r
2097 );\r
2098\r
2099 TempAddress = Address + Node->Length - 1;\r
2100\r
2101 PciIo->Pci.Write (\r
2102 PciIo,\r
2103 EfiPciIoWidthUint32,\r
2104 PCI_CARD_MEMORY_LIMIT_1,\r
2105 1,\r
2106 &TempAddress\r
2107 );\r
2108\r
2109 if (Node->ResType == PciBarTypeMem32) {\r
2110\r
2111 //\r
2112 // Set non-prefetchable bit\r
2113 //\r
2114 PciIo->Pci.Read (\r
2115 PciIo,\r
2116 EfiPciIoWidthUint16,\r
2117 PCI_CARD_BRIDGE_CONTROL,\r
2118 1,\r
2119 &BridgeControl\r
2120 );\r
2121\r
2122 BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE);\r
2123 PciIo->Pci.Write (\r
2124 PciIo,\r
2125 EfiPciIoWidthUint16,\r
2126 PCI_CARD_BRIDGE_CONTROL,\r
2127 1,\r
2128 &BridgeControl\r
2129 );\r
2130\r
2131 } else {\r
2132\r
2133 //\r
2134 // Set pre-fetchable bit\r
2135 //\r
2136 PciIo->Pci.Read (\r
2137 PciIo,\r
2138 EfiPciIoWidthUint16,\r
2139 PCI_CARD_BRIDGE_CONTROL,\r
2140 1,\r
2141 &BridgeControl\r
2142 );\r
2143\r
2144 BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE;\r
2145 PciIo->Pci.Write (\r
2146 PciIo,\r
2147 EfiPciIoWidthUint16,\r
2148 PCI_CARD_BRIDGE_CONTROL,\r
2149 1,\r
2150 &BridgeControl\r
2151 );\r
2152 }\r
2153\r
2154 Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
2155 Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
2156 Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;\r
2157 break;\r
2158\r
2159 case P2C_IO_1:\r
2160 PciIo->Pci.Write (\r
2161 PciIo,\r
2162 EfiPciIoWidthUint32,\r
2163 PCI_CARD_IO_BASE_0_LOWER,\r
2164 1,\r
2165 &Address\r
2166 );\r
2167\r
2168 TempAddress = Address + Node->Length - 1;\r
2169 PciIo->Pci.Write (\r
2170 PciIo,\r
2171 EfiPciIoWidthUint32,\r
2172 PCI_CARD_IO_LIMIT_0_LOWER,\r
2173 1,\r
2174 &TempAddress\r
2175 );\r
2176\r
2177 Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
2178 Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
2179 Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;\r
2180\r
2181 break;\r
2182\r
2183 case P2C_IO_2:\r
2184 PciIo->Pci.Write (\r
2185 PciIo,\r
2186 EfiPciIoWidthUint32,\r
2187 PCI_CARD_IO_BASE_1_LOWER,\r
2188 1,\r
2189 &Address\r
2190 );\r
2191\r
2192 TempAddress = Address + Node->Length - 1;\r
2193 PciIo->Pci.Write (\r
2194 PciIo,\r
2195 EfiPciIoWidthUint32,\r
2196 PCI_CARD_IO_LIMIT_1_LOWER,\r
2197 1,\r
2198 &TempAddress\r
2199 );\r
2200\r
2201 Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
2202 Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
2203 Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;\r
2204 break;\r
2205\r
2206 default:\r
2207 break;\r
2208 }\r
2209}\r
2210\r
2211/**\r
2212 Create padding resource node.\r
2213\r
2214 @param PciDev Pci device instance.\r
2215 @param IoNode Resource info node for IO.\r
2216 @param Mem32Node Resource info node for 32-bit memory.\r
2217 @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
2218 @param Mem64Node Resource info node for 64-bit memory.\r
2219 @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
2220\r
2221**/\r
2222VOID\r
2223ApplyResourcePadding (\r
2224 IN PCI_IO_DEVICE *PciDev,\r
2225 IN PCI_RESOURCE_NODE *IoNode,\r
2226 IN PCI_RESOURCE_NODE *Mem32Node,\r
2227 IN PCI_RESOURCE_NODE *PMem32Node,\r
2228 IN PCI_RESOURCE_NODE *Mem64Node,\r
2229 IN PCI_RESOURCE_NODE *PMem64Node\r
2230 )\r
2231{\r
2232 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
2233 PCI_RESOURCE_NODE *Node;\r
2234 UINT8 DummyBarIndex;\r
2235\r
2236 DummyBarIndex = 0;\r
2237 Ptr = PciDev->ResourcePaddingDescriptors;\r
2238\r
2239 while (((EFI_ACPI_END_TAG_DESCRIPTOR *) Ptr)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
2240\r
2241 if (Ptr->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR && Ptr->ResType == ACPI_ADDRESS_SPACE_TYPE_IO) {\r
2242 if (Ptr->AddrLen != 0) {\r
2243\r
2244 Node = CreateResourceNode (\r
2245 PciDev,\r
2246 Ptr->AddrLen,\r
2247 Ptr->AddrRangeMax,\r
2248 DummyBarIndex,\r
2249 PciBarTypeIo16,\r
2250 PciResUsagePadding\r
2251 );\r
2252 InsertResourceNode (\r
2253 IoNode,\r
2254 Node\r
2255 );\r
2256 }\r
2257\r
2258 Ptr++;\r
2259 continue;\r
2260 }\r
2261\r
2262 if (Ptr->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR && Ptr->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {\r
2263\r
2264 if (Ptr->AddrSpaceGranularity == 32) {\r
2265\r
2266 //\r
2267 // prefechable\r
2268 //\r
2269 if (Ptr->SpecificFlag == 0x6) {\r
2270 if (Ptr->AddrLen != 0) {\r
2271 Node = CreateResourceNode (\r
2272 PciDev,\r
2273 Ptr->AddrLen,\r
2274 Ptr->AddrRangeMax,\r
2275 DummyBarIndex,\r
2276 PciBarTypePMem32,\r
2277 PciResUsagePadding\r
2278 );\r
2279 InsertResourceNode (\r
2280 PMem32Node,\r
2281 Node\r
2282 );\r
2283 }\r
2284\r
2285 Ptr++;\r
2286 continue;\r
2287 }\r
2288\r
2289 //\r
2290 // Non-prefechable\r
2291 //\r
2292 if (Ptr->SpecificFlag == 0) {\r
2293 if (Ptr->AddrLen != 0) {\r
2294 Node = CreateResourceNode (\r
2295 PciDev,\r
2296 Ptr->AddrLen,\r
2297 Ptr->AddrRangeMax,\r
2298 DummyBarIndex,\r
2299 PciBarTypeMem32,\r
2300 PciResUsagePadding\r
2301 );\r
2302 InsertResourceNode (\r
2303 Mem32Node,\r
2304 Node\r
2305 );\r
2306 }\r
2307\r
2308 Ptr++;\r
2309 continue;\r
2310 }\r
2311 }\r
2312\r
2313 if (Ptr->AddrSpaceGranularity == 64) {\r
2314\r
2315 //\r
2316 // prefechable\r
2317 //\r
2318 if (Ptr->SpecificFlag == 0x6) {\r
2319 if (Ptr->AddrLen != 0) {\r
2320 Node = CreateResourceNode (\r
2321 PciDev,\r
2322 Ptr->AddrLen,\r
2323 Ptr->AddrRangeMax,\r
2324 DummyBarIndex,\r
2325 PciBarTypePMem64,\r
2326 PciResUsagePadding\r
2327 );\r
2328 InsertResourceNode (\r
2329 PMem64Node,\r
2330 Node\r
2331 );\r
2332 }\r
2333\r
2334 Ptr++;\r
2335 continue;\r
2336 }\r
2337\r
2338 //\r
2339 // Non-prefechable\r
2340 //\r
2341 if (Ptr->SpecificFlag == 0) {\r
2342 if (Ptr->AddrLen != 0) {\r
2343 Node = CreateResourceNode (\r
2344 PciDev,\r
2345 Ptr->AddrLen,\r
2346 Ptr->AddrRangeMax,\r
2347 DummyBarIndex,\r
2348 PciBarTypeMem64,\r
2349 PciResUsagePadding\r
2350 );\r
2351 InsertResourceNode (\r
2352 Mem64Node,\r
2353 Node\r
2354 );\r
2355 }\r
2356\r
2357 Ptr++;\r
2358 continue;\r
2359 }\r
2360 }\r
2361 }\r
2362\r
2363 Ptr++;\r
2364 }\r
2365}\r
2366\r
2367/**\r
2368 Get padding resource for PCI-PCI bridge.\r
2369\r
2370 @param PciIoDevice PCI-PCI bridge device instance.\r
2371\r
2372 @note Feature flag PcdPciBusHotplugDeviceSupport determines\r
2373 whether need to pad resource for them.\r
2374**/\r
2375VOID\r
2376GetResourcePaddingPpb (\r
2377 IN PCI_IO_DEVICE *PciIoDevice\r
2378 )\r
2379{\r
2380 if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
2381 if (PciIoDevice->ResourcePaddingDescriptors == NULL) {\r
2382 GetResourcePaddingForHpb (PciIoDevice);\r
2383 }\r
2384 }\r
2385}\r
2386\r
EFI Development Kit II mirror for PVE