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48555339 FT |
1 | /** @file\r |
2 | This file provides some helper functions which are specific for EMMC device.\r | |
3 | \r | |
b5547b9c | 4 | Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.\r |
8c983d3e | 5 | Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r |
9d510e61 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
48555339 FT |
7 | \r |
8 | **/\r | |
9 | \r | |
10 | #include "SdMmcPciHcDxe.h"\r | |
11 | \r | |
12 | /**\r | |
13 | Send command GO_IDLE_STATE (CMD0 with argument of 0x00000000) to the device to\r | |
14 | make it go to Idle State.\r | |
15 | \r | |
16 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r | |
17 | \r | |
18 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
19 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
20 | \r | |
21 | @retval EFI_SUCCESS The EMMC device is reset correctly.\r | |
22 | @retval Others The device reset fails.\r | |
23 | \r | |
24 | **/\r | |
25 | EFI_STATUS\r | |
26 | EmmcReset (\r | |
27 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
28 | IN UINT8 Slot\r | |
29 | )\r | |
30 | {\r | |
31 | EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;\r | |
32 | EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;\r | |
33 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;\r | |
34 | EFI_STATUS Status;\r | |
35 | \r | |
36 | ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));\r | |
37 | ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));\r | |
38 | ZeroMem (&Packet, sizeof (Packet));\r | |
39 | \r | |
40 | Packet.SdMmcCmdBlk = &SdMmcCmdBlk;\r | |
41 | Packet.SdMmcStatusBlk = &SdMmcStatusBlk;\r | |
42 | Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;\r | |
43 | \r | |
44 | SdMmcCmdBlk.CommandIndex = EMMC_GO_IDLE_STATE;\r | |
45 | SdMmcCmdBlk.CommandType = SdMmcCommandTypeBc;\r | |
46 | SdMmcCmdBlk.ResponseType = 0;\r | |
47 | SdMmcCmdBlk.CommandArgument = 0;\r | |
48 | \r | |
9252d67a JZ |
49 | gBS->Stall (1000);\r |
50 | \r | |
48555339 FT |
51 | Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);\r |
52 | \r | |
53 | return Status;\r | |
54 | }\r | |
55 | \r | |
56 | /**\r | |
57 | Send command SEND_OP_COND to the EMMC device to get the data of the OCR register.\r | |
58 | \r | |
59 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r | |
60 | \r | |
61 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
62 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
63 | @param[in, out] Argument On input, the argument of SEND_OP_COND is to send to the device.\r | |
64 | On output, the argument is the value of OCR register.\r | |
65 | \r | |
66 | @retval EFI_SUCCESS The operation is done correctly.\r | |
67 | @retval Others The operation fails.\r | |
68 | \r | |
69 | **/\r | |
70 | EFI_STATUS\r | |
71 | EmmcGetOcr (\r | |
72 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
73 | IN UINT8 Slot,\r | |
74 | IN OUT UINT32 *Argument\r | |
75 | )\r | |
76 | {\r | |
77 | EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;\r | |
78 | EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;\r | |
79 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;\r | |
80 | EFI_STATUS Status;\r | |
81 | \r | |
82 | ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));\r | |
83 | ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));\r | |
84 | ZeroMem (&Packet, sizeof (Packet));\r | |
85 | \r | |
86 | Packet.SdMmcCmdBlk = &SdMmcCmdBlk;\r | |
87 | Packet.SdMmcStatusBlk = &SdMmcStatusBlk;\r | |
88 | Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;\r | |
89 | \r | |
90 | SdMmcCmdBlk.CommandIndex = EMMC_SEND_OP_COND;\r | |
91 | SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr;\r | |
92 | SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR3;\r | |
93 | SdMmcCmdBlk.CommandArgument = *Argument;\r | |
94 | \r | |
95 | Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);\r | |
96 | if (!EFI_ERROR (Status)) {\r | |
97 | //\r | |
98 | // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.\r | |
99 | //\r | |
100 | *Argument = SdMmcStatusBlk.Resp0;\r | |
101 | }\r | |
102 | \r | |
103 | return Status;\r | |
104 | }\r | |
105 | \r | |
106 | /**\r | |
107 | Broadcast command ALL_SEND_CID to the bus to ask all the EMMC devices to send the\r | |
108 | data of their CID registers.\r | |
109 | \r | |
110 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r | |
111 | \r | |
112 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
113 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
114 | \r | |
115 | @retval EFI_SUCCESS The operation is done correctly.\r | |
116 | @retval Others The operation fails.\r | |
117 | \r | |
118 | **/\r | |
119 | EFI_STATUS\r | |
120 | EmmcGetAllCid (\r | |
121 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
122 | IN UINT8 Slot\r | |
123 | )\r | |
124 | {\r | |
125 | EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;\r | |
126 | EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;\r | |
127 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;\r | |
128 | EFI_STATUS Status;\r | |
129 | \r | |
130 | ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));\r | |
131 | ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));\r | |
132 | ZeroMem (&Packet, sizeof (Packet));\r | |
133 | \r | |
134 | Packet.SdMmcCmdBlk = &SdMmcCmdBlk;\r | |
135 | Packet.SdMmcStatusBlk = &SdMmcStatusBlk;\r | |
136 | Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;\r | |
137 | \r | |
138 | SdMmcCmdBlk.CommandIndex = EMMC_ALL_SEND_CID;\r | |
139 | SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr;\r | |
140 | SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;\r | |
141 | SdMmcCmdBlk.CommandArgument = 0;\r | |
142 | \r | |
143 | Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);\r | |
144 | \r | |
145 | return Status;\r | |
146 | }\r | |
147 | \r | |
148 | /**\r | |
149 | Send command SET_RELATIVE_ADDR to the EMMC device to assign a Relative device\r | |
150 | Address (RCA).\r | |
151 | \r | |
152 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r | |
153 | \r | |
154 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
155 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
156 | @param[in] Rca The relative device address to be assigned.\r | |
157 | \r | |
158 | @retval EFI_SUCCESS The operation is done correctly.\r | |
159 | @retval Others The operation fails.\r | |
160 | \r | |
161 | **/\r | |
162 | EFI_STATUS\r | |
163 | EmmcSetRca (\r | |
164 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
165 | IN UINT8 Slot,\r | |
166 | IN UINT16 Rca\r | |
167 | )\r | |
168 | {\r | |
169 | EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;\r | |
170 | EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;\r | |
171 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;\r | |
172 | EFI_STATUS Status;\r | |
173 | \r | |
174 | ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));\r | |
175 | ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));\r | |
176 | ZeroMem (&Packet, sizeof (Packet));\r | |
177 | \r | |
178 | Packet.SdMmcCmdBlk = &SdMmcCmdBlk;\r | |
179 | Packet.SdMmcStatusBlk = &SdMmcStatusBlk;\r | |
180 | Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;\r | |
181 | \r | |
182 | SdMmcCmdBlk.CommandIndex = EMMC_SET_RELATIVE_ADDR;\r | |
183 | SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;\r | |
184 | SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;\r | |
185 | SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;\r | |
186 | \r | |
187 | Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);\r | |
188 | \r | |
189 | return Status;\r | |
190 | }\r | |
191 | \r | |
192 | /**\r | |
193 | Send command SEND_CSD to the EMMC device to get the data of the CSD register.\r | |
194 | \r | |
195 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r | |
196 | \r | |
197 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
198 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
199 | @param[in] Rca The relative device address of selected device.\r | |
200 | @param[out] Csd The buffer to store the content of the CSD register.\r | |
201 | Note the caller should ignore the lowest byte of this\r | |
202 | buffer as the content of this byte is meaningless even\r | |
203 | if the operation succeeds.\r | |
204 | \r | |
205 | @retval EFI_SUCCESS The operation is done correctly.\r | |
206 | @retval Others The operation fails.\r | |
207 | \r | |
208 | **/\r | |
209 | EFI_STATUS\r | |
210 | EmmcGetCsd (\r | |
211 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
212 | IN UINT8 Slot,\r | |
213 | IN UINT16 Rca,\r | |
214 | OUT EMMC_CSD *Csd\r | |
215 | )\r | |
216 | {\r | |
217 | EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;\r | |
218 | EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;\r | |
219 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;\r | |
220 | EFI_STATUS Status;\r | |
221 | \r | |
222 | ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));\r | |
223 | ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));\r | |
224 | ZeroMem (&Packet, sizeof (Packet));\r | |
225 | \r | |
226 | Packet.SdMmcCmdBlk = &SdMmcCmdBlk;\r | |
227 | Packet.SdMmcStatusBlk = &SdMmcStatusBlk;\r | |
228 | Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;\r | |
229 | \r | |
230 | SdMmcCmdBlk.CommandIndex = EMMC_SEND_CSD;\r | |
231 | SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;\r | |
232 | SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;\r | |
233 | SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;\r | |
234 | \r | |
235 | Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);\r | |
236 | if (!EFI_ERROR (Status)) {\r | |
237 | //\r | |
238 | // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.\r | |
239 | //\r | |
240 | CopyMem (((UINT8*)Csd) + 1, &SdMmcStatusBlk.Resp0, sizeof (EMMC_CSD) - 1);\r | |
241 | }\r | |
242 | \r | |
243 | return Status;\r | |
244 | }\r | |
245 | \r | |
246 | /**\r | |
247 | Send command SELECT_DESELECT_CARD to the EMMC device to select/deselect it.\r | |
248 | \r | |
249 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r | |
250 | \r | |
251 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
252 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
253 | @param[in] Rca The relative device address of selected device.\r | |
254 | \r | |
255 | @retval EFI_SUCCESS The operation is done correctly.\r | |
256 | @retval Others The operation fails.\r | |
257 | \r | |
258 | **/\r | |
259 | EFI_STATUS\r | |
260 | EmmcSelect (\r | |
261 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
262 | IN UINT8 Slot,\r | |
263 | IN UINT16 Rca\r | |
264 | )\r | |
265 | {\r | |
266 | EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;\r | |
267 | EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;\r | |
268 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;\r | |
269 | EFI_STATUS Status;\r | |
270 | \r | |
271 | ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));\r | |
272 | ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));\r | |
273 | ZeroMem (&Packet, sizeof (Packet));\r | |
274 | \r | |
275 | Packet.SdMmcCmdBlk = &SdMmcCmdBlk;\r | |
276 | Packet.SdMmcStatusBlk = &SdMmcStatusBlk;\r | |
277 | Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;\r | |
278 | \r | |
279 | SdMmcCmdBlk.CommandIndex = EMMC_SELECT_DESELECT_CARD;\r | |
280 | SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;\r | |
281 | SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;\r | |
282 | SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;\r | |
283 | \r | |
284 | Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);\r | |
285 | \r | |
286 | return Status;\r | |
287 | }\r | |
288 | \r | |
289 | /**\r | |
290 | Send command SEND_EXT_CSD to the EMMC device to get the data of the EXT_CSD register.\r | |
291 | \r | |
292 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r | |
293 | \r | |
294 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
295 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
296 | @param[out] ExtCsd The buffer to store the content of the EXT_CSD register.\r | |
297 | \r | |
298 | @retval EFI_SUCCESS The operation is done correctly.\r | |
299 | @retval Others The operation fails.\r | |
300 | \r | |
301 | **/\r | |
302 | EFI_STATUS\r | |
303 | EmmcGetExtCsd (\r | |
304 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
305 | IN UINT8 Slot,\r | |
306 | OUT EMMC_EXT_CSD *ExtCsd\r | |
307 | )\r | |
308 | {\r | |
309 | EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;\r | |
310 | EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;\r | |
311 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;\r | |
312 | EFI_STATUS Status;\r | |
313 | \r | |
314 | ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));\r | |
315 | ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));\r | |
316 | ZeroMem (&Packet, sizeof (Packet));\r | |
317 | \r | |
318 | Packet.SdMmcCmdBlk = &SdMmcCmdBlk;\r | |
319 | Packet.SdMmcStatusBlk = &SdMmcStatusBlk;\r | |
320 | Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;\r | |
321 | \r | |
322 | SdMmcCmdBlk.CommandIndex = EMMC_SEND_EXT_CSD;\r | |
323 | SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc;\r | |
324 | SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;\r | |
325 | SdMmcCmdBlk.CommandArgument = 0x00000000;\r | |
326 | \r | |
327 | Packet.InDataBuffer = ExtCsd;\r | |
328 | Packet.InTransferLength = sizeof (EMMC_EXT_CSD);\r | |
329 | \r | |
330 | Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);\r | |
331 | return Status;\r | |
332 | }\r | |
333 | \r | |
334 | /**\r | |
335 | Send command SWITCH to the EMMC device to switch the mode of operation of the\r | |
336 | selected Device or modifies the EXT_CSD registers.\r | |
337 | \r | |
338 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r | |
339 | \r | |
340 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
341 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
342 | @param[in] Access The access mode of SWTICH command.\r | |
343 | @param[in] Index The offset of the field to be access.\r | |
344 | @param[in] Value The value to be set to the specified field of EXT_CSD register.\r | |
345 | @param[in] CmdSet The value of CmdSet field of EXT_CSD register.\r | |
346 | \r | |
347 | @retval EFI_SUCCESS The operation is done correctly.\r | |
348 | @retval Others The operation fails.\r | |
349 | \r | |
350 | **/\r | |
351 | EFI_STATUS\r | |
352 | EmmcSwitch (\r | |
353 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
354 | IN UINT8 Slot,\r | |
355 | IN UINT8 Access,\r | |
356 | IN UINT8 Index,\r | |
357 | IN UINT8 Value,\r | |
358 | IN UINT8 CmdSet\r | |
359 | )\r | |
360 | {\r | |
361 | EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;\r | |
362 | EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;\r | |
363 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;\r | |
364 | EFI_STATUS Status;\r | |
365 | \r | |
366 | ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));\r | |
367 | ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));\r | |
368 | ZeroMem (&Packet, sizeof (Packet));\r | |
369 | \r | |
370 | Packet.SdMmcCmdBlk = &SdMmcCmdBlk;\r | |
371 | Packet.SdMmcStatusBlk = &SdMmcStatusBlk;\r | |
372 | Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;\r | |
373 | \r | |
374 | SdMmcCmdBlk.CommandIndex = EMMC_SWITCH;\r | |
375 | SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;\r | |
376 | SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b;\r | |
377 | SdMmcCmdBlk.CommandArgument = (Access << 24) | (Index << 16) | (Value << 8) | CmdSet;\r | |
378 | \r | |
379 | Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);\r | |
380 | \r | |
381 | return Status;\r | |
382 | }\r | |
383 | \r | |
384 | /**\r | |
385 | Send command SEND_STATUS to the addressed EMMC device to get its status register.\r | |
386 | \r | |
387 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r | |
388 | \r | |
389 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
390 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
391 | @param[in] Rca The relative device address of addressed device.\r | |
392 | @param[out] DevStatus The returned device status.\r | |
393 | \r | |
394 | @retval EFI_SUCCESS The operation is done correctly.\r | |
395 | @retval Others The operation fails.\r | |
396 | \r | |
397 | **/\r | |
398 | EFI_STATUS\r | |
399 | EmmcSendStatus (\r | |
400 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
401 | IN UINT8 Slot,\r | |
402 | IN UINT16 Rca,\r | |
403 | OUT UINT32 *DevStatus\r | |
404 | )\r | |
405 | {\r | |
406 | EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;\r | |
407 | EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;\r | |
408 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;\r | |
409 | EFI_STATUS Status;\r | |
410 | \r | |
411 | ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));\r | |
412 | ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));\r | |
413 | ZeroMem (&Packet, sizeof (Packet));\r | |
414 | \r | |
415 | Packet.SdMmcCmdBlk = &SdMmcCmdBlk;\r | |
416 | Packet.SdMmcStatusBlk = &SdMmcStatusBlk;\r | |
417 | Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;\r | |
418 | \r | |
419 | SdMmcCmdBlk.CommandIndex = EMMC_SEND_STATUS;\r | |
420 | SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;\r | |
421 | SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;\r | |
422 | SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;\r | |
423 | \r | |
424 | Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);\r | |
425 | if (!EFI_ERROR (Status)) {\r | |
426 | *DevStatus = SdMmcStatusBlk.Resp0;\r | |
427 | }\r | |
428 | \r | |
429 | return Status;\r | |
430 | }\r | |
431 | \r | |
432 | /**\r | |
433 | Send command SEND_TUNING_BLOCK to the EMMC device for HS200 optimal sampling point\r | |
434 | detection.\r | |
435 | \r | |
436 | It may be sent up to 40 times until the host finishes the tuning procedure.\r | |
437 | \r | |
438 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 for details.\r | |
439 | \r | |
440 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
441 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
442 | @param[in] BusWidth The bus width to work.\r | |
443 | \r | |
444 | @retval EFI_SUCCESS The operation is done correctly.\r | |
445 | @retval Others The operation fails.\r | |
446 | \r | |
447 | **/\r | |
448 | EFI_STATUS\r | |
449 | EmmcSendTuningBlk (\r | |
450 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
451 | IN UINT8 Slot,\r | |
452 | IN UINT8 BusWidth\r | |
453 | )\r | |
454 | {\r | |
455 | EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;\r | |
456 | EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;\r | |
457 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;\r | |
458 | EFI_STATUS Status;\r | |
459 | UINT8 TuningBlock[128];\r | |
460 | \r | |
461 | ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));\r | |
462 | ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));\r | |
463 | ZeroMem (&Packet, sizeof (Packet));\r | |
464 | \r | |
465 | Packet.SdMmcCmdBlk = &SdMmcCmdBlk;\r | |
466 | Packet.SdMmcStatusBlk = &SdMmcStatusBlk;\r | |
467 | Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;\r | |
468 | \r | |
469 | SdMmcCmdBlk.CommandIndex = EMMC_SEND_TUNING_BLOCK;\r | |
470 | SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc;\r | |
471 | SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;\r | |
472 | SdMmcCmdBlk.CommandArgument = 0;\r | |
473 | \r | |
474 | Packet.InDataBuffer = TuningBlock;\r | |
475 | if (BusWidth == 8) {\r | |
476 | Packet.InTransferLength = sizeof (TuningBlock);\r | |
477 | } else {\r | |
478 | Packet.InTransferLength = 64;\r | |
479 | }\r | |
480 | \r | |
481 | Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);\r | |
482 | \r | |
483 | return Status;\r | |
484 | }\r | |
485 | \r | |
486 | /**\r | |
487 | Tunning the clock to get HS200 optimal sampling point.\r | |
488 | \r | |
489 | Command SEND_TUNING_BLOCK may be sent up to 40 times until the host finishes the\r | |
490 | tuning procedure.\r | |
491 | \r | |
492 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r | |
493 | Simplified Spec 3.0 Figure 2-29 for details.\r | |
494 | \r | |
495 | @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
496 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
497 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
498 | @param[in] BusWidth The bus width to work.\r | |
499 | \r | |
500 | @retval EFI_SUCCESS The operation is done correctly.\r | |
501 | @retval Others The operation fails.\r | |
502 | \r | |
503 | **/\r | |
504 | EFI_STATUS\r | |
505 | EmmcTuningClkForHs200 (\r | |
506 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
507 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
508 | IN UINT8 Slot,\r | |
509 | IN UINT8 BusWidth\r | |
510 | )\r | |
511 | {\r | |
512 | EFI_STATUS Status;\r | |
513 | UINT8 HostCtrl2;\r | |
514 | UINT8 Retry;\r | |
515 | \r | |
516 | //\r | |
517 | // Notify the host that the sampling clock tuning procedure starts.\r | |
518 | //\r | |
519 | HostCtrl2 = BIT6;\r | |
520 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
521 | if (EFI_ERROR (Status)) {\r | |
522 | return Status;\r | |
523 | }\r | |
524 | //\r | |
525 | // Ask the device to send a sequence of tuning blocks till the tuning procedure is done.\r | |
526 | //\r | |
527 | Retry = 0;\r | |
528 | do {\r | |
529 | Status = EmmcSendTuningBlk (PassThru, Slot, BusWidth);\r | |
530 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 531 | DEBUG ((DEBUG_ERROR, "EmmcTuningClkForHs200: Send tuning block fails with %r\n", Status));\r |
48555339 FT |
532 | return Status;\r |
533 | }\r | |
534 | \r | |
535 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);\r | |
536 | if (EFI_ERROR (Status)) {\r | |
537 | return Status;\r | |
538 | }\r | |
539 | \r | |
8c983d3e | 540 | if ((HostCtrl2 & (BIT6 | BIT7)) == 0) {\r |
48555339 FT |
541 | break;\r |
542 | }\r | |
8c983d3e FT |
543 | \r |
544 | if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {\r | |
545 | return EFI_SUCCESS;\r | |
546 | }\r | |
48555339 FT |
547 | } while (++Retry < 40);\r |
548 | \r | |
e27ccaba | 549 | DEBUG ((DEBUG_ERROR, "EmmcTuningClkForHs200: Send tuning block fails at %d times with HostCtrl2 %02x\n", Retry, HostCtrl2));\r |
8c983d3e FT |
550 | //\r |
551 | // Abort the tuning procedure and reset the tuning circuit.\r | |
552 | //\r | |
553 | HostCtrl2 = (UINT8)~(BIT6 | BIT7);\r | |
554 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
555 | if (EFI_ERROR (Status)) {\r | |
556 | return Status;\r | |
48555339 | 557 | }\r |
8c983d3e | 558 | return EFI_DEVICE_ERROR;\r |
48555339 FT |
559 | }\r |
560 | \r | |
561 | /**\r | |
562 | Switch the bus width to specified width.\r | |
563 | \r | |
564 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.9 and SD Host Controller\r | |
565 | Simplified Spec 3.0 Figure 3-7 for details.\r | |
566 | \r | |
567 | @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
568 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
569 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
570 | @param[in] Rca The relative device address to be assigned.\r | |
571 | @param[in] IsDdr If TRUE, use dual data rate data simpling method. Otherwise\r | |
572 | use single data rate data simpling method.\r | |
573 | @param[in] BusWidth The bus width to be set, it could be 4 or 8.\r | |
574 | \r | |
575 | @retval EFI_SUCCESS The operation is done correctly.\r | |
576 | @retval Others The operation fails.\r | |
577 | \r | |
578 | **/\r | |
579 | EFI_STATUS\r | |
580 | EmmcSwitchBusWidth (\r | |
581 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
582 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
583 | IN UINT8 Slot,\r | |
584 | IN UINT16 Rca,\r | |
585 | IN BOOLEAN IsDdr,\r | |
586 | IN UINT8 BusWidth\r | |
587 | )\r | |
588 | {\r | |
589 | EFI_STATUS Status;\r | |
590 | UINT8 Access;\r | |
591 | UINT8 Index;\r | |
592 | UINT8 Value;\r | |
593 | UINT8 CmdSet;\r | |
594 | UINT32 DevStatus;\r | |
595 | \r | |
596 | //\r | |
597 | // Write Byte, the Value field is written into the byte pointed by Index.\r | |
598 | //\r | |
599 | Access = 0x03;\r | |
600 | Index = OFFSET_OF (EMMC_EXT_CSD, BusWidth);\r | |
601 | if (BusWidth == 4) {\r | |
602 | Value = 1;\r | |
603 | } else if (BusWidth == 8) {\r | |
604 | Value = 2;\r | |
605 | } else {\r | |
606 | return EFI_INVALID_PARAMETER;\r | |
607 | }\r | |
608 | \r | |
609 | if (IsDdr) {\r | |
610 | Value += 4;\r | |
611 | }\r | |
612 | \r | |
613 | CmdSet = 0;\r | |
614 | Status = EmmcSwitch (PassThru, Slot, Access, Index, Value, CmdSet);\r | |
615 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 616 | DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: Switch to bus width %d fails with %r\n", BusWidth, Status));\r |
48555339 FT |
617 | return Status;\r |
618 | }\r | |
619 | \r | |
620 | Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);\r | |
621 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 622 | DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: Send status fails with %r\n", Status));\r |
48555339 FT |
623 | return Status;\r |
624 | }\r | |
625 | //\r | |
626 | // Check the switch operation is really successful or not.\r | |
627 | //\r | |
628 | if ((DevStatus & BIT7) != 0) {\r | |
e27ccaba | 629 | DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: The switch operation fails as DevStatus is 0x%08x\n", DevStatus));\r |
48555339 FT |
630 | return EFI_DEVICE_ERROR;\r |
631 | }\r | |
632 | \r | |
633 | Status = SdMmcHcSetBusWidth (PciIo, Slot, BusWidth);\r | |
634 | \r | |
635 | return Status;\r | |
636 | }\r | |
637 | \r | |
638 | /**\r | |
195f673f | 639 | Switch the bus timing and clock frequency.\r |
48555339 FT |
640 | \r |
641 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.6 and SD Host Controller\r | |
642 | Simplified Spec 3.0 Figure 3-3 for details.\r | |
643 | \r | |
644 | @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
645 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
646 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
647 | @param[in] Rca The relative device address to be assigned.\r | |
648 | @param[in] HsTiming The value to be written to HS_TIMING field of EXT_CSD register.\r | |
b7b803a6 | 649 | @param[in] Timing The bus mode timing indicator.\r |
48555339 FT |
650 | @param[in] ClockFreq The max clock frequency to be set, the unit is MHz.\r |
651 | \r | |
652 | @retval EFI_SUCCESS The operation is done correctly.\r | |
653 | @retval Others The operation fails.\r | |
654 | \r | |
655 | **/\r | |
656 | EFI_STATUS\r | |
195f673f | 657 | EmmcSwitchBusTiming (\r |
48555339 FT |
658 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
659 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
660 | IN UINT8 Slot,\r | |
661 | IN UINT16 Rca,\r | |
662 | IN UINT8 HsTiming,\r | |
b7b803a6 | 663 | IN SD_MMC_BUS_MODE Timing,\r |
48555339 FT |
664 | IN UINT32 ClockFreq\r |
665 | )\r | |
666 | {\r | |
667 | EFI_STATUS Status;\r | |
668 | UINT8 Access;\r | |
669 | UINT8 Index;\r | |
670 | UINT8 Value;\r | |
671 | UINT8 CmdSet;\r | |
672 | UINT32 DevStatus;\r | |
673 | SD_MMC_HC_PRIVATE_DATA *Private;\r | |
674 | \r | |
675 | Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);\r | |
676 | //\r | |
677 | // Write Byte, the Value field is written into the byte pointed by Index.\r | |
678 | //\r | |
679 | Access = 0x03;\r | |
680 | Index = OFFSET_OF (EMMC_EXT_CSD, HsTiming);\r | |
681 | Value = HsTiming;\r | |
682 | CmdSet = 0;\r | |
683 | \r | |
684 | Status = EmmcSwitch (PassThru, Slot, Access, Index, Value, CmdSet);\r | |
685 | if (EFI_ERROR (Status)) {\r | |
195f673f AM |
686 | DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Switch to hstiming %d fails with %r\n", HsTiming, Status));\r |
687 | return Status;\r | |
688 | }\r | |
689 | \r | |
690 | //\r | |
691 | // Convert the clock freq unit from MHz to KHz.\r | |
692 | //\r | |
693 | Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->BaseClkFreq[Slot], Private->ControllerVersion[Slot]);\r | |
694 | if (EFI_ERROR (Status)) {\r | |
48555339 FT |
695 | return Status;\r |
696 | }\r | |
697 | \r | |
698 | Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);\r | |
699 | if (EFI_ERROR (Status)) {\r | |
195f673f | 700 | DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Send status fails with %r\n", Status));\r |
48555339 FT |
701 | return Status;\r |
702 | }\r | |
703 | //\r | |
704 | // Check the switch operation is really successful or not.\r | |
705 | //\r | |
706 | if ((DevStatus & BIT7) != 0) {\r | |
195f673f | 707 | DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: The switch operation fails as DevStatus is 0x%08x\n", DevStatus));\r |
48555339 FT |
708 | return EFI_DEVICE_ERROR;\r |
709 | }\r | |
b7b803a6 TM |
710 | \r |
711 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
712 | Status = mOverride->NotifyPhase (\r | |
713 | Private->ControllerHandle,\r | |
714 | Slot,\r | |
715 | EdkiiSdMmcSwitchClockFreqPost,\r | |
716 | &Timing\r | |
717 | );\r | |
718 | if (EFI_ERROR (Status)) {\r | |
719 | DEBUG ((\r | |
720 | DEBUG_ERROR,\r | |
721 | "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",\r | |
722 | __FUNCTION__,\r | |
723 | Status\r | |
724 | ));\r | |
725 | return Status;\r | |
726 | }\r | |
727 | }\r | |
48555339 FT |
728 | \r |
729 | return Status;\r | |
730 | }\r | |
731 | \r | |
732 | /**\r | |
733 | Switch to the High Speed timing according to request.\r | |
734 | \r | |
735 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r | |
736 | Simplified Spec 3.0 Figure 2-29 for details.\r | |
737 | \r | |
738 | @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
739 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
740 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
741 | @param[in] Rca The relative device address to be assigned.\r | |
742 | @param[in] ClockFreq The max clock frequency to be set.\r | |
743 | @param[in] IsDdr If TRUE, use dual data rate data simpling method. Otherwise\r | |
744 | use single data rate data simpling method.\r | |
745 | @param[in] BusWidth The bus width to be set, it could be 4 or 8.\r | |
746 | \r | |
747 | @retval EFI_SUCCESS The operation is done correctly.\r | |
748 | @retval Others The operation fails.\r | |
749 | \r | |
750 | **/\r | |
751 | EFI_STATUS\r | |
752 | EmmcSwitchToHighSpeed (\r | |
753 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
754 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
755 | IN UINT8 Slot,\r | |
756 | IN UINT16 Rca,\r | |
757 | IN UINT32 ClockFreq,\r | |
758 | IN BOOLEAN IsDdr,\r | |
759 | IN UINT8 BusWidth\r | |
760 | )\r | |
761 | {\r | |
a4708009 TM |
762 | EFI_STATUS Status;\r |
763 | UINT8 HsTiming;\r | |
764 | UINT8 HostCtrl1;\r | |
765 | SD_MMC_BUS_MODE Timing;\r | |
766 | SD_MMC_HC_PRIVATE_DATA *Private;\r | |
767 | \r | |
768 | Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);\r | |
48555339 FT |
769 | \r |
770 | Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);\r | |
771 | if (EFI_ERROR (Status)) {\r | |
772 | return Status;\r | |
773 | }\r | |
774 | //\r | |
775 | // Set to Hight Speed timing\r | |
776 | //\r | |
777 | HostCtrl1 = BIT2;\r | |
778 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
779 | if (EFI_ERROR (Status)) {\r | |
780 | return Status;\r | |
781 | }\r | |
782 | \r | |
48555339 | 783 | if (IsDdr) {\r |
a4708009 | 784 | Timing = SdMmcMmcHsDdr;\r |
48555339 | 785 | } else if (ClockFreq == 52) {\r |
a4708009 | 786 | Timing = SdMmcMmcHsSdr;\r |
48555339 | 787 | } else {\r |
a4708009 | 788 | Timing = SdMmcMmcLegacy;\r |
48555339 | 789 | }\r |
a4708009 TM |
790 | \r |
791 | Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, Timing);\r | |
48555339 FT |
792 | if (EFI_ERROR (Status)) {\r |
793 | return Status;\r | |
794 | }\r | |
795 | \r | |
796 | HsTiming = 1;\r | |
195f673f | 797 | Status = EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, Timing, ClockFreq);\r |
48555339 FT |
798 | \r |
799 | return Status;\r | |
800 | }\r | |
801 | \r | |
802 | /**\r | |
803 | Switch to the HS200 timing according to request.\r | |
804 | \r | |
805 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r | |
806 | Simplified Spec 3.0 Figure 2-29 for details.\r | |
807 | \r | |
808 | @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
809 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
810 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
811 | @param[in] Rca The relative device address to be assigned.\r | |
812 | @param[in] ClockFreq The max clock frequency to be set.\r | |
813 | @param[in] BusWidth The bus width to be set, it could be 4 or 8.\r | |
814 | \r | |
815 | @retval EFI_SUCCESS The operation is done correctly.\r | |
816 | @retval Others The operation fails.\r | |
817 | \r | |
818 | **/\r | |
819 | EFI_STATUS\r | |
820 | EmmcSwitchToHS200 (\r | |
821 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
822 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
823 | IN UINT8 Slot,\r | |
824 | IN UINT16 Rca,\r | |
825 | IN UINT32 ClockFreq,\r | |
826 | IN UINT8 BusWidth\r | |
827 | )\r | |
828 | {\r | |
a4708009 TM |
829 | EFI_STATUS Status;\r |
830 | UINT8 HsTiming;\r | |
831 | UINT16 ClockCtrl;\r | |
832 | SD_MMC_BUS_MODE Timing;\r | |
833 | SD_MMC_HC_PRIVATE_DATA *Private;\r | |
834 | \r | |
835 | Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);\r | |
48555339 FT |
836 | \r |
837 | if ((BusWidth != 4) && (BusWidth != 8)) {\r | |
838 | return EFI_INVALID_PARAMETER;\r | |
839 | }\r | |
840 | \r | |
841 | Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, FALSE, BusWidth);\r | |
842 | if (EFI_ERROR (Status)) {\r | |
843 | return Status;\r | |
844 | }\r | |
845 | //\r | |
846 | // Set to HS200/SDR104 timing\r | |
847 | //\r | |
848 | //\r | |
849 | // Stop bus clock at first\r | |
850 | //\r | |
851 | Status = SdMmcHcStopClock (PciIo, Slot);\r | |
852 | if (EFI_ERROR (Status)) {\r | |
853 | return Status;\r | |
854 | }\r | |
a4708009 TM |
855 | \r |
856 | Timing = SdMmcMmcHs200;\r | |
857 | \r | |
858 | Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, Timing);\r | |
48555339 FT |
859 | if (EFI_ERROR (Status)) {\r |
860 | return Status;\r | |
861 | }\r | |
a4708009 | 862 | \r |
48555339 FT |
863 | //\r |
864 | // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit\r | |
865 | //\r | |
866 | Status = SdMmcHcWaitMmioSet (\r | |
867 | PciIo,\r | |
868 | Slot,\r | |
869 | SD_MMC_HC_CLOCK_CTRL,\r | |
870 | sizeof (ClockCtrl),\r | |
871 | BIT1,\r | |
872 | BIT1,\r | |
873 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
874 | );\r | |
875 | if (EFI_ERROR (Status)) {\r | |
876 | return Status;\r | |
877 | }\r | |
878 | //\r | |
879 | // Set SD Clock Enable in the Clock Control register to 1\r | |
880 | //\r | |
881 | ClockCtrl = BIT2;\r | |
882 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r | |
883 | \r | |
884 | HsTiming = 2;\r | |
195f673f | 885 | Status = EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, Timing, ClockFreq);\r |
48555339 FT |
886 | if (EFI_ERROR (Status)) {\r |
887 | return Status;\r | |
888 | }\r | |
889 | \r | |
890 | Status = EmmcTuningClkForHs200 (PciIo, PassThru, Slot, BusWidth);\r | |
891 | \r | |
892 | return Status;\r | |
893 | }\r | |
894 | \r | |
895 | /**\r | |
896 | Switch to the HS400 timing according to request.\r | |
897 | \r | |
898 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r | |
899 | Simplified Spec 3.0 Figure 2-29 for details.\r | |
900 | \r | |
901 | @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
902 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
903 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
904 | @param[in] Rca The relative device address to be assigned.\r | |
905 | @param[in] ClockFreq The max clock frequency to be set.\r | |
906 | \r | |
907 | @retval EFI_SUCCESS The operation is done correctly.\r | |
908 | @retval Others The operation fails.\r | |
909 | \r | |
910 | **/\r | |
911 | EFI_STATUS\r | |
912 | EmmcSwitchToHS400 (\r | |
913 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
914 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
915 | IN UINT8 Slot,\r | |
916 | IN UINT16 Rca,\r | |
917 | IN UINT32 ClockFreq\r | |
918 | )\r | |
919 | {\r | |
a4708009 TM |
920 | EFI_STATUS Status;\r |
921 | UINT8 HsTiming;\r | |
922 | SD_MMC_BUS_MODE Timing;\r | |
923 | SD_MMC_HC_PRIVATE_DATA *Private;\r | |
924 | \r | |
925 | Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);\r | |
48555339 FT |
926 | \r |
927 | Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, 8);\r | |
928 | if (EFI_ERROR (Status)) {\r | |
929 | return Status;\r | |
930 | }\r | |
931 | //\r | |
932 | // Set to Hight Speed timing and set the clock frequency to a value less than 52MHz.\r | |
933 | //\r | |
934 | HsTiming = 1;\r | |
195f673f | 935 | Status = EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, SdMmcMmcHsSdr, 52);\r |
48555339 FT |
936 | if (EFI_ERROR (Status)) {\r |
937 | return Status;\r | |
938 | }\r | |
939 | //\r | |
940 | // HS400 mode must use 8 data lines.\r | |
941 | //\r | |
942 | Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, TRUE, 8);\r | |
943 | if (EFI_ERROR (Status)) {\r | |
944 | return Status;\r | |
945 | }\r | |
a4708009 TM |
946 | \r |
947 | Timing = SdMmcMmcHs400;\r | |
948 | \r | |
949 | Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, Timing);\r | |
48555339 FT |
950 | if (EFI_ERROR (Status)) {\r |
951 | return Status;\r | |
952 | }\r | |
953 | \r | |
954 | HsTiming = 3;\r | |
195f673f | 955 | Status = EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, Timing, ClockFreq);\r |
48555339 FT |
956 | \r |
957 | return Status;\r | |
958 | }\r | |
959 | \r | |
960 | /**\r | |
961 | Switch the high speed timing according to request.\r | |
962 | \r | |
963 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r | |
964 | Simplified Spec 3.0 Figure 2-29 for details.\r | |
965 | \r | |
966 | @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
967 | @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r | |
968 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
969 | @param[in] Rca The relative device address to be assigned.\r | |
970 | \r | |
971 | @retval EFI_SUCCESS The operation is done correctly.\r | |
972 | @retval Others The operation fails.\r | |
973 | \r | |
974 | **/\r | |
975 | EFI_STATUS\r | |
976 | EmmcSetBusMode (\r | |
977 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
978 | IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r | |
979 | IN UINT8 Slot,\r | |
980 | IN UINT16 Rca\r | |
981 | )\r | |
982 | {\r | |
983 | EFI_STATUS Status;\r | |
984 | EMMC_CSD Csd;\r | |
985 | EMMC_EXT_CSD ExtCsd;\r | |
986 | UINT8 HsTiming;\r | |
987 | BOOLEAN IsDdr;\r | |
988 | UINT32 ClockFreq;\r | |
989 | UINT8 BusWidth;\r | |
990 | SD_MMC_HC_PRIVATE_DATA *Private;\r | |
991 | \r | |
992 | Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);\r | |
993 | \r | |
994 | Status = EmmcGetCsd (PassThru, Slot, Rca, &Csd);\r | |
995 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 996 | DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: GetCsd fails with %r\n", Status));\r |
48555339 FT |
997 | return Status;\r |
998 | }\r | |
999 | \r | |
1000 | Status = EmmcSelect (PassThru, Slot, Rca);\r | |
1001 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 1002 | DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: Select fails with %r\n", Status));\r |
48555339 FT |
1003 | return Status;\r |
1004 | }\r | |
1005 | \r | |
7f3b0bad | 1006 | ASSERT (Private->BaseClkFreq[Slot] != 0);\r |
48555339 FT |
1007 | //\r |
1008 | // Check if the Host Controller support 8bits bus width.\r | |
1009 | //\r | |
1010 | if (Private->Capability[Slot].BusWidth8 != 0) {\r | |
1011 | BusWidth = 8;\r | |
1012 | } else {\r | |
1013 | BusWidth = 4;\r | |
1014 | }\r | |
1015 | //\r | |
1016 | // Get Deivce_Type from EXT_CSD register.\r | |
1017 | //\r | |
1018 | Status = EmmcGetExtCsd (PassThru, Slot, &ExtCsd);\r | |
1019 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 1020 | DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: GetExtCsd fails with %r\n", Status));\r |
48555339 FT |
1021 | return Status;\r |
1022 | }\r | |
1023 | //\r | |
1024 | // Calculate supported bus speed/bus width/clock frequency.\r | |
1025 | //\r | |
1026 | HsTiming = 0;\r | |
1027 | IsDdr = FALSE;\r | |
1028 | ClockFreq = 0;\r | |
1029 | if (((ExtCsd.DeviceType & (BIT4 | BIT5)) != 0) && (Private->Capability[Slot].Sdr104 != 0)) {\r | |
1030 | HsTiming = 2;\r | |
1031 | IsDdr = FALSE;\r | |
1032 | ClockFreq = 200;\r | |
1033 | } else if (((ExtCsd.DeviceType & (BIT2 | BIT3)) != 0) && (Private->Capability[Slot].Ddr50 != 0)) {\r | |
1034 | HsTiming = 1;\r | |
1035 | IsDdr = TRUE;\r | |
1036 | ClockFreq = 52;\r | |
1037 | } else if (((ExtCsd.DeviceType & BIT1) != 0) && (Private->Capability[Slot].HighSpeed != 0)) {\r | |
1038 | HsTiming = 1;\r | |
1039 | IsDdr = FALSE;\r | |
1040 | ClockFreq = 52;\r | |
1041 | } else if (((ExtCsd.DeviceType & BIT0) != 0) && (Private->Capability[Slot].HighSpeed != 0)) {\r | |
1042 | HsTiming = 1;\r | |
1043 | IsDdr = FALSE;\r | |
1044 | ClockFreq = 26;\r | |
1045 | }\r | |
1046 | //\r | |
1047 | // Check if both of the device and the host controller support HS400 DDR mode.\r | |
1048 | //\r | |
1049 | if (((ExtCsd.DeviceType & (BIT6 | BIT7)) != 0) && (Private->Capability[Slot].Hs400 != 0)) {\r | |
1050 | //\r | |
1051 | // The host controller supports 8bits bus.\r | |
1052 | //\r | |
1053 | ASSERT (BusWidth == 8);\r | |
1054 | HsTiming = 3;\r | |
1055 | IsDdr = TRUE;\r | |
1056 | ClockFreq = 200;\r | |
1057 | }\r | |
1058 | \r | |
1059 | if ((ClockFreq == 0) || (HsTiming == 0)) {\r | |
1060 | //\r | |
1061 | // Continue using default setting.\r | |
1062 | //\r | |
1063 | return EFI_SUCCESS;\r | |
1064 | }\r | |
1065 | \r | |
e27ccaba | 1066 | DEBUG ((DEBUG_INFO, "EmmcSetBusMode: HsTiming %d ClockFreq %d BusWidth %d Ddr %a\n", HsTiming, ClockFreq, BusWidth, IsDdr ? "TRUE":"FALSE"));\r |
48555339 FT |
1067 | \r |
1068 | if (HsTiming == 3) {\r | |
1069 | //\r | |
1070 | // Execute HS400 timing switch procedure\r | |
1071 | //\r | |
1072 | Status = EmmcSwitchToHS400 (PciIo, PassThru, Slot, Rca, ClockFreq);\r | |
1073 | } else if (HsTiming == 2) {\r | |
1074 | //\r | |
1075 | // Execute HS200 timing switch procedure\r | |
1076 | //\r | |
1077 | Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, BusWidth);\r | |
1078 | } else {\r | |
1079 | //\r | |
1080 | // Execute High Speed timing switch procedure\r | |
1081 | //\r | |
91ff0f05 | 1082 | Status = EmmcSwitchToHighSpeed (PciIo, PassThru, Slot, Rca, ClockFreq, IsDdr, BusWidth);\r |
48555339 FT |
1083 | }\r |
1084 | \r | |
e27ccaba | 1085 | DEBUG ((DEBUG_INFO, "EmmcSetBusMode: Switch to %a %r\n", (HsTiming == 3) ? "HS400" : ((HsTiming == 2) ? "HS200" : "HighSpeed"), Status));\r |
48555339 FT |
1086 | \r |
1087 | return Status;\r | |
1088 | }\r | |
1089 | \r | |
1090 | /**\r | |
1091 | Execute EMMC device identification procedure.\r | |
1092 | \r | |
1093 | Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r | |
1094 | \r | |
1095 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1096 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1097 | \r | |
1098 | @retval EFI_SUCCESS There is a EMMC card.\r | |
1099 | @retval Others There is not a EMMC card.\r | |
1100 | \r | |
1101 | **/\r | |
1102 | EFI_STATUS\r | |
1103 | EmmcIdentification (\r | |
1104 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
1105 | IN UINT8 Slot\r | |
1106 | )\r | |
1107 | {\r | |
1108 | EFI_STATUS Status;\r | |
1109 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1110 | EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru;\r | |
1111 | UINT32 Ocr;\r | |
1112 | UINT16 Rca;\r | |
ec86d285 | 1113 | UINTN Retry;\r |
48555339 FT |
1114 | \r |
1115 | PciIo = Private->PciIo;\r | |
1116 | PassThru = &Private->PassThru;\r | |
1117 | \r | |
1118 | Status = EmmcReset (PassThru, Slot);\r | |
1119 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 1120 | DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd0 fails with %r\n", Status));\r |
48555339 FT |
1121 | return Status;\r |
1122 | }\r | |
1123 | \r | |
ec86d285 FT |
1124 | Ocr = 0;\r |
1125 | Retry = 0;\r | |
48555339 FT |
1126 | do {\r |
1127 | Status = EmmcGetOcr (PassThru, Slot, &Ocr);\r | |
1128 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 1129 | DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd1 fails with %r\n", Status));\r |
48555339 FT |
1130 | return Status;\r |
1131 | }\r | |
1132 | Ocr |= BIT30;\r | |
ec86d285 FT |
1133 | \r |
1134 | if (Retry++ == 100) {\r | |
1135 | DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd1 fails too many times\n"));\r | |
1136 | return EFI_DEVICE_ERROR;\r | |
1137 | }\r | |
1138 | gBS->Stall(10 * 1000);\r | |
48555339 FT |
1139 | } while ((Ocr & BIT31) == 0);\r |
1140 | \r | |
1141 | Status = EmmcGetAllCid (PassThru, Slot);\r | |
1142 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 1143 | DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd2 fails with %r\n", Status));\r |
48555339 FT |
1144 | return Status;\r |
1145 | }\r | |
1146 | //\r | |
1147 | // Slot starts from 0 and valid RCA starts from 1.\r | |
1148 | // Here we takes a simple formula to calculate the RCA.\r | |
1149 | // Don't support multiple devices on the slot, that is\r | |
1150 | // shared bus slot feature.\r | |
1151 | //\r | |
1152 | Rca = Slot + 1;\r | |
1153 | Status = EmmcSetRca (PassThru, Slot, Rca);\r | |
1154 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 1155 | DEBUG ((DEBUG_ERROR, "EmmcIdentification: Executing Cmd3 fails with %r\n", Status));\r |
48555339 FT |
1156 | return Status;\r |
1157 | }\r | |
1158 | //\r | |
1159 | // Enter Data Tranfer Mode.\r | |
1160 | //\r | |
e27ccaba | 1161 | DEBUG ((DEBUG_INFO, "EmmcIdentification: Found a EMMC device at slot [%d], RCA [%d]\n", Slot, Rca));\r |
48555339 FT |
1162 | Private->Slot[Slot].CardType = EmmcCardType;\r |
1163 | \r | |
1164 | Status = EmmcSetBusMode (PciIo, PassThru, Slot, Rca);\r | |
1165 | \r | |
1166 | return Status;\r | |
1167 | }\r | |
1168 | \r |