[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.h

/** @file\r
\r
  Provides some data structure definitions used by the SD/MMC host controller driver.\r
\r
Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.\r
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _SD_MMC_PCI_HCI_H_\r
#define _SD_MMC_PCI_HCI_H_\r
\r
//\r
// SD Host Controller SlotInfo Register Offset\r
//\r
#define SD_MMC_HC_SLOT_OFFSET         0x40\r
\r
#define SD_MMC_HC_MAX_SLOT            6\r
\r
//\r
// SD Host Controller MMIO Register Offset\r
//\r
#define SD_MMC_HC_SDMA_ADDR           0x00\r
#define SD_MMC_HC_ARG2                0x00\r
#define SD_MMC_HC_BLK_SIZE            0x04\r
#define SD_MMC_HC_BLK_COUNT           0x06\r
#define SD_MMC_HC_ARG1                0x08\r
#define SD_MMC_HC_TRANS_MOD           0x0C\r
#define SD_MMC_HC_COMMAND             0x0E\r
#define SD_MMC_HC_RESPONSE            0x10\r
#define SD_MMC_HC_BUF_DAT_PORT        0x20\r
#define SD_MMC_HC_PRESENT_STATE       0x24\r
#define SD_MMC_HC_HOST_CTRL1          0x28\r
#define SD_MMC_HC_POWER_CTRL          0x29\r
#define SD_MMC_HC_BLK_GAP_CTRL        0x2A\r
#define SD_MMC_HC_WAKEUP_CTRL         0x2B\r
#define SD_MMC_HC_CLOCK_CTRL          0x2C\r
#define SD_MMC_HC_TIMEOUT_CTRL        0x2E\r
#define SD_MMC_HC_SW_RST              0x2F\r
#define SD_MMC_HC_NOR_INT_STS         0x30\r
#define SD_MMC_HC_ERR_INT_STS         0x32\r
#define SD_MMC_HC_NOR_INT_STS_EN      0x34\r
#define SD_MMC_HC_ERR_INT_STS_EN      0x36\r
#define SD_MMC_HC_NOR_INT_SIG_EN      0x38\r
#define SD_MMC_HC_ERR_INT_SIG_EN      0x3A\r
#define SD_MMC_HC_AUTO_CMD_ERR_STS    0x3C\r
#define SD_MMC_HC_HOST_CTRL2          0x3E\r
#define SD_MMC_HC_CAP                 0x40\r
#define SD_MMC_HC_MAX_CURRENT_CAP     0x48\r
#define SD_MMC_HC_FORCE_EVT_AUTO_CMD  0x50\r
#define SD_MMC_HC_FORCE_EVT_ERR_INT   0x52\r
#define SD_MMC_HC_ADMA_ERR_STS        0x54\r
#define SD_MMC_HC_ADMA_SYS_ADDR       0x58\r
#define SD_MMC_HC_PRESET_VAL          0x60\r
#define SD_MMC_HC_SHARED_BUS_CTRL     0xE0\r
#define SD_MMC_HC_SLOT_INT_STS        0xFC\r
#define SD_MMC_HC_CTRL_VER            0xFE\r
\r
//\r
// SD Host Controller bits to HOST_CTRL2 register\r
//\r
#define SD_MMC_HC_CTRL_UHS_MASK       0x0007\r
#define SD_MMC_HC_CTRL_UHS_SDR12      0x0000\r
#define SD_MMC_HC_CTRL_UHS_SDR25      0x0001\r
#define SD_MMC_HC_CTRL_UHS_SDR50      0x0002\r
#define SD_MMC_HC_CTRL_UHS_SDR104     0x0003\r
#define SD_MMC_HC_CTRL_UHS_DDR50      0x0004\r
#define SD_MMC_HC_CTRL_MMC_LEGACY     0x0000\r
#define SD_MMC_HC_CTRL_MMC_HS_SDR     0x0001\r
#define SD_MMC_HC_CTRL_MMC_HS_DDR     0x0004\r
#define SD_MMC_HC_CTRL_MMC_HS200      0x0003\r
#define SD_MMC_HC_CTRL_MMC_HS400      0x0005\r
\r
#define SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK  0x0030\r
\r
//\r
// The transfer modes supported by SD Host Controller\r
//\r
typedef enum {\r
  SdMmcNoData,\r
  SdMmcPioMode,\r
  SdMmcSdmaMode,\r
  SdMmcAdma32bMode,\r
  SdMmcAdma64bV3Mode,\r
  SdMmcAdma64bV4Mode\r
} SD_MMC_HC_TRANSFER_MODE;\r
\r
//\r
// The ADMA transfer lengths supported by SD Host Controller\r
//\r
typedef enum {\r
  SdMmcAdmaLen16b,\r
  SdMmcAdmaLen26b\r
} SD_MMC_HC_ADMA_LENGTH_MODE;\r
\r
//\r
// The maximum data length of each descriptor line\r
//\r
#define ADMA_MAX_DATA_PER_LINE_16B     SIZE_64KB\r
#define ADMA_MAX_DATA_PER_LINE_26B     SIZE_64MB\r
\r
//\r
// ADMA descriptor for 32b addressing.\r
//\r
typedef struct {\r
  UINT32 Valid:1;\r
  UINT32 End:1;\r
  UINT32 Int:1;\r
  UINT32 Reserved:1;\r
  UINT32 Act:2;\r
  UINT32 UpperLength:10;\r
  UINT32 LowerLength:16;\r
  UINT32 Address;\r
} SD_MMC_HC_ADMA_32_DESC_LINE;\r
\r
//\r
// ADMA descriptor for 64b addressing.\r
//\r
typedef struct {\r
  UINT32 Valid:1;\r
  UINT32 End:1;\r
  UINT32 Int:1;\r
  UINT32 Reserved:1;\r
  UINT32 Act:2;\r
  UINT32 UpperLength:10;\r
  UINT32 LowerLength:16;\r
  UINT32 LowerAddress;\r
  UINT32 UpperAddress;\r
} SD_MMC_HC_ADMA_64_V3_DESC_LINE;\r
\r
typedef struct {\r
  UINT32 Valid:1;\r
  UINT32 End:1;\r
  UINT32 Int:1;\r
  UINT32 Reserved:1;\r
  UINT32 Act:2;\r
  UINT32 UpperLength:10;\r
  UINT32 LowerLength:16;\r
  UINT32 LowerAddress;\r
  UINT32 UpperAddress;\r
  UINT32 Reserved1;\r
} SD_MMC_HC_ADMA_64_V4_DESC_LINE;\r
\r
#define SD_MMC_SDMA_BOUNDARY          512 * 1024\r
#define SD_MMC_SDMA_ROUND_UP(x, n)    (((x) + n) & ~(n - 1))\r
\r
typedef struct {\r
  UINT8    FirstBar:3;        // bit 0:2\r
  UINT8    Reserved:1;        // bit 3\r
  UINT8    SlotNum:3;         // bit 4:6\r
  UINT8    Reserved1:1;       // bit 7\r
} SD_MMC_HC_SLOT_INFO;\r
\r
typedef struct {\r
  UINT32   TimeoutFreq:6;     // bit 0:5\r
  UINT32   Reserved:1;        // bit 6\r
  UINT32   TimeoutUnit:1;     // bit 7\r
  UINT32   BaseClkFreq:8;     // bit 8:15\r
  UINT32   MaxBlkLen:2;       // bit 16:17\r
  UINT32   BusWidth8:1;       // bit 18\r
  UINT32   Adma2:1;           // bit 19\r
  UINT32   Reserved2:1;       // bit 20\r
  UINT32   HighSpeed:1;       // bit 21\r
  UINT32   Sdma:1;            // bit 22\r
  UINT32   SuspRes:1;         // bit 23\r
  UINT32   Voltage33:1;       // bit 24\r
  UINT32   Voltage30:1;       // bit 25\r
  UINT32   Voltage18:1;       // bit 26\r
  UINT32   SysBus64V4:1;      // bit 27\r
  UINT32   SysBus64V3:1;      // bit 28\r
  UINT32   AsyncInt:1;        // bit 29\r
  UINT32   SlotType:2;        // bit 30:31\r
  UINT32   Sdr50:1;           // bit 32\r
  UINT32   Sdr104:1;          // bit 33\r
  UINT32   Ddr50:1;           // bit 34\r
  UINT32   Reserved3:1;       // bit 35\r
  UINT32   DriverTypeA:1;     // bit 36\r
  UINT32   DriverTypeC:1;     // bit 37\r
  UINT32   DriverTypeD:1;     // bit 38\r
  UINT32   DriverType4:1;     // bit 39\r
  UINT32   TimerCount:4;      // bit 40:43\r
  UINT32   Reserved4:1;       // bit 44\r
  UINT32   TuningSDR50:1;     // bit 45\r
  UINT32   RetuningMod:2;     // bit 46:47\r
  UINT32   ClkMultiplier:8;   // bit 48:55\r
  UINT32   Reserved5:7;       // bit 56:62\r
  UINT32   Hs400:1;           // bit 63\r
} SD_MMC_HC_SLOT_CAP;\r
\r
//\r
// SD Host controller version\r
//\r
#define SD_MMC_HC_CTRL_VER_100        0x00\r
#define SD_MMC_HC_CTRL_VER_200        0x01\r
#define SD_MMC_HC_CTRL_VER_300        0x02\r
#define SD_MMC_HC_CTRL_VER_400        0x03\r
#define SD_MMC_HC_CTRL_VER_410        0x04\r
#define SD_MMC_HC_CTRL_VER_420        0x05\r
\r
//\r
// SD Host controller V4 enhancements\r
//\r
#define SD_MMC_HC_V4_EN               BIT12\r
#define SD_MMC_HC_64_ADDR_EN          BIT13\r
#define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10\r
\r
/**\r
  Dump the content of SD/MMC host controller's Capability Register.\r
\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[in]  Capability      The buffer to store the capability data.\r
\r
**/\r
VOID\r
DumpCapabilityReg (\r
  IN UINT8                Slot,\r
  IN SD_MMC_HC_SLOT_CAP   *Capability\r
  );\r
\r
/**\r
  Read SlotInfo register from SD/MMC host controller pci config space.\r
\r
  @param[in]  PciIo        The PCI IO protocol instance.\r
  @param[out] FirstBar     The buffer to store the first BAR value.\r
  @param[out] SlotNum      The buffer to store the supported slot number.\r
\r
  @retval EFI_SUCCESS      The operation succeeds.\r
  @retval Others           The operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcGetSlotInfo (\r
  IN     EFI_PCI_IO_PROTOCOL   *PciIo,\r
     OUT UINT8                 *FirstBar,\r
     OUT UINT8                 *SlotNum\r
  );\r
\r
/**\r
  Read/Write specified SD/MMC host controller mmio register.\r
\r
  @param[in]      PciIo        The PCI IO protocol instance.\r
  @param[in]      BarIndex     The BAR index of the standard PCI Configuration\r
                               header to use as the base address for the memory\r
                               operation to perform.\r
  @param[in]      Offset       The offset within the selected BAR to start the\r
                               memory operation.\r
  @param[in]      Read         A boolean to indicate it's read or write operation.\r
  @param[in]      Count        The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in, out] Data         For read operations, the destination buffer to store\r
                               the results. For write operations, the source buffer\r
                               to write data from. The caller is responsible for\r
                               having ownership of the data buffer and ensuring its\r
                               size not less than Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.\r
  @retval EFI_SUCCESS           The read/write operation succeeds.\r
  @retval Others                The read/write operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcRwMmio (\r
  IN     EFI_PCI_IO_PROTOCOL   *PciIo,\r
  IN     UINT8                 BarIndex,\r
  IN     UINT32                Offset,\r
  IN     BOOLEAN               Read,\r
  IN     UINT8                 Count,\r
  IN OUT VOID                  *Data\r
  );\r
\r
/**\r
  Do OR operation with the value of the specified SD/MMC host controller mmio register.\r
\r
  @param[in] PciIo             The PCI IO protocol instance.\r
  @param[in] BarIndex          The BAR index of the standard PCI Configuration\r
                               header to use as the base address for the memory\r
                               operation to perform.\r
  @param[in] Offset            The offset within the selected BAR to start the\r
                               memory operation.\r
  @param[in] Count             The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in] OrData            The pointer to the data used to do OR operation.\r
                               The caller is responsible for having ownership of\r
                               the data buffer and ensuring its size not less than\r
                               Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.\r
  @retval EFI_SUCCESS           The OR operation succeeds.\r
  @retval Others                The OR operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcOrMmio (\r
  IN  EFI_PCI_IO_PROTOCOL      *PciIo,\r
  IN  UINT8                    BarIndex,\r
  IN  UINT32                   Offset,\r
  IN  UINT8                    Count,\r
  IN  VOID                     *OrData\r
  );\r
\r
/**\r
  Do AND operation with the value of the specified SD/MMC host controller mmio register.\r
\r
  @param[in] PciIo             The PCI IO protocol instance.\r
  @param[in] BarIndex          The BAR index of the standard PCI Configuration\r
                               header to use as the base address for the memory\r
                               operation to perform.\r
  @param[in] Offset            The offset within the selected BAR to start the\r
                               memory operation.\r
  @param[in] Count             The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in] AndData           The pointer to the data used to do AND operation.\r
                               The caller is responsible for having ownership of\r
                               the data buffer and ensuring its size not less than\r
                               Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.\r
  @retval EFI_SUCCESS           The AND operation succeeds.\r
  @retval Others                The AND operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcAndMmio (\r
  IN  EFI_PCI_IO_PROTOCOL      *PciIo,\r
  IN  UINT8                    BarIndex,\r
  IN  UINT32                   Offset,\r
  IN  UINT8                    Count,\r
  IN  VOID                     *AndData\r
  );\r
\r
/**\r
  Wait for the value of the specified MMIO register set to the test value.\r
\r
  @param[in]  PciIo         The PCI IO protocol instance.\r
  @param[in]  BarIndex      The BAR index of the standard PCI Configuration\r
                            header to use as the base address for the memory\r
                            operation to perform.\r
  @param[in]  Offset        The offset within the selected BAR to start the\r
                            memory operation.\r
  @param[in]  Count         The width of the mmio register in bytes.\r
                            Must be 1, 2, 4 or 8 bytes.\r
  @param[in]  MaskValue     The mask value of memory.\r
  @param[in]  TestValue     The test value of memory.\r
  @param[in]  Timeout       The time out value for wait memory set, uses 1\r
                            microsecond as a unit.\r
\r
  @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout\r
                            range.\r
  @retval EFI_SUCCESS       The MMIO register has expected value.\r
  @retval Others            The MMIO operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcWaitMmioSet (\r
  IN  EFI_PCI_IO_PROTOCOL       *PciIo,\r
  IN  UINT8                     BarIndex,\r
  IN  UINT32                    Offset,\r
  IN  UINT8                     Count,\r
  IN  UINT64                    MaskValue,\r
  IN  UINT64                    TestValue,\r
  IN  UINT64                    Timeout\r
  );\r
\r
/**\r
  Get the controller version information from the specified slot.\r
\r
  @param[in]  PciIo           The PCI IO protocol instance.\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[out] Version         The buffer to store the version information.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcGetControllerVersion (\r
  IN  EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN  UINT8                Slot,\r
  OUT UINT16               *Version\r
  );\r
\r
/**\r
  Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
  register.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       The operation executes successfully.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcEnableInterrupt (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot\r
  );\r
\r
/**\r
  Get the capability data from the specified slot.\r
\r
  @param[in]  PciIo           The PCI IO protocol instance.\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[out] Capability      The buffer to store the capability data.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcGetCapability (\r
  IN     EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN     UINT8                Slot,\r
     OUT SD_MMC_HC_SLOT_CAP   *Capability\r
  );\r
\r
/**\r
  Get the maximum current capability data from the specified slot.\r
\r
  @param[in]  PciIo           The PCI IO protocol instance.\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[out] MaxCurrent      The buffer to store the maximum current capability data.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcGetMaxCurrent (\r
  IN     EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN     UINT8                Slot,\r
     OUT UINT64               *MaxCurrent\r
  );\r
\r
/**\r
  Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller\r
  slot.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
\r
  @param[in]  PciIo         The PCI IO protocol instance.\r
  @param[in]  Slot          The slot number of the SD card to send the command to.\r
  @param[out] MediaPresent  The pointer to the media present boolean value.\r
\r
  @retval EFI_SUCCESS       There is no media change happened.\r
  @retval EFI_MEDIA_CHANGED There is media change happened.\r
  @retval Others            The detection fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcCardDetect (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
     OUT BOOLEAN            *MediaPresent\r
  );\r
\r
/**\r
  Stop SD/MMC card clock.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.\r
  @retval Others            Fail to stop SD/MMC clock.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcStopClock (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot\r
  );\r
\r
/**\r
  Start the SD clock.\r
\r
  @param[in] PciIo  The PCI IO protocol instance.\r
  @param[in] Slot   The slot number.\r
\r
  @retval EFI_SUCCESS  Succeeded to start the SD clock.\r
  @retval Others       Failed to start the SD clock.\r
**/\r
EFI_STATUS\r
SdMmcHcStartSdClock (\r
  IN EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN UINT8                Slot\r
  );\r
\r
/**\r
  SD/MMC bus power control.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] PowerCtrl      The value setting to the power control register.\r
\r
  @retval TRUE              There is a SD/MMC card attached.\r
  @retval FALSE             There is no a SD/MMC card attached.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcPowerControl (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT8                  PowerCtrl\r
  );\r
\r
/**\r
  Set the SD/MMC bus width.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.\r
\r
  @retval EFI_SUCCESS       The bus width is set successfully.\r
  @retval Others            The bus width isn't set successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcSetBusWidth (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT16                 BusWidth\r
  );\r
\r
/**\r
  Supply SD/MMC card with maximum voltage at initialization.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] Capability     The capability of the slot.\r
\r
  @retval EFI_SUCCESS       The voltage is supplied successfully.\r
  @retval Others            The voltage isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitPowerVoltage (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN SD_MMC_HC_SLOT_CAP     Capability\r
  );\r
\r
/**\r
  Initialize the Timeout Control register with most conservative value at initialization.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       The timeout control register is configured successfully.\r
  @retval Others            The timeout control register isn't configured successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitTimeoutCtrl (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot\r
  );\r
\r
/**\r
  Set SD Host Controller control 2 registry according to selected speed.\r
\r
  @param[in] ControllerHandle The handle of the controller.\r
  @param[in] PciIo            The PCI IO protocol instance.\r
  @param[in] Slot             The slot number of the SD card to send the command to.\r
  @param[in] Timing           The timing to select.\r
\r
  @retval EFI_SUCCESS         The timing is set successfully.\r
  @retval Others              The timing isn't set successfully.\r
**/\r
EFI_STATUS\r
SdMmcHcUhsSignaling (\r
  IN EFI_HANDLE             ControllerHandle,\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN SD_MMC_BUS_MODE        Timing\r
  );\r
\r
/**\r
  Set driver strength in host controller.\r
\r
  @param[in] PciIo           The PCI IO protocol instance.\r
  @param[in] SlotIndex       The slot index of the card.\r
  @param[in] DriverStrength  DriverStrength to set in the controller.\r
\r
  @retval EFI_SUCCESS  Driver strength programmed successfully.\r
  @retval Others       Failed to set driver strength.\r
**/\r
EFI_STATUS\r
SdMmcSetDriverStrength (\r
  IN EFI_PCI_IO_PROTOCOL      *PciIo,\r
  IN UINT8                    SlotIndex,\r
  IN SD_DRIVER_STRENGTH_TYPE  DriverStrength\r
  );\r
\r
#endif\r
Commit	Line	Data
48555339 FT	1	/** @file\r
	2	\r
	3	Provides some data structure definitions used by the SD/MMC host controller driver.\r
	4	\r
690d60c0	5	Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.\r
48555339	6	Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
9d510e61	7	SPDX-License-Identifier: BSD-2-Clause-Patent\r
48555339 FT	8	\r
	9	**/\r
	10	\r
	11	#ifndef _SD_MMC_PCI_HCI_H_\r
	12	#define _SD_MMC_PCI_HCI_H_\r
	13	\r
	14	//\r
	15	// SD Host Controller SlotInfo Register Offset\r
	16	//\r
	17	#define SD_MMC_HC_SLOT_OFFSET 0x40\r
	18	\r
	19	#define SD_MMC_HC_MAX_SLOT 6\r
	20	\r
	21	//\r
	22	// SD Host Controller MMIO Register Offset\r
	23	//\r
	24	#define SD_MMC_HC_SDMA_ADDR 0x00\r
	25	#define SD_MMC_HC_ARG2 0x00\r
	26	#define SD_MMC_HC_BLK_SIZE 0x04\r
	27	#define SD_MMC_HC_BLK_COUNT 0x06\r
	28	#define SD_MMC_HC_ARG1 0x08\r
	29	#define SD_MMC_HC_TRANS_MOD 0x0C\r
	30	#define SD_MMC_HC_COMMAND 0x0E\r
	31	#define SD_MMC_HC_RESPONSE 0x10\r
	32	#define SD_MMC_HC_BUF_DAT_PORT 0x20\r
	33	#define SD_MMC_HC_PRESENT_STATE 0x24\r
	34	#define SD_MMC_HC_HOST_CTRL1 0x28\r
	35	#define SD_MMC_HC_POWER_CTRL 0x29\r
	36	#define SD_MMC_HC_BLK_GAP_CTRL 0x2A\r
	37	#define SD_MMC_HC_WAKEUP_CTRL 0x2B\r
	38	#define SD_MMC_HC_CLOCK_CTRL 0x2C\r
	39	#define SD_MMC_HC_TIMEOUT_CTRL 0x2E\r
	40	#define SD_MMC_HC_SW_RST 0x2F\r
	41	#define SD_MMC_HC_NOR_INT_STS 0x30\r
	42	#define SD_MMC_HC_ERR_INT_STS 0x32\r
	43	#define SD_MMC_HC_NOR_INT_STS_EN 0x34\r
	44	#define SD_MMC_HC_ERR_INT_STS_EN 0x36\r
	45	#define SD_MMC_HC_NOR_INT_SIG_EN 0x38\r
	46	#define SD_MMC_HC_ERR_INT_SIG_EN 0x3A\r
	47	#define SD_MMC_HC_AUTO_CMD_ERR_STS 0x3C\r
	48	#define SD_MMC_HC_HOST_CTRL2 0x3E\r
	49	#define SD_MMC_HC_CAP 0x40\r
	50	#define SD_MMC_HC_MAX_CURRENT_CAP 0x48\r
	51	#define SD_MMC_HC_FORCE_EVT_AUTO_CMD 0x50\r
	52	#define SD_MMC_HC_FORCE_EVT_ERR_INT 0x52\r
	53	#define SD_MMC_HC_ADMA_ERR_STS 0x54\r
	54	#define SD_MMC_HC_ADMA_SYS_ADDR 0x58\r
	55	#define SD_MMC_HC_PRESET_VAL 0x60\r
	56	#define SD_MMC_HC_SHARED_BUS_CTRL 0xE0\r
	57	#define SD_MMC_HC_SLOT_INT_STS 0xFC\r
	58	#define SD_MMC_HC_CTRL_VER 0xFE\r
	59	\r
a4708009 TM	60	//\r
	61	// SD Host Controller bits to HOST_CTRL2 register\r
	62	//\r
	63	#define SD_MMC_HC_CTRL_UHS_MASK 0x0007\r
	64	#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000\r
	65	#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001\r
	66	#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002\r
	67	#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003\r
	68	#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004\r
	69	#define SD_MMC_HC_CTRL_MMC_LEGACY 0x0000\r
	70	#define SD_MMC_HC_CTRL_MMC_HS_SDR 0x0001\r
	71	#define SD_MMC_HC_CTRL_MMC_HS_DDR 0x0004\r
	72	#define SD_MMC_HC_CTRL_MMC_HS200 0x0003\r
	73	#define SD_MMC_HC_CTRL_MMC_HS400 0x0005\r
	74	\r
adec1f5d AM	75	#define SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK 0x0030\r
adec1f5d AM	76	\r
48555339 FT	77	//\r
48555339 FT	78	// The transfer modes supported by SD Host Controller\r
48555339 FT	79	//\r
	80	typedef enum {\r
	81	SdMmcNoData,\r
	82	SdMmcPioMode,\r
	83	SdMmcSdmaMode,\r
690d60c0 AS	84	SdMmcAdma32bMode,\r
	85	SdMmcAdma64bV3Mode,\r
	86	SdMmcAdma64bV4Mode\r
48555339 FT	87	} SD_MMC_HC_TRANSFER_MODE;\r
48555339 FT	88	\r
690d60c0 AS	89	//\r
	90	// The ADMA transfer lengths supported by SD Host Controller\r
	91	//\r
	92	typedef enum {\r
	93	SdMmcAdmaLen16b,\r
	94	SdMmcAdmaLen26b\r
	95	} SD_MMC_HC_ADMA_LENGTH_MODE;\r
	96	\r
48555339 FT	97	//\r
	98	// The maximum data length of each descriptor line\r
	99	//\r
b5547b9c AS	100	#define ADMA_MAX_DATA_PER_LINE_16B SIZE_64KB\r
b5547b9c AS	101	#define ADMA_MAX_DATA_PER_LINE_26B SIZE_64MB\r
48555339	102	\r
b5547b9c AS	103	//\r
	104	// ADMA descriptor for 32b addressing.\r
	105	//\r
48555339 FT	106	typedef struct {\r
	107	UINT32 Valid:1;\r
	108	UINT32 End:1;\r
	109	UINT32 Int:1;\r
	110	UINT32 Reserved:1;\r
	111	UINT32 Act:2;\r
b5547b9c AS	112	UINT32 UpperLength:10;\r
b5547b9c AS	113	UINT32 LowerLength:16;\r
48555339	114	UINT32 Address;\r
b5547b9c AS	115	} SD_MMC_HC_ADMA_32_DESC_LINE;\r
	116	\r
	117	//\r
	118	// ADMA descriptor for 64b addressing.\r
	119	//\r
690d60c0 AS	120	typedef struct {\r
	121	UINT32 Valid:1;\r
	122	UINT32 End:1;\r
	123	UINT32 Int:1;\r
	124	UINT32 Reserved:1;\r
	125	UINT32 Act:2;\r
	126	UINT32 UpperLength:10;\r
	127	UINT32 LowerLength:16;\r
	128	UINT32 LowerAddress;\r
	129	UINT32 UpperAddress;\r
	130	} SD_MMC_HC_ADMA_64_V3_DESC_LINE;\r
	131	\r
b5547b9c AS	132	typedef struct {\r
	133	UINT32 Valid:1;\r
	134	UINT32 End:1;\r
	135	UINT32 Int:1;\r
	136	UINT32 Reserved:1;\r
	137	UINT32 Act:2;\r
	138	UINT32 UpperLength:10;\r
	139	UINT32 LowerLength:16;\r
	140	UINT32 LowerAddress;\r
	141	UINT32 UpperAddress;\r
	142	UINT32 Reserved1;\r
690d60c0	143	} SD_MMC_HC_ADMA_64_V4_DESC_LINE;\r
48555339 FT	144	\r
	145	#define SD_MMC_SDMA_BOUNDARY 512 * 1024\r
	146	#define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))\r
	147	\r
	148	typedef struct {\r
	149	UINT8 FirstBar:3; // bit 0:2\r
	150	UINT8 Reserved:1; // bit 3\r
	151	UINT8 SlotNum:3; // bit 4:6\r
	152	UINT8 Reserved1:1; // bit 7\r
	153	} SD_MMC_HC_SLOT_INFO;\r
	154	\r
	155	typedef struct {\r
	156	UINT32 TimeoutFreq:6; // bit 0:5\r
	157	UINT32 Reserved:1; // bit 6\r
	158	UINT32 TimeoutUnit:1; // bit 7\r
	159	UINT32 BaseClkFreq:8; // bit 8:15\r
	160	UINT32 MaxBlkLen:2; // bit 16:17\r
	161	UINT32 BusWidth8:1; // bit 18\r
	162	UINT32 Adma2:1; // bit 19\r
	163	UINT32 Reserved2:1; // bit 20\r
	164	UINT32 HighSpeed:1; // bit 21\r
	165	UINT32 Sdma:1; // bit 22\r
	166	UINT32 SuspRes:1; // bit 23\r
	167	UINT32 Voltage33:1; // bit 24\r
	168	UINT32 Voltage30:1; // bit 25\r
	169	UINT32 Voltage18:1; // bit 26\r
b5547b9c AS	170	UINT32 SysBus64V4:1; // bit 27\r
b5547b9c AS	171	UINT32 SysBus64V3:1; // bit 28\r
48555339 FT	172	UINT32 AsyncInt:1; // bit 29\r
	173	UINT32 SlotType:2; // bit 30:31\r
	174	UINT32 Sdr50:1; // bit 32\r
	175	UINT32 Sdr104:1; // bit 33\r
	176	UINT32 Ddr50:1; // bit 34\r
b5547b9c	177	UINT32 Reserved3:1; // bit 35\r
48555339 FT	178	UINT32 DriverTypeA:1; // bit 36\r
	179	UINT32 DriverTypeC:1; // bit 37\r
	180	UINT32 DriverTypeD:1; // bit 38\r
	181	UINT32 DriverType4:1; // bit 39\r
	182	UINT32 TimerCount:4; // bit 40:43\r
b5547b9c	183	UINT32 Reserved4:1; // bit 44\r
48555339 FT	184	UINT32 TuningSDR50:1; // bit 45\r
	185	UINT32 RetuningMod:2; // bit 46:47\r
	186	UINT32 ClkMultiplier:8; // bit 48:55\r
b5547b9c	187	UINT32 Reserved5:7; // bit 56:62\r
48555339 FT	188	UINT32 Hs400:1; // bit 63\r
	189	} SD_MMC_HC_SLOT_CAP;\r
	190	\r
bdf038cc JB	191	//\r
	192	// SD Host controller version\r
	193	//\r
b5547b9c AS	194	#define SD_MMC_HC_CTRL_VER_100 0x00\r
	195	#define SD_MMC_HC_CTRL_VER_200 0x01\r
	196	#define SD_MMC_HC_CTRL_VER_300 0x02\r
	197	#define SD_MMC_HC_CTRL_VER_400 0x03\r
	198	#define SD_MMC_HC_CTRL_VER_410 0x04\r
	199	#define SD_MMC_HC_CTRL_VER_420 0x05\r
	200	\r
	201	//\r
	202	// SD Host controller V4 enhancements\r
	203	//\r
	204	#define SD_MMC_HC_V4_EN BIT12\r
	205	#define SD_MMC_HC_64_ADDR_EN BIT13\r
	206	#define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10\r
bdf038cc	207	\r
48555339 FT	208	/**\r
	209	Dump the content of SD/MMC host controller's Capability Register.\r
	210	\r
	211	@param[in] Slot The slot number of the SD card to send the command to.\r
	212	@param[in] Capability The buffer to store the capability data.\r
	213	\r
	214	**/\r
	215	VOID\r
	216	DumpCapabilityReg (\r
	217	IN UINT8 Slot,\r
	218	IN SD_MMC_HC_SLOT_CAP *Capability\r
	219	);\r
	220	\r
	221	/**\r
	222	Read SlotInfo register from SD/MMC host controller pci config space.\r
	223	\r
	224	@param[in] PciIo The PCI IO protocol instance.\r
	225	@param[out] FirstBar The buffer to store the first BAR value.\r
	226	@param[out] SlotNum The buffer to store the supported slot number.\r
	227	\r
	228	@retval EFI_SUCCESS The operation succeeds.\r
	229	@retval Others The operation fails.\r
	230	\r
	231	**/\r
	232	EFI_STATUS\r
	233	EFIAPI\r
	234	SdMmcHcGetSlotInfo (\r
	235	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	236	OUT UINT8 *FirstBar,\r
	237	OUT UINT8 *SlotNum\r
	238	);\r
	239	\r
	240	/**\r
	241	Read/Write specified SD/MMC host controller mmio register.\r
	242	\r
	243	@param[in] PciIo The PCI IO protocol instance.\r
	244	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
	245	header to use as the base address for the memory\r
	246	operation to perform.\r
	247	@param[in] Offset The offset within the selected BAR to start the\r
	248	memory operation.\r
	249	@param[in] Read A boolean to indicate it's read or write operation.\r
	250	@param[in] Count The width of the mmio register in bytes.\r
	251	Must be 1, 2 , 4 or 8 bytes.\r
	252	@param[in, out] Data For read operations, the destination buffer to store\r
	253	the results. For write operations, the source buffer\r
	254	to write data from. The caller is responsible for\r
	255	having ownership of the data buffer and ensuring its\r
	256	size not less than Count bytes.\r
	257	\r
	258	@retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.\r
	259	@retval EFI_SUCCESS The read/write operation succeeds.\r
	260	@retval Others The read/write operation fails.\r
	261	\r
	262	**/\r
	263	EFI_STATUS\r
	264	EFIAPI\r
	265	SdMmcHcRwMmio (\r
	266	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	267	IN UINT8 BarIndex,\r
	268	IN UINT32 Offset,\r
	269	IN BOOLEAN Read,\r
	270	IN UINT8 Count,\r
	271	IN OUT VOID *Data\r
272	);\r
273	\r
274	/**\r
275	Do OR operation with the value of the specified SD/MMC host controller mmio register.\r
276	\r
277	@param[in] PciIo The PCI IO protocol instance.\r
278	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
279	header to use as the base address for the memory\r
280	operation to perform.\r
281	@param[in] Offset The offset within the selected BAR to start the\r
282	memory operation.\r
283	@param[in] Count The width of the mmio register in bytes.\r
284	Must be 1, 2 , 4 or 8 bytes.\r
285	@param[in] OrData The pointer to the data used to do OR operation.\r
286	The caller is responsible for having ownership of\r
287	the data buffer and ensuring its size not less than\r
288	Count bytes.\r
289	\r
290	@retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.\r
291	@retval EFI_SUCCESS The OR operation succeeds.\r
292	@retval Others The OR operation fails.\r
293	\r
294	**/\r
295	EFI_STATUS\r
296	EFIAPI\r
297	SdMmcHcOrMmio (\r
298	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
299	IN UINT8 BarIndex,\r
300	IN UINT32 Offset,\r
301	IN UINT8 Count,\r
302	IN VOID *OrData\r
303	);\r
304	\r
305	/**\r
306	Do AND operation with the value of the specified SD/MMC host controller mmio register.\r
307	\r
308	@param[in] PciIo The PCI IO protocol instance.\r
309	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
310	header to use as the base address for the memory\r
311	operation to perform.\r
312	@param[in] Offset The offset within the selected BAR to start the\r
313	memory operation.\r
314	@param[in] Count The width of the mmio register in bytes.\r
315	Must be 1, 2 , 4 or 8 bytes.\r
316	@param[in] AndData The pointer to the data used to do AND operation.\r
317	The caller is responsible for having ownership of\r
318	the data buffer and ensuring its size not less than\r
319	Count bytes.\r
320	\r
321	@retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.\r
322	@retval EFI_SUCCESS The AND operation succeeds.\r
323	@retval Others The AND operation fails.\r
324	\r
325	**/\r
326	EFI_STATUS\r
327	EFIAPI\r
328	SdMmcHcAndMmio (\r
329	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
330	IN UINT8 BarIndex,\r
331	IN UINT32 Offset,\r
332	IN UINT8 Count,\r
333	IN VOID *AndData\r
334	);\r
335	\r
336	/**\r
337	Wait for the value of the specified MMIO register set to the test value.\r
338	\r
339	@param[in] PciIo The PCI IO protocol instance.\r
340	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
341	header to use as the base address for the memory\r
342	operation to perform.\r
343	@param[in] Offset The offset within the selected BAR to start the\r
344	memory operation.\r
345	@param[in] Count The width of the mmio register in bytes.\r
346	Must be 1, 2, 4 or 8 bytes.\r
347	@param[in] MaskValue The mask value of memory.\r
348	@param[in] TestValue The test value of memory.\r
349	@param[in] Timeout The time out value for wait memory set, uses 1\r
350	microsecond as a unit.\r
351	\r
352	@retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout\r
353	range.\r
354	@retval EFI_SUCCESS The MMIO register has expected value.\r
355	@retval Others The MMIO operation fails.\r
356	\r
357	**/\r
358	EFI_STATUS\r
359	EFIAPI\r
360	SdMmcHcWaitMmioSet (\r
361	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
362	IN UINT8 BarIndex,\r
363	IN UINT32 Offset,\r
364	IN UINT8 Count,\r
365	IN UINT64 MaskValue,\r
366	IN UINT64 TestValue,\r
367	IN UINT64 Timeout\r
368	);\r
369	\r
b5547b9c AS	370	/**\r
	371	Get the controller version information from the specified slot.\r
	372	\r
	373	@param[in] PciIo The PCI IO protocol instance.\r
	374	@param[in] Slot The slot number of the SD card to send the command to.\r
	375	@param[out] Version The buffer to store the version information.\r
	376	\r
	377	@retval EFI_SUCCESS The operation executes successfully.\r
	378	@retval Others The operation fails.\r
	379	\r
	380	**/\r
	381	EFI_STATUS\r
	382	SdMmcHcGetControllerVersion (\r
	383	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	384	IN UINT8 Slot,\r
	385	OUT UINT16 *Version\r
	386	);\r
	387	\r
48555339 FT	388	/**\r
	389	Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
	390	register.\r
	391	\r
	392	@param[in] PciIo The PCI IO protocol instance.\r
	393	@param[in] Slot The slot number of the SD card to send the command to.\r
	394	\r
	395	@retval EFI_SUCCESS The operation executes successfully.\r
	396	@retval Others The operation fails.\r
	397	\r
	398	**/\r
	399	EFI_STATUS\r
	400	SdMmcHcEnableInterrupt (\r
	401	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	402	IN UINT8 Slot\r
	403	);\r
	404	\r
	405	/**\r
	406	Get the capability data from the specified slot.\r
	407	\r
	408	@param[in] PciIo The PCI IO protocol instance.\r
	409	@param[in] Slot The slot number of the SD card to send the command to.\r
	410	@param[out] Capability The buffer to store the capability data.\r
	411	\r
	412	@retval EFI_SUCCESS The operation executes successfully.\r
	413	@retval Others The operation fails.\r
	414	\r
	415	**/\r
	416	EFI_STATUS\r
	417	SdMmcHcGetCapability (\r
	418	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	419	IN UINT8 Slot,\r
	420	OUT SD_MMC_HC_SLOT_CAP *Capability\r
	421	);\r
	422	\r
	423	/**\r
	424	Get the maximum current capability data from the specified slot.\r
	425	\r
	426	@param[in] PciIo The PCI IO protocol instance.\r
	427	@param[in] Slot The slot number of the SD card to send the command to.\r
	428	@param[out] MaxCurrent The buffer to store the maximum current capability data.\r
	429	\r
	430	@retval EFI_SUCCESS The operation executes successfully.\r
	431	@retval Others The operation fails.\r
	432	\r
	433	**/\r
	434	EFI_STATUS\r
	435	SdMmcHcGetMaxCurrent (\r
	436	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	437	IN UINT8 Slot,\r
	438	OUT UINT64 *MaxCurrent\r
	439	);\r
	440	\r
	441	/**\r
	442	Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller\r
	443	slot.\r
	444	\r
	445	Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
	446	\r
	447	@param[in] PciIo The PCI IO protocol instance.\r
	448	@param[in] Slot The slot number of the SD card to send the command to.\r
	449	@param[out] MediaPresent The pointer to the media present boolean value.\r
	450	\r
	451	@retval EFI_SUCCESS There is no media change happened.\r
452	@retval EFI_MEDIA_CHANGED There is media change happened.\r
453	@retval Others The detection fails.\r
454	\r
455	**/\r
456	EFI_STATUS\r
457	SdMmcHcCardDetect (\r
458	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
459	IN UINT8 Slot,\r
460	OUT BOOLEAN *MediaPresent\r
461	);\r
462	\r
463	/**\r
464	Stop SD/MMC card clock.\r
465	\r
466	Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r
467	\r
468	@param[in] PciIo The PCI IO protocol instance.\r
469	@param[in] Slot The slot number of the SD card to send the command to.\r
470	\r
471	@retval EFI_SUCCESS Succeed to stop SD/MMC clock.\r
472	@retval Others Fail to stop SD/MMC clock.\r
473	\r
474	**/\r
475	EFI_STATUS\r
476	SdMmcHcStopClock (\r
477	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
478	IN UINT8 Slot\r
479	);\r
480	\r
f68cb23c AM	481	/**\r
	482	Start the SD clock.\r
	483	\r
	484	@param[in] PciIo The PCI IO protocol instance.\r
	485	@param[in] Slot The slot number.\r
	486	\r
	487	@retval EFI_SUCCESS Succeeded to start the SD clock.\r
27f44ea1	488	@retval Others Failed to start the SD clock.\r
f68cb23c AM	489	**/\r
	490	EFI_STATUS\r
	491	SdMmcHcStartSdClock (\r
	492	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	493	IN UINT8 Slot\r
	494	);\r
	495	\r
48555339 FT	496	/**\r
	497	SD/MMC bus power control.\r
	498	\r
	499	Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
	500	\r
	501	@param[in] PciIo The PCI IO protocol instance.\r
	502	@param[in] Slot The slot number of the SD card to send the command to.\r
	503	@param[in] PowerCtrl The value setting to the power control register.\r
	504	\r
	505	@retval TRUE There is a SD/MMC card attached.\r
	506	@retval FALSE There is no a SD/MMC card attached.\r
	507	\r
	508	**/\r
	509	EFI_STATUS\r
	510	SdMmcHcPowerControl (\r
	511	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	512	IN UINT8 Slot,\r
	513	IN UINT8 PowerCtrl\r
	514	);\r
	515	\r
	516	/**\r
	517	Set the SD/MMC bus width.\r
	518	\r
	519	Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r
	520	\r
	521	@param[in] PciIo The PCI IO protocol instance.\r
	522	@param[in] Slot The slot number of the SD card to send the command to.\r
	523	@param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.\r
	524	\r
	525	@retval EFI_SUCCESS The bus width is set successfully.\r
	526	@retval Others The bus width isn't set successfully.\r
	527	\r
	528	**/\r
	529	EFI_STATUS\r
	530	SdMmcHcSetBusWidth (\r
	531	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	532	IN UINT8 Slot,\r
	533	IN UINT16 BusWidth\r
	534	);\r
	535	\r
48555339 FT	536	/**\r
	537	Supply SD/MMC card with maximum voltage at initialization.\r
	538	\r
	539	Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
	540	\r
	541	@param[in] PciIo The PCI IO protocol instance.\r
	542	@param[in] Slot The slot number of the SD card to send the command to.\r
	543	@param[in] Capability The capability of the slot.\r
	544	\r
	545	@retval EFI_SUCCESS The voltage is supplied successfully.\r
	546	@retval Others The voltage isn't supplied successfully.\r
	547	\r
	548	**/\r
	549	EFI_STATUS\r
	550	SdMmcHcInitPowerVoltage (\r
	551	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	552	IN UINT8 Slot,\r
	553	IN SD_MMC_HC_SLOT_CAP Capability\r
	554	);\r
	555	\r
	556	/**\r
	557	Initialize the Timeout Control register with most conservative value at initialization.\r
	558	\r
	559	Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r
	560	\r
	561	@param[in] PciIo The PCI IO protocol instance.\r
	562	@param[in] Slot The slot number of the SD card to send the command to.\r
	563	\r
	564	@retval EFI_SUCCESS The timeout control register is configured successfully.\r
	565	@retval Others The timeout control register isn't configured successfully.\r
	566	\r
	567	**/\r
	568	EFI_STATUS\r
	569	SdMmcHcInitTimeoutCtrl (\r
	570	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	571	IN UINT8 Slot\r
	572	);\r
	573	\r
a4708009 TM	574	/**\r
	575	Set SD Host Controller control 2 registry according to selected speed.\r
	576	\r
	577	@param[in] ControllerHandle The handle of the controller.\r
	578	@param[in] PciIo The PCI IO protocol instance.\r
	579	@param[in] Slot The slot number of the SD card to send the command to.\r
	580	@param[in] Timing The timing to select.\r
	581	\r
	582	@retval EFI_SUCCESS The timing is set successfully.\r
	583	@retval Others The timing isn't set successfully.\r
	584	**/\r
	585	EFI_STATUS\r
	586	SdMmcHcUhsSignaling (\r
	587	IN EFI_HANDLE ControllerHandle,\r
	588	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	589	IN UINT8 Slot,\r
	590	IN SD_MMC_BUS_MODE Timing\r
	591	);\r
	592	\r
adec1f5d AM	593	/**\r
	594	Set driver strength in host controller.\r
	595	\r
	596	@param[in] PciIo The PCI IO protocol instance.\r
	597	@param[in] SlotIndex The slot index of the card.\r
	598	@param[in] DriverStrength DriverStrength to set in the controller.\r
	599	\r
	600	@retval EFI_SUCCESS Driver strength programmed successfully.\r
	601	@retval Others Failed to set driver strength.\r
	602	**/\r
	603	EFI_STATUS\r
	604	SdMmcSetDriverStrength (\r
	605	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	606	IN UINT8 SlotIndex,\r
	607	IN SD_DRIVER_STRENGTH_TYPE DriverStrength\r
	608	);\r
	609	\r
48555339	610	#endif\r