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913cb9dc 1/** @file\r
2\r
ab6495ea 3 The definition for UHCI driver model and HC protocol routines.\r
4\r
1ccdbf2a 5Copyright (c) 2004 - 2010, Intel Corporation\r
913cb9dc 6All rights reserved. This program and the accompanying materials\r
7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
913cb9dc 14**/\r
15\r
ab6495ea 16#ifndef _EFI_UHCI_H_\r
17#define _EFI_UHCI_H_\r
913cb9dc 18\r
ed7748fe 19\r
60c93673 20#include <Uefi.h>\r
ed7748fe 21\r
913cb9dc 22#include <Protocol/Usb2HostController.h>\r
23#include <Protocol/UsbHostController.h>\r
24#include <Protocol/PciIo.h>\r
ed7748fe 25\r
0428a6cb 26#include <Guid/EventGroup.h>\r
27\r
913cb9dc 28#include <Library/DebugLib.h>\r
29#include <Library/BaseMemoryLib.h>\r
30#include <Library/UefiDriverEntryPoint.h>\r
31#include <Library/UefiBootServicesTableLib.h>\r
32#include <Library/UefiLib.h>\r
33#include <Library/BaseLib.h>\r
34#include <Library/MemoryAllocationLib.h>\r
dd4047a5 35#include <Library/PcdLib.h>\r
913cb9dc 36\r
a261044c 37#include <IndustryStandard/Pci.h>\r
913cb9dc 38\r
39typedef struct _USB_HC_DEV USB_HC_DEV;\r
40\r
41#include "UsbHcMem.h"\r
42#include "UhciQueue.h"\r
43#include "UhciReg.h"\r
44#include "UhciSched.h"\r
45#include "UhciDebug.h"\r
aa79b0b3 46#include "ComponentName.h"\r
913cb9dc 47\r
1ccdbf2a 48//\r
49// UHC timeout experience values\r
50//\r
51\r
52#define UHC_1_MICROSECOND 1\r
53#define UHC_1_MILLISECOND (1000 * UHC_1_MICROSECOND)\r
54#define UHC_1_SECOND (1000 * UHC_1_MILLISECOND)\r
55\r
56//\r
57// UHCI register operation timeout, set by experience\r
58//\r
59#define UHC_GENERIC_TIMEOUT UHC_1_SECOND\r
60\r
61//\r
62// Wait for force global resume(FGR) complete, refers to\r
63// specification[UHCI11-2.1.1]\r
64//\r
65#define UHC_FORCE_GLOBAL_RESUME_STALL (20 * UHC_1_MILLISECOND)\r
68246fa8 66\r
1ccdbf2a 67//\r
68// Wait for roothub port reset and recovery, reset stall\r
69// is set by experience, and recovery stall refers to\r
70// specification[UHCI11-2.1.1]\r
71//\r
72#define UHC_ROOT_PORT_RESET_STALL (50 * UHC_1_MILLISECOND)\r
73#define UHC_ROOT_PORT_RECOVERY_STALL (10 * UHC_1_MILLISECOND)\r
74\r
75//\r
76// Sync and Async transfer polling interval, set by experience,\r
77// and the unit of Async is 100us.\r
78//\r
79#define UHC_SYNC_POLL_INTERVAL (1 * UHC_1_MILLISECOND)\r
80#define UHC_ASYNC_POLL_INTERVAL (50 * 10000UL)\r
913cb9dc 81\r
ab6495ea 82//\r
83// UHC raises TPL to TPL_NOTIFY to serialize all its operations\r
84// to protect shared data structures.\r
85//\r
86#define UHCI_TPL TPL_NOTIFY\r
87\r
f3f2e05d 88#define USB_HC_DEV_SIGNATURE SIGNATURE_32 ('u', 'h', 'c', 'i')\r
913cb9dc 89\r
90#pragma pack(1)\r
91typedef struct {\r
1ccdbf2a 92 UINT8 ProgInterface;\r
913cb9dc 93 UINT8 SubClassCode;\r
94 UINT8 BaseCode;\r
95} USB_CLASSC;\r
96#pragma pack()\r
97\r
913cb9dc 98#define UHC_FROM_USB2_HC_PROTO(This) CR(This, USB_HC_DEV, Usb2Hc, USB_HC_DEV_SIGNATURE)\r
99\r
100//\r
101// USB_HC_DEV support the UHCI hardware controller. It schedules\r
102// the asynchronous interrupt transfer with the same method as\r
103// EHCI: a reversed tree structure. For synchronous interrupt,\r
104// control and bulk transfer, it uses three static queue head to\r
105// schedule them. SyncIntQh is for interrupt transfer. LsCtrlQh is\r
106// for LOW speed control transfer, and FsCtrlBulkQh is for FULL\r
107// speed control or bulk transfer. This is because FULL speed contrl\r
108// or bulk transfer can reclaim the unused bandwidth. Some USB\r
109// device requires this bandwidth reclamation capability.\r
110//\r
c52fa98c 111struct _USB_HC_DEV {\r
913cb9dc 112 UINT32 Signature;\r
913cb9dc 113 EFI_USB2_HC_PROTOCOL Usb2Hc;\r
114 EFI_PCI_IO_PROTOCOL *PciIo;\r
68246fa8 115 UINT64 OriginalPciAttributes;\r
913cb9dc 116\r
117 //\r
118 // Schedule data structures\r
119 //\r
120 UINT32 *FrameBase;\r
3af875e2 121 UINT32 *FrameBasePciMemAddr;\r
913cb9dc 122 UHCI_QH_SW *SyncIntQh;\r
123 UHCI_QH_SW *CtrlQh;\r
124 UHCI_QH_SW *BulkQh;\r
125\r
126 //\r
127 // Structures to maintain asynchronus interrupt transfers.\r
128 // When asynchronous interrutp transfer is unlinked from\r
129 // the frame list, the hardware may still hold a pointer\r
130 // to it. To synchronize with hardware, its resoureces are\r
131 // released in two steps using Recycle and RecycleWait.\r
132 // Check the asynchronous interrupt management routines.\r
133 //\r
134 LIST_ENTRY AsyncIntList;\r
135 EFI_EVENT AsyncIntMonitor;\r
136 UHCI_ASYNC_REQUEST *Recycle;\r
137 UHCI_ASYNC_REQUEST *RecycleWait;\r
138\r
139\r
140 UINTN RootPorts;\r
141 USBHC_MEM_POOL *MemPool;\r
142 EFI_UNICODE_STRING_TABLE *CtrlNameTable;\r
143 VOID *FrameMapping;\r
0428a6cb 144\r
145 //\r
146 // ExitBootServicesEvent is used to stop the EHC DMA operation \r
147 // after exit boot service.\r
148 //\r
149 EFI_EVENT ExitBootServiceEvent;\r
c52fa98c 150};\r
913cb9dc 151\r
f527bce3 152extern EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding;\r
153extern EFI_COMPONENT_NAME_PROTOCOL gUhciComponentName;\r
154extern EFI_COMPONENT_NAME2_PROTOCOL gUhciComponentName2;\r
913cb9dc 155\r
aa79b0b3 156/**\r
157 Test to see if this driver supports ControllerHandle. Any\r
158 ControllerHandle that has UsbHcProtocol installed will be supported.\r
159\r
160 @param This Protocol instance pointer.\r
161 @param Controller Handle of device to test.\r
162 @param RemainingDevicePath Not used.\r
163\r
164 @return EFI_SUCCESS This driver supports this device.\r
165 @return EFI_UNSUPPORTED This driver does not support this device.\r
166\r
167**/\r
168EFI_STATUS\r
169EFIAPI\r
170UhciDriverBindingSupported (\r
171 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
172 IN EFI_HANDLE Controller,\r
173 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
174 );\r
175\r
176/**\r
177 Starting the Usb UHCI Driver.\r
178\r
179 @param This Protocol instance pointer.\r
180 @param Controller Handle of device to test.\r
181 @param RemainingDevicePath Not used.\r
182\r
183 @retval EFI_SUCCESS This driver supports this device.\r
184 @retval EFI_UNSUPPORTED This driver does not support this device.\r
185 @retval EFI_DEVICE_ERROR This driver cannot be started due to device Error.\r
186 EFI_OUT_OF_RESOURCES- Failed due to resource shortage.\r
187\r
188**/\r
189EFI_STATUS\r
190EFIAPI\r
191UhciDriverBindingStart (\r
192 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
193 IN EFI_HANDLE Controller,\r
194 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
195 );\r
196\r
197/**\r
198 Stop this driver on ControllerHandle. Support stoping any child handles\r
199 created by this driver.\r
200\r
201 @param This Protocol instance pointer.\r
202 @param Controller Handle of device to stop driver on.\r
203 @param NumberOfChildren Number of Children in the ChildHandleBuffer.\r
204 @param ChildHandleBuffer List of handles for the children we need to stop.\r
205\r
206 @return EFI_SUCCESS\r
207 @return others\r
208\r
209**/\r
210EFI_STATUS\r
211EFIAPI\r
212UhciDriverBindingStop (\r
213 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
214 IN EFI_HANDLE Controller,\r
215 IN UINTN NumberOfChildren,\r
216 IN EFI_HANDLE *ChildHandleBuffer\r
217 );\r
218\r
913cb9dc 219#endif\r