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1. Remove USB HC Protocol installing from Uhci module. It only installs USB2 HC protocol.
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciDxe / Uhci.h
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913cb9dc 1/** @file\r
2\r
3Copyright (c) 2004 - 2007, Intel Corporation\r
4All rights reserved. This program and the accompanying materials\r
5are licensed and made available under the terms and conditions of the BSD License\r
6which accompanies this distribution. The full text of the license may be found at\r
7http://opensource.org/licenses/bsd-license.php\r
8\r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11\r
12Module Name:\r
13\r
14 Uhci.h\r
15\r
16Abstract:\r
17\r
18 The definition for UHCI driver model and HC protocol routines.\r
19\r
20Revision History\r
21\r
22\r
23**/\r
24\r
25#ifndef _UHCI_H\r
26#define _UHCI_H\r
27\r
ed7748fe 28\r
913cb9dc 29#include <PiDxe.h>\r
ed7748fe 30\r
913cb9dc 31#include <Protocol/Usb2HostController.h>\r
32#include <Protocol/UsbHostController.h>\r
33#include <Protocol/PciIo.h>\r
ed7748fe 34\r
913cb9dc 35#include <Library/DebugLib.h>\r
36#include <Library/BaseMemoryLib.h>\r
37#include <Library/UefiDriverEntryPoint.h>\r
38#include <Library/UefiBootServicesTableLib.h>\r
39#include <Library/UefiLib.h>\r
40#include <Library/BaseLib.h>\r
41#include <Library/MemoryAllocationLib.h>\r
42\r
43#include <IndustryStandard/Pci22.h>\r
44\r
45typedef struct _USB_HC_DEV USB_HC_DEV;\r
46\r
47#include "UsbHcMem.h"\r
48#include "UhciQueue.h"\r
49#include "UhciReg.h"\r
50#include "UhciSched.h"\r
51#include "UhciDebug.h"\r
52\r
53enum {\r
41e8ff27 54 UHC_1_MICROSECOND = 1,\r
55 UHC_1_MILLISECOND = 1000 * UHC_1_MICROSECOND,\r
56 UHC_1_SECOND = 1000 * UHC_1_MILLISECOND,\r
57\r
58 //\r
59 // UHCI register operation timeout, set by experience\r
913cb9dc 60 //\r
41e8ff27 61 UHC_GENERIC_TIMEOUT = UHC_1_SECOND,\r
68246fa8 62\r
913cb9dc 63 //\r
41e8ff27 64 // Wait for force global resume(FGR) complete, refers to\r
65 // specification[UHCI11-2.1.1]\r
68246fa8 66 //\r
41e8ff27 67 UHC_FORCE_GLOBAL_RESUME_STALL = 20 * UHC_1_MILLISECOND,\r
913cb9dc 68\r
41e8ff27 69 //\r
70 // Wait for roothub port reset and recovery, reset stall\r
68246fa8 71 // is set by experience, and recovery stall refers to\r
41e8ff27 72 // specification[UHCI11-2.1.1]\r
73 //\r
74 UHC_ROOT_PORT_RESET_STALL = 50 * UHC_1_MILLISECOND,\r
75 UHC_ROOT_PORT_RECOVERY_STALL = 10 * UHC_1_MILLISECOND,\r
913cb9dc 76\r
41e8ff27 77 //\r
68246fa8 78 // Sync and Async transfer polling interval, set by experience,\r
41e8ff27 79 // and the unit of Async is 100us.\r
80 //\r
81 UHC_SYNC_POLL_INTERVAL = 50 * UHC_1_MICROSECOND,\r
82 UHC_ASYNC_POLL_INTERVAL = 50 * 10000UL,\r
68246fa8 83\r
913cb9dc 84 //\r
85 // UHC raises TPL to TPL_NOTIFY to serialize all its operations\r
86 // to protect shared data structures.\r
87 //\r
88 UHCI_TPL = TPL_NOTIFY,\r
89\r
23c326c2 90 USB_HC_DEV_SIGNATURE = EFI_SIGNATURE_32 ('u', 'h', 'c', 'i')\r
913cb9dc 91};\r
92\r
93#pragma pack(1)\r
94typedef struct {\r
95 UINT8 PI;\r
96 UINT8 SubClassCode;\r
97 UINT8 BaseCode;\r
98} USB_CLASSC;\r
99#pragma pack()\r
100\r
913cb9dc 101#define UHC_FROM_USB2_HC_PROTO(This) CR(This, USB_HC_DEV, Usb2Hc, USB_HC_DEV_SIGNATURE)\r
102\r
103//\r
104// USB_HC_DEV support the UHCI hardware controller. It schedules\r
105// the asynchronous interrupt transfer with the same method as\r
106// EHCI: a reversed tree structure. For synchronous interrupt,\r
107// control and bulk transfer, it uses three static queue head to\r
108// schedule them. SyncIntQh is for interrupt transfer. LsCtrlQh is\r
109// for LOW speed control transfer, and FsCtrlBulkQh is for FULL\r
110// speed control or bulk transfer. This is because FULL speed contrl\r
111// or bulk transfer can reclaim the unused bandwidth. Some USB\r
112// device requires this bandwidth reclamation capability.\r
113//\r
c52fa98c 114struct _USB_HC_DEV {\r
913cb9dc 115 UINT32 Signature;\r
913cb9dc 116 EFI_USB2_HC_PROTOCOL Usb2Hc;\r
117 EFI_PCI_IO_PROTOCOL *PciIo;\r
68246fa8 118 UINT64 OriginalPciAttributes;\r
913cb9dc 119\r
120 //\r
121 // Schedule data structures\r
122 //\r
123 UINT32 *FrameBase;\r
124 UHCI_QH_SW *SyncIntQh;\r
125 UHCI_QH_SW *CtrlQh;\r
126 UHCI_QH_SW *BulkQh;\r
127\r
128 //\r
129 // Structures to maintain asynchronus interrupt transfers.\r
130 // When asynchronous interrutp transfer is unlinked from\r
131 // the frame list, the hardware may still hold a pointer\r
132 // to it. To synchronize with hardware, its resoureces are\r
133 // released in two steps using Recycle and RecycleWait.\r
134 // Check the asynchronous interrupt management routines.\r
135 //\r
136 LIST_ENTRY AsyncIntList;\r
137 EFI_EVENT AsyncIntMonitor;\r
138 UHCI_ASYNC_REQUEST *Recycle;\r
139 UHCI_ASYNC_REQUEST *RecycleWait;\r
140\r
141\r
142 UINTN RootPorts;\r
143 USBHC_MEM_POOL *MemPool;\r
144 EFI_UNICODE_STRING_TABLE *CtrlNameTable;\r
145 VOID *FrameMapping;\r
c52fa98c 146};\r
913cb9dc 147\r
f527bce3 148extern EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding;\r
149extern EFI_COMPONENT_NAME_PROTOCOL gUhciComponentName;\r
150extern EFI_COMPONENT_NAME2_PROTOCOL gUhciComponentName2;\r
913cb9dc 151\r
152#endif\r