]> git.proxmox.com Git - mirror_edk2.git/blame - MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.h
Clean up DEC files:
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciDxe / UhciQueue.h
CommitLineData
913cb9dc 1/** @file\r
2\r
ab6495ea 3 The definition for UHCI register operation routines.\r
4\r
cd5ebaa0
HT
5Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>\r
6This program and the accompanying materials\r
913cb9dc 7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
913cb9dc 14**/\r
15\r
16#ifndef _EFI_UHCI_QUEUE_H_\r
17#define _EFI_UHCI_QUEUE_H_\r
18\r
19//\r
20// Macroes used to set various links in UHCI's driver.\r
21// In this UHCI driver, QH's horizontal link always pointers to other QH,\r
22// and its vertical link always pointers to TD. TD's next pointer always\r
23// pointers to other sibling TD. Frame link always pointers to QH because\r
24// ISO transfer isn't supported.\r
25//\r
26// We should use UINT32 to access these pointers to void race conditions\r
27// with hardware.\r
28//\r
29#define QH_HLINK(Pointer, Terminate) \\r
30 (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | 0x02 | ((Terminate) ? 0x01 : 0))\r
31\r
32#define QH_VLINK(Pointer, Terminate) \\r
33 (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | ((Terminate) ? 0x01 : 0))\r
34\r
35#define TD_LINK(Pointer, VertFirst, Terminate) \\r
36 (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | \\r
37 ((VertFirst) ? 0x04 : 0) | ((Terminate) ? 0x01 : 0))\r
38\r
39#define LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
40\r
41#define UHCI_ADDR(QhOrTd) ((VOID *) (UINTN) ((QhOrTd) & 0xFFFFFFF0))\r
42\r
43#pragma pack(1)\r
44//\r
45// Both links in QH has this internal structure:\r
46// Next pointer: 28, Reserved: 2, NextIsQh: 1, Terminate: 1\r
47// This is the same as frame list entry.\r
48//\r
49typedef struct {\r
50 UINT32 HorizonLink;\r
51 UINT32 VerticalLink;\r
52} UHCI_QH_HW;\r
53\r
54//\r
55// Next link in TD has this internal structure:\r
56// Next pointer: 28, Reserved: 1, Vertical First: 1, NextIsQh: 1, Terminate: 1\r
57//\r
58typedef struct {\r
59 UINT32 NextLink;\r
60 UINT32 ActualLen : 11;\r
61 UINT32 Reserved1 : 5;\r
62 UINT32 Status : 8;\r
63 UINT32 IntOnCpl : 1;\r
64 UINT32 IsIsoch : 1;\r
65 UINT32 LowSpeed : 1;\r
66 UINT32 ErrorCount : 2;\r
67 UINT32 ShortPacket : 1;\r
68 UINT32 Reserved2 : 2;\r
69 UINT32 PidCode : 8;\r
70 UINT32 DeviceAddr : 7;\r
71 UINT32 EndPoint : 4;\r
72 UINT32 DataToggle : 1;\r
73 UINT32 Reserved3 : 1;\r
74 UINT32 MaxPacketLen: 11;\r
75 UINT32 DataBuffer;\r
76} UHCI_TD_HW;\r
77#pragma pack()\r
78\r
79typedef struct _UHCI_TD_SW UHCI_TD_SW;\r
80typedef struct _UHCI_QH_SW UHCI_QH_SW;\r
81\r
c52fa98c 82struct _UHCI_QH_SW {\r
913cb9dc 83 UHCI_QH_HW QhHw;\r
84 UHCI_QH_SW *NextQh;\r
85 UHCI_TD_SW *TDs;\r
86 UINTN Interval;\r
c52fa98c 87};\r
913cb9dc 88\r
c52fa98c 89struct _UHCI_TD_SW {\r
913cb9dc 90 UHCI_TD_HW TdHw;\r
91 UHCI_TD_SW *NextTd;\r
92 UINT8 *Data;\r
93 UINT16 DataLen;\r
c52fa98c 94};\r
913cb9dc 95\r
96\r
97/**\r
ab6495ea 98 Link the TD To QH.\r
913cb9dc 99\r
3af875e2 100 @param Uhc The UHCI device.\r
ab6495ea 101 @param Qh The queue head for the TD to link to.\r
102 @param Td The TD to link.\r
913cb9dc 103\r
913cb9dc 104**/\r
105VOID\r
106UhciLinkTdToQh (\r
3af875e2 107 IN USB_HC_DEV *Uhc,\r
913cb9dc 108 IN UHCI_QH_SW *Qh,\r
109 IN UHCI_TD_SW *Td\r
ed66e1bc 110 );\r
913cb9dc 111\r
112\r
113/**\r
ab6495ea 114 Unlink TD from the QH.\r
913cb9dc 115\r
ab6495ea 116 @param Qh The queue head to unlink from.\r
117 @param Td The TD to unlink.\r
913cb9dc 118\r
ab6495ea 119 @return None.\r
913cb9dc 120\r
121**/\r
122VOID\r
123UhciUnlinkTdFromQh (\r
124 IN UHCI_QH_SW *Qh,\r
125 IN UHCI_TD_SW *Td\r
ed66e1bc 126 );\r
913cb9dc 127\r
128\r
129/**\r
ab6495ea 130 Map address of request structure buffer.\r
913cb9dc 131\r
ab6495ea 132 @param Uhc The UHCI device.\r
133 @param Request The user request buffer.\r
134 @param MappedAddr Mapped address of request.\r
135 @param Map Identificaion of this mapping to return.\r
913cb9dc 136\r
ab6495ea 137 @return EFI_SUCCESS Success.\r
138 @return EFI_DEVICE_ERROR Fail to map the user request.\r
913cb9dc 139\r
140**/\r
141EFI_STATUS\r
142UhciMapUserRequest (\r
143 IN USB_HC_DEV *Uhc,\r
144 IN OUT VOID *Request,\r
145 OUT UINT8 **MappedAddr,\r
146 OUT VOID **Map\r
ed66e1bc 147 );\r
913cb9dc 148\r
149\r
150/**\r
ab6495ea 151 Map address of user data buffer.\r
913cb9dc 152\r
ab6495ea 153 @param Uhc The UHCI device.\r
154 @param Direction Direction of the data transfer.\r
155 @param Data The user data buffer.\r
156 @param Len Length of the user data.\r
157 @param PktId Packet identificaion.\r
158 @param MappedAddr Mapped address to return.\r
159 @param Map Identificaion of this mapping to return.\r
913cb9dc 160\r
ab6495ea 161 @return EFI_SUCCESS Success.\r
162 @return EFI_DEVICE_ERROR Fail to map the user data.\r
913cb9dc 163\r
164**/\r
165EFI_STATUS\r
166UhciMapUserData (\r
167 IN USB_HC_DEV *Uhc,\r
168 IN EFI_USB_DATA_DIRECTION Direction,\r
169 IN VOID *Data,\r
170 IN OUT UINTN *Len,\r
171 OUT UINT8 *PktId,\r
172 OUT UINT8 **MappedAddr,\r
173 OUT VOID **Map\r
ed66e1bc 174 );\r
913cb9dc 175\r
176\r
177/**\r
ab6495ea 178 Delete a list of TDs.\r
913cb9dc 179\r
ab6495ea 180 @param Uhc The UHCI device.\r
181 @param FirstTd TD link list head.\r
913cb9dc 182\r
ab6495ea 183 @return None.\r
913cb9dc 184\r
185**/\r
186VOID\r
187UhciDestoryTds (\r
188 IN USB_HC_DEV *Uhc,\r
189 IN UHCI_TD_SW *FirstTd\r
ed66e1bc 190 );\r
913cb9dc 191\r
192\r
193/**\r
ab6495ea 194 Create an initialize a new queue head.\r
913cb9dc 195\r
ab6495ea 196 @param Uhc The UHCI device.\r
197 @param Interval The polling interval for the queue.\r
913cb9dc 198\r
ab6495ea 199 @return The newly created queue header.\r
913cb9dc 200\r
201**/\r
202UHCI_QH_SW *\r
203UhciCreateQh (\r
204 IN USB_HC_DEV *Uhc,\r
205 IN UINTN Interval\r
ed66e1bc 206 );\r
913cb9dc 207\r
208\r
209/**\r
ab6495ea 210 Create Tds list for Control Transfer.\r
913cb9dc 211\r
ab6495ea 212 @param Uhc The UHCI device.\r
213 @param DeviceAddr The device address.\r
214 @param DataPktId Packet Identification of Data Tds.\r
3af875e2 215 @param Request A pointer to cpu memory address of request structure buffer to transfer.\r
216 @param RequestPhy A pointer to pci memory address of request structure buffer to transfer.\r
217 @param Data A pointer to cpu memory address of user data buffer to transfer.\r
218 @param DataPhy A pointer to pci memory address of user data buffer to transfer.\r
ab6495ea 219 @param DataLen Length of user data to transfer.\r
220 @param MaxPacket Maximum packet size for control transfer.\r
221 @param IsLow Full speed or low speed.\r
913cb9dc 222\r
ab6495ea 223 @return The Td list head for the control transfer.\r
913cb9dc 224\r
225**/\r
226UHCI_TD_SW *\r
227UhciCreateCtrlTds (\r
228 IN USB_HC_DEV *Uhc,\r
229 IN UINT8 DeviceAddr,\r
230 IN UINT8 DataPktId,\r
231 IN UINT8 *Request,\r
3af875e2 232 IN UINT8 *RequestPhy,\r
913cb9dc 233 IN UINT8 *Data,\r
3af875e2 234 IN UINT8 *DataPhy,\r
913cb9dc 235 IN UINTN DataLen,\r
236 IN UINT8 MaxPacket,\r
237 IN BOOLEAN IsLow\r
ed66e1bc 238 );\r
913cb9dc 239\r
240\r
241/**\r
ab6495ea 242 Create Tds list for Bulk/Interrupt Transfer.\r
243\r
244 @param Uhc USB_HC_DEV.\r
245 @param DevAddr Address of Device.\r
246 @param EndPoint Endpoint Number.\r
247 @param PktId Packet Identification of Data Tds.\r
3af875e2 248 @param Data A pointer to cpu memory address of user data buffer to transfer.\r
249 @param DataPhy A pointer to pci memory address of user data buffer to transfer.\r
ab6495ea 250 @param DataLen Length of user data to transfer.\r
251 @param DataToggle Data Toggle Pointer.\r
252 @param MaxPacket Maximum packet size for Bulk/Interrupt transfer.\r
253 @param IsLow Is Low Speed Device.\r
254\r
255 @return The Tds list head for the bulk transfer.\r
913cb9dc 256\r
257**/\r
258UHCI_TD_SW *\r
259UhciCreateBulkOrIntTds (\r
260 IN USB_HC_DEV *Uhc,\r
261 IN UINT8 DevAddr,\r
262 IN UINT8 EndPoint,\r
263 IN UINT8 PktId,\r
264 IN UINT8 *Data,\r
3af875e2 265 IN UINT8 *DataPhy,\r
913cb9dc 266 IN UINTN DataLen,\r
267 IN OUT UINT8 *DataToggle,\r
268 IN UINT8 MaxPacket,\r
269 IN BOOLEAN IsLow\r
ed66e1bc 270 );\r
913cb9dc 271\r
272#endif\r