]>
Commit | Line | Data |
---|---|---|
913cb9dc | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2007, Intel Corporation\r | |
4 | All rights reserved. This program and the accompanying materials\r | |
5 | are licensed and made available under the terms and conditions of the BSD License\r | |
6 | which accompanies this distribution. The full text of the license may be found at\r | |
7 | http://opensource.org/licenses/bsd-license.php\r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | \r | |
12 | Module Name:\r | |
13 | \r | |
14 | UhciReg.h\r | |
15 | \r | |
16 | Abstract:\r | |
17 | \r | |
18 | The definition for UHCI register operation routines.\r | |
19 | \r | |
20 | Revision History\r | |
21 | \r | |
22 | \r | |
23 | **/\r | |
24 | \r | |
25 | #ifndef _EFI_UHCI_REG_H_\r | |
26 | #define _EFI_UHCI_REG_H_\r | |
27 | \r | |
28 | #define BIT(a) (1 << (a))\r | |
29 | \r | |
30 | enum {\r | |
31 | UHCI_FRAME_NUM = 1024,\r | |
32 | \r | |
33 | //\r | |
34 | // Register offset and PCI related staff\r | |
35 | //\r | |
36 | CLASSC_OFFSET = 0x09,\r | |
37 | USBBASE_OFFSET = 0x20,\r | |
38 | USB_BAR_INDEX = 4,\r | |
39 | PCI_CLASSC_PI_UHCI = 0x00,\r | |
40 | \r | |
41 | USBCMD_OFFSET = 0,\r | |
42 | USBSTS_OFFSET = 2,\r | |
43 | USBINTR_OFFSET = 4,\r | |
44 | USBPORTSC_OFFSET = 0x10,\r | |
45 | USB_FRAME_NO_OFFSET = 6,\r | |
46 | USB_FRAME_BASE_OFFSET = 8,\r | |
47 | USB_EMULATION_OFFSET = 0xC0,\r | |
48 | \r | |
49 | //\r | |
50 | // Packet IDs\r | |
51 | //\r | |
52 | SETUP_PACKET_ID = 0x2D,\r | |
53 | INPUT_PACKET_ID = 0x69,\r | |
54 | OUTPUT_PACKET_ID = 0xE1,\r | |
55 | ERROR_PACKET_ID = 0x55,\r | |
56 | \r | |
57 | //\r | |
58 | // USB port status and control bit definition.\r | |
59 | //\r | |
60 | USBPORTSC_CCS = BIT(0), // Current Connect Status\r | |
61 | USBPORTSC_CSC = BIT(1), // Connect Status Change\r | |
62 | USBPORTSC_PED = BIT(2), // Port Enable / Disable\r | |
63 | USBPORTSC_PEDC = BIT(3), // Port Enable / Disable Change\r | |
64 | USBPORTSC_LSL = BIT(4), // Line Status Low BIT\r | |
65 | USBPORTSC_LSH = BIT(5), // Line Status High BIT\r | |
66 | USBPORTSC_RD = BIT(6), // Resume Detect\r | |
67 | USBPORTSC_LSDA = BIT(8), // Low Speed Device Attached\r | |
68 | USBPORTSC_PR = BIT(9), // Port Reset\r | |
69 | USBPORTSC_SUSP = BIT(12), // Suspend\r | |
70 | \r | |
71 | USB_MAX_ROOTHUB_PORT = 0x0F, // Max number of root hub port\r | |
72 | \r | |
73 | //\r | |
74 | // Command register bit definitions\r | |
75 | //\r | |
76 | USBCMD_RS = BIT(0), // Run/Stop\r | |
77 | USBCMD_HCRESET = BIT(1), // Host reset\r | |
78 | USBCMD_GRESET = BIT(2), // Global reset\r | |
79 | USBCMD_EGSM = BIT(3), // Global Suspend Mode\r | |
80 | USBCMD_FGR = BIT(4), // Force Global Resume\r | |
81 | USBCMD_SWDBG = BIT(5), // SW Debug mode\r | |
82 | USBCMD_CF = BIT(6), // Config Flag (sw only)\r | |
83 | USBCMD_MAXP = BIT(7), // Max Packet (0 = 32, 1 = 64)\r | |
84 | \r | |
85 | //\r | |
86 | // USB Status register bit definitions\r | |
87 | //\r | |
88 | USBSTS_USBINT = BIT(0), // Interrupt due to IOC\r | |
89 | USBSTS_ERROR = BIT(1), // Interrupt due to error\r | |
90 | USBSTS_RD = BIT(2), // Resume Detect\r | |
91 | USBSTS_HSE = BIT(3), // Host System Error\r | |
92 | USBSTS_HCPE = BIT(4), // Host Controller Process Error\r | |
93 | USBSTS_HCH = BIT(5), // HC Halted\r | |
94 | \r | |
95 | USBTD_ACTIVE = BIT(7), // TD is still active\r | |
96 | USBTD_STALLED = BIT(6), // TD is stalled\r | |
97 | USBTD_BUFFERR = BIT(5), // Buffer underflow or overflow\r | |
98 | USBTD_BABBLE = BIT(4), // Babble condition\r | |
99 | USBTD_NAK = BIT(3), // NAK is received\r | |
100 | USBTD_CRC = BIT(2), // CRC/Time out error\r | |
c52fa98c | 101 | USBTD_BITSTUFF = BIT(1) // Bit stuff error\r |
913cb9dc | 102 | };\r |
103 | \r | |
104 | \r | |
105 | /**\r | |
106 | Read a UHCI register\r | |
107 | \r | |
108 | @param PciIo The EFI_PCI_IO_PROTOCOL to use\r | |
109 | @param Offset Register offset to USB_BAR_INDEX\r | |
110 | \r | |
111 | @return Content of register\r | |
112 | \r | |
113 | **/\r | |
114 | UINT16\r | |
115 | UhciReadReg (\r | |
116 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
117 | IN UINT32 Offset\r | |
118 | )\r | |
119 | ;\r | |
120 | \r | |
121 | \r | |
122 | \r | |
123 | /**\r | |
124 | Write data to UHCI register\r | |
125 | \r | |
126 | @param PciIo The EFI_PCI_IO_PROTOCOL to use\r | |
127 | @param Offset Register offset to USB_BAR_INDEX\r | |
128 | @param Data Data to write\r | |
129 | \r | |
130 | @return VOID\r | |
131 | \r | |
132 | **/\r | |
133 | VOID\r | |
134 | UhciWriteReg (\r | |
135 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
136 | IN UINT32 Offset,\r | |
137 | IN UINT16 Data\r | |
138 | )\r | |
139 | ;\r | |
140 | \r | |
141 | \r | |
142 | \r | |
143 | /**\r | |
144 | Set a bit of the UHCI Register\r | |
145 | \r | |
146 | @param PciIo The EFI_PCI_IO_PROTOCOL to use\r | |
147 | @param Offset Register offset to USB_BAR_INDEX\r | |
148 | @param Bit The bit to set\r | |
149 | \r | |
150 | @return None\r | |
151 | \r | |
152 | **/\r | |
153 | VOID\r | |
154 | UhciSetRegBit (\r | |
155 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
156 | IN UINT32 Offset,\r | |
157 | IN UINT16 Bit\r | |
158 | )\r | |
159 | ;\r | |
160 | \r | |
161 | \r | |
162 | \r | |
163 | /**\r | |
164 | Clear a bit of the UHCI Register\r | |
165 | \r | |
166 | @param PciIo The PCI_IO protocol to access the PCI\r | |
167 | @param Offset Register offset to USB_BAR_INDEX\r | |
168 | @param Bit The bit to clear\r | |
169 | \r | |
170 | @return None\r | |
171 | \r | |
172 | **/\r | |
173 | VOID\r | |
174 | UhciClearRegBit (\r | |
175 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
176 | IN UINT32 Offset,\r | |
177 | IN UINT16 Bit\r | |
178 | )\r | |
179 | ;\r | |
180 | \r | |
181 | \r | |
182 | /**\r | |
183 | Clear all the interrutp status bits, these bits\r | |
184 | are Write-Clean\r | |
185 | \r | |
186 | @param Uhc The UHCI device\r | |
187 | \r | |
188 | @return None\r | |
189 | \r | |
190 | **/\r | |
191 | VOID\r | |
192 | UhciAckAllInterrupt (\r | |
193 | IN USB_HC_DEV *Uhc\r | |
194 | )\r | |
195 | ;\r | |
196 | \r | |
197 | \r | |
198 | /**\r | |
199 | Stop the host controller\r | |
200 | \r | |
201 | @param Uhc The UHCI device\r | |
202 | @param Timeout Max time allowed\r | |
203 | \r | |
204 | @retval EFI_SUCCESS The host controller is stopped\r | |
205 | @retval EFI_TIMEOUT Failed to stop the host controller\r | |
206 | \r | |
207 | **/\r | |
208 | EFI_STATUS\r | |
209 | UhciStopHc (\r | |
210 | IN USB_HC_DEV *Uhc,\r | |
211 | IN UINTN Timeout\r | |
212 | )\r | |
213 | ;\r | |
214 | \r | |
215 | \r | |
216 | \r | |
217 | /**\r | |
218 | Check whether the host controller operates well\r | |
219 | \r | |
220 | @param PciIo The PCI_IO protocol to use\r | |
221 | \r | |
222 | @retval TRUE Host controller is working\r | |
223 | @retval FALSE Host controller is halted or system error\r | |
224 | \r | |
225 | **/\r | |
226 | BOOLEAN\r | |
227 | UhciIsHcWorking (\r | |
228 | IN EFI_PCI_IO_PROTOCOL *PciIo\r | |
229 | )\r | |
230 | ;\r | |
231 | \r | |
232 | \r | |
233 | /**\r | |
234 | Set the UHCI frame list base address. It can't use\r | |
235 | UhciWriteReg which access memory in UINT16.\r | |
236 | \r | |
237 | @param PciIo The EFI_PCI_IO_PROTOCOL to use\r | |
238 | @param Addr Address to set\r | |
239 | \r | |
240 | @return VOID\r | |
241 | \r | |
242 | **/\r | |
243 | VOID\r | |
244 | UhciSetFrameListBaseAddr (\r | |
245 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
246 | IN VOID *Addr\r | |
247 | )\r | |
248 | ;\r | |
249 | \r | |
250 | \r | |
251 | /**\r | |
252 | Disable USB Emulation\r | |
253 | \r | |
254 | @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use\r | |
255 | \r | |
256 | @return VOID\r | |
257 | \r | |
258 | **/\r | |
259 | VOID\r | |
260 | UhciTurnOffUsbEmulation (\r | |
261 | IN EFI_PCI_IO_PROTOCOL *PciIo\r | |
262 | )\r | |
263 | ;\r | |
264 | #endif\r |