projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 4b1bf81c | 1 | /** @file\r |
| 2 | Private Header file for Usb Host Controller PEIM\r | |
| 3 | \r | |
| 8284b179 | 4 | Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r |
| 4b1bf81c | 5 | \r |
| 6 | This program and the accompanying materials\r | |
| 7 | are licensed and made available under the terms and conditions\r | |
| 8 | of the BSD License which accompanies this distribution. The\r | |
| 9 | full text of the license may be found at\r | |
| 10 | http://opensource.org/licenses/bsd-license.php\r | |
| 11 | \r | |
| 12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 14 | \r | |
| 15 | **/\r | |
| 16 | \r | |
| 17 | #ifndef _RECOVERY_UHC_H_\r | |
| 18 | #define _RECOVERY_UHC_H_\r | |
| 19 | \r | |
| 20 | \r | |
| 21 | #include <PiPei.h>\r | |
| 22 | \r | |
| 23 | #include <Ppi/UsbController.h>\r | |
| 24 | #include <Ppi/UsbHostController.h>\r | |
| 8284b179 SZ |
25 | #include <Ppi/IoMmu.h>\r |
| 26 | #include <Ppi/EndOfPeiPhase.h>\r | |
| 4b1bf81c | 27 | \r |
| 28 | #include <Library/DebugLib.h>\r | |
| 29 | #include <Library/PeimEntryPoint.h>\r | |
| 30 | #include <Library/PeiServicesLib.h>\r | |
| 31 | #include <Library/BaseMemoryLib.h>\r | |
| 32 | #include <Library/TimerLib.h>\r | |
| 33 | #include <Library/IoLib.h>\r | |
| 34 | #include <Library/PeiServicesLib.h>\r | |
| 35 | \r | |
| 36 | #define USB_SLOW_SPEED_DEVICE 0x01\r | |
| 37 | #define USB_FULL_SPEED_DEVICE 0x02\r | |
| 38 | \r | |
| 39 | //\r | |
| 40 | // One memory block uses 16 page\r | |
| 41 | //\r | |
| 42 | #define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 16\r | |
| 43 | \r | |
| 44 | #define USBCMD 0 /* Command Register Offset 00-01h */\r | |
| 45 | #define USBCMD_RS BIT0 /* Run/Stop */\r | |
| 46 | #define USBCMD_HCRESET BIT1 /* Host reset */\r | |
| 47 | #define USBCMD_GRESET BIT2 /* Global reset */\r | |
| 48 | #define USBCMD_EGSM BIT3 /* Global Suspend Mode */\r | |
| 49 | #define USBCMD_FGR BIT4 /* Force Global Resume */\r | |
| 50 | #define USBCMD_SWDBG BIT5 /* SW Debug mode */\r | |
| 51 | #define USBCMD_CF BIT6 /* Config Flag (sw only) */\r | |
| 52 | #define USBCMD_MAXP BIT7 /* Max Packet (0 = 32, 1 = 64) */\r | |
| 53 | \r | |
| 54 | /* Status register */\r | |
| 55 | #define USBSTS 2 /* Status Register Offset 02-03h */\r | |
| 56 | #define USBSTS_USBINT BIT0 /* Interrupt due to IOC */\r | |
| 57 | #define USBSTS_ERROR BIT1 /* Interrupt due to error */\r | |
| 58 | #define USBSTS_RD BIT2 /* Resume Detect */\r | |
| 59 | #define USBSTS_HSE BIT3 /* Host System Error - basically PCI problems */\r | |
| 60 | #define USBSTS_HCPE BIT4 /* Host Controller Process Error - the scripts were buggy */\r | |
| 61 | #define USBSTS_HCH BIT5 /* HC Halted */\r | |
| 62 | \r | |
| 63 | /* Interrupt enable register */\r | |
| 64 | #define USBINTR 4 /* Interrupt Enable Register 04-05h */\r | |
| 65 | #define USBINTR_TIMEOUT BIT0 /* Timeout/CRC error enable */\r | |
| 66 | #define USBINTR_RESUME BIT1 /* Resume interrupt enable */\r | |
| 67 | #define USBINTR_IOC BIT2 /* Interrupt On Complete enable */\r | |
| 68 | #define USBINTR_SP BIT3 /* Short packet interrupt enable */\r | |
| 69 | \r | |
| 70 | /* Frame Number Register Offset 06-08h */\r | |
| 71 | #define USBFRNUM 6\r | |
| 72 | \r | |
| 73 | /* Frame List Base Address Register Offset 08-0Bh */\r | |
| 74 | #define USBFLBASEADD 8\r | |
| 75 | \r | |
| 76 | /* Start of Frame Modify Register Offset 0Ch */\r | |
| 77 | #define USBSOF 0x0c\r | |
| 78 | \r | |
| 79 | /* USB port status and control registers */\r | |
| 80 | #define USBPORTSC1 0x10 /*Port 1 offset 10-11h */\r | |
| 81 | #define USBPORTSC2 0x12 /*Port 2 offset 12-13h */\r | |
| 82 | \r | |
| 83 | #define USBPORTSC_CCS BIT0 /* Current Connect Status ("device present") */\r | |
| 84 | #define USBPORTSC_CSC BIT1 /* Connect Status Change */\r | |
| 85 | #define USBPORTSC_PED BIT2 /* Port Enable / Disable */\r | |
| 86 | #define USBPORTSC_PEDC BIT3 /* Port Enable / Disable Change */\r | |
| 87 | #define USBPORTSC_LSL BIT4 /* Line Status Low bit*/\r | |
| 88 | #define USBPORTSC_LSH BIT5 /* Line Status High bit*/\r | |
| 89 | #define USBPORTSC_RD BIT6 /* Resume Detect */\r | |
| 90 | #define USBPORTSC_LSDA BIT8 /* Low Speed Device Attached */\r | |
| 91 | #define USBPORTSC_PR BIT9 /* Port Reset */\r | |
| 92 | #define USBPORTSC_SUSP BIT12 /* Suspend */\r | |
| 93 | \r | |
| 94 | #define SETUP_PACKET_ID 0x2D\r | |
| 95 | #define INPUT_PACKET_ID 0x69\r | |
| 96 | #define OUTPUT_PACKET_ID 0xE1\r | |
| 97 | #define ERROR_PACKET_ID 0x55\r | |
| 98 | \r | |
| ca243131 | 99 | #define STALL_1_MICRO_SECOND 1\r |
| 4b1bf81c | 100 | #define STALL_1_MILLI_SECOND 1000\r |
| 101 | \r | |
| 102 | \r | |
| 103 | #pragma pack(1)\r | |
| 104 | \r | |
| 105 | typedef struct {\r | |
| 106 | UINT32 FrameListPtrTerminate : 1;\r | |
| 107 | UINT32 FrameListPtrQSelect : 1;\r | |
| 108 | UINT32 FrameListRsvd : 2;\r | |
| 109 | UINT32 FrameListPtr : 28;\r | |
| 110 | } FRAMELIST_ENTRY;\r | |
| 111 | \r | |
| 112 | typedef struct {\r | |
| 113 | UINT32 QHHorizontalTerminate : 1;\r | |
| 114 | UINT32 QHHorizontalQSelect : 1;\r | |
| 115 | UINT32 QHHorizontalRsvd : 2;\r | |
| 116 | UINT32 QHHorizontalPtr : 28;\r | |
| 117 | UINT32 QHVerticalTerminate : 1;\r | |
| 118 | UINT32 QHVerticalQSelect : 1;\r | |
| 119 | UINT32 QHVerticalRsvd : 2;\r | |
| 120 | UINT32 QHVerticalPtr : 28;\r | |
| 121 | } QUEUE_HEAD;\r | |
| 122 | \r | |
| 123 | typedef struct {\r | |
| 124 | QUEUE_HEAD QueueHead;\r | |
| 125 | UINT32 Reserved1;\r | |
| 126 | UINT32 Reserved2;\r | |
| 127 | VOID *PtrNext;\r | |
| 128 | VOID *PtrDown;\r | |
| 129 | VOID *Reserved3;\r | |
| 130 | UINT32 Reserved4;\r | |
| 131 | } QH_STRUCT;\r | |
| 132 | \r | |
| 133 | typedef struct {\r | |
| 134 | UINT32 TDLinkPtrTerminate : 1;\r | |
| 135 | UINT32 TDLinkPtrQSelect : 1;\r | |
| 136 | UINT32 TDLinkPtrDepthSelect : 1;\r | |
| 137 | UINT32 TDLinkPtrRsvd : 1;\r | |
| 138 | UINT32 TDLinkPtr : 28;\r | |
| 139 | UINT32 TDStatusActualLength : 11;\r | |
| 140 | UINT32 TDStatusRsvd : 5;\r | |
| 141 | UINT32 TDStatus : 8;\r | |
| 142 | UINT32 TDStatusIOC : 1;\r | |
| 143 | UINT32 TDStatusIOS : 1;\r | |
| 144 | UINT32 TDStatusLS : 1;\r | |
| 145 | UINT32 TDStatusErr : 2;\r | |
| 146 | UINT32 TDStatusSPD : 1;\r | |
| 147 | UINT32 TDStatusRsvd2 : 2;\r | |
| 148 | UINT32 TDTokenPID : 8;\r | |
| 149 | UINT32 TDTokenDevAddr : 7;\r | |
| 150 | UINT32 TDTokenEndPt : 4;\r | |
| 151 | UINT32 TDTokenDataToggle : 1;\r | |
| 152 | UINT32 TDTokenRsvd : 1;\r | |
| 153 | UINT32 TDTokenMaxLen : 11;\r | |
| 154 | UINT32 TDBufferPtr;\r | |
| 155 | } TD;\r | |
| 156 | \r | |
| 157 | typedef struct {\r | |
| 158 | TD TDData;\r | |
| 159 | UINT8 *PtrTDBuffer;\r | |
| 160 | VOID *PtrNextTD;\r | |
| 161 | VOID *PtrNextQH;\r | |
| 162 | UINT16 TDBufferLength;\r | |
| 163 | UINT16 Reserved;\r | |
| 164 | } TD_STRUCT;\r | |
| 165 | \r | |
| 166 | #pragma pack()\r | |
| 167 | \r | |
| 168 | typedef struct _MEMORY_MANAGE_HEADER MEMORY_MANAGE_HEADER;\r | |
| 169 | \r | |
| 170 | struct _MEMORY_MANAGE_HEADER {\r | |
| 171 | UINT8 *BitArrayPtr;\r | |
| 172 | UINTN BitArraySizeInBytes;\r | |
| 173 | UINT8 *MemoryBlockPtr;\r | |
| 174 | UINTN MemoryBlockSizeInBytes;\r | |
| 175 | MEMORY_MANAGE_HEADER *Next;\r | |
| 176 | };\r | |
| 177 | \r | |
| 178 | #define USB_UHC_DEV_SIGNATURE SIGNATURE_32 ('p', 'u', 'h', 'c')\r | |
| 179 | typedef struct {\r | |
| 180 | UINTN Signature;\r | |
| 181 | PEI_USB_HOST_CONTROLLER_PPI UsbHostControllerPpi;\r | |
| 8284b179 | 182 | EDKII_IOMMU_PPI *IoMmu;\r |
| 4b1bf81c | 183 | EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;\r |
| 8284b179 SZ |
184 | //\r |
| 185 | // EndOfPei callback is used to stop the UHC DMA operation\r | |
| 186 | // after exit PEI phase.\r | |
| 187 | //\r | |
| 188 | EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;\r | |
| 4b1bf81c | 189 | \r |
| 190 | UINT32 UsbHostControllerBaseAddress;\r | |
| 191 | FRAMELIST_ENTRY *FrameListEntry;\r | |
| 192 | QH_STRUCT *ConfigQH;\r | |
| 193 | QH_STRUCT *BulkQH;\r | |
| 194 | //\r | |
| 195 | // Header1 used for QH,TD memory blocks management\r | |
| 196 | //\r | |
| 197 | MEMORY_MANAGE_HEADER *Header1;\r | |
| 198 | \r | |
| 199 | } USB_UHC_DEV;\r | |
| 200 | \r | |
| 201 | #define PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS(a) CR (a, USB_UHC_DEV, UsbHostControllerPpi, USB_UHC_DEV_SIGNATURE)\r | |
| 8284b179 | 202 | #define PEI_RECOVERY_USB_UHC_DEV_FROM_THIS_NOTIFY(a) CR (a, USB_UHC_DEV, EndOfPeiNotifyList, USB_UHC_DEV_SIGNATURE)\r |
| 4b1bf81c | 203 | \r |
| 204 | /**\r | |
| 205 | Submits control transfer to a target USB device.\r | |
| 206 | \r | |
| 207 | @param PeiServices The pointer of EFI_PEI_SERVICES.\r | |
| 208 | @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.\r | |
| 209 | @param DeviceAddress The target device address.\r | |
| 210 | @param DeviceSpeed Target device speed.\r | |
| 211 | @param MaximumPacketLength Maximum packet size the default control transfer \r | |
| 212 | endpoint is capable of sending or receiving.\r | |
| 213 | @param Request USB device request to send.\r | |
| 214 | @param TransferDirection Specifies the data direction for the data stage.\r | |
| 215 | @param Data Data buffer to be transmitted or received from USB device.\r | |
| 216 | @param DataLength The size (in bytes) of the data buffer.\r | |
| 217 | @param TimeOut Indicates the maximum timeout, in millisecond.\r | |
| 218 | @param TransferResult Return the result of this control transfer.\r | |
| 219 | \r | |
| 220 | @retval EFI_SUCCESS Transfer was completed successfully.\r | |
| 221 | @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resources.\r | |
| 222 | @retval EFI_INVALID_PARAMETER Some parameters are invalid.\r | |
| 223 | @retval EFI_TIMEOUT Transfer failed due to timeout.\r | |
| 224 | @retval EFI_DEVICE_ERROR Transfer failed due to host controller or device error.\r | |
| 225 | \r | |
| 226 | **/\r | |
| 227 | EFI_STATUS\r | |
| 228 | EFIAPI\r | |
| 229 | UhcControlTransfer (\r | |
| 230 | IN EFI_PEI_SERVICES **PeiServices,\r | |
| 231 | IN PEI_USB_HOST_CONTROLLER_PPI * This,\r | |
| 232 | IN UINT8 DeviceAddress,\r | |
| 233 | IN UINT8 DeviceSpeed,\r | |
| 234 | IN UINT8 MaximumPacketLength,\r | |
| 235 | IN EFI_USB_DEVICE_REQUEST * Request,\r | |
| 236 | IN EFI_USB_DATA_DIRECTION TransferDirection,\r | |
| 237 | IN OUT VOID *Data OPTIONAL,\r | |
| 238 | IN OUT UINTN *DataLength OPTIONAL,\r | |
| 239 | IN UINTN TimeOut,\r | |
| 240 | OUT UINT32 *TransferResult\r | |
| 241 | );\r | |
| 242 | \r | |
| 243 | /**\r | |
| 244 | Submits bulk transfer to a bulk endpoint of a USB device.\r | |
| 245 | \r | |
| 246 | @param PeiServices The pointer of EFI_PEI_SERVICES.\r | |
| 247 | @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.\r | |
| 248 | @param DeviceAddress Target device address.\r | |
| 249 | @param EndPointAddress Endpoint number and its direction in bit 7.\r | |
| 250 | @param MaximumPacketLength Maximum packet size the endpoint is capable of \r | |
| 251 | sending or receiving.\r | |
| 252 | @param Data Array of pointers to the buffers of data to transmit \r | |
| 253 | from or receive into.\r | |
| 254 | @param DataLength The lenght of the data buffer.\r | |
| 255 | @param DataToggle On input, the initial data toggle for the transfer;\r | |
| 256 | On output, it is updated to to next data toggle to use of \r | |
| 257 | the subsequent bulk transfer.\r | |
| 258 | @param TimeOut Indicates the maximum time, in millisecond, which the\r | |
| 259 | transfer is allowed to complete.\r | |
| 260 | @param TransferResult A pointer to the detailed result information of the\r | |
| 261 | bulk transfer.\r | |
| 262 | \r | |
| 263 | @retval EFI_SUCCESS The transfer was completed successfully.\r | |
| 264 | @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.\r | |
| 265 | @retval EFI_INVALID_PARAMETER Parameters are invalid.\r | |
| 266 | @retval EFI_TIMEOUT The transfer failed due to timeout.\r | |
| 267 | @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.\r | |
| 268 | \r | |
| 269 | **/\r | |
| 270 | EFI_STATUS\r | |
| 271 | EFIAPI\r | |
| 272 | UhcBulkTransfer (\r | |
| 273 | IN EFI_PEI_SERVICES **PeiServices,\r | |
| 274 | IN PEI_USB_HOST_CONTROLLER_PPI *This,\r | |
| 275 | IN UINT8 DeviceAddress,\r | |
| 276 | IN UINT8 EndPointAddress,\r | |
| 277 | IN UINT8 MaximumPacketLength,\r | |
| 278 | IN OUT VOID *Data,\r | |
| 279 | IN OUT UINTN *DataLength,\r | |
| 280 | IN OUT UINT8 *DataToggle,\r | |
| 281 | IN UINTN TimeOut,\r | |
| 282 | OUT UINT32 *TransferResult\r | |
| 283 | );\r | |
| 284 | \r | |
| 285 | /**\r | |
| 286 | Retrieves the number of root hub ports.\r | |
| 287 | \r | |
| 288 | @param[in] PeiServices The pointer to the PEI Services Table.\r | |
| 289 | @param[in] This The pointer to this instance of the \r | |
| 290 | PEI_USB_HOST_CONTROLLER_PPI.\r | |
| 291 | @param[out] PortNumber The pointer to the number of the root hub ports. \r | |
| 292 | \r | |
| 293 | @retval EFI_SUCCESS The port number was retrieved successfully.\r | |
| 294 | @retval EFI_INVALID_PARAMETER PortNumber is NULL.\r | |
| 295 | \r | |
| 296 | **/\r | |
| 297 | EFI_STATUS\r | |
| 298 | EFIAPI\r | |
| 299 | UhcGetRootHubPortNumber (\r | |
| 300 | IN EFI_PEI_SERVICES **PeiServices,\r | |
| 301 | IN PEI_USB_HOST_CONTROLLER_PPI *This,\r | |
| 302 | OUT UINT8 *PortNumber\r | |
| 303 | );\r | |
| 304 | \r | |
| 305 | /**\r | |
| 306 | Retrieves the current status of a USB root hub port.\r | |
| 307 | \r | |
| 308 | @param PeiServices The pointer of EFI_PEI_SERVICES.\r | |
| 309 | @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.\r | |
| 310 | @param PortNumber The root hub port to retrieve the state from. \r | |
| 311 | @param PortStatus Variable to receive the port state.\r | |
| 312 | \r | |
| 313 | @retval EFI_SUCCESS The status of the USB root hub port specified.\r | |
| 314 | by PortNumber was returned in PortStatus.\r | |
| 315 | @retval EFI_INVALID_PARAMETER PortNumber is invalid.\r | |
| 316 | \r | |
| 317 | **/\r | |
| 318 | EFI_STATUS\r | |
| 319 | EFIAPI\r | |
| 320 | UhcGetRootHubPortStatus (\r | |
| 321 | IN EFI_PEI_SERVICES **PeiServices,\r | |
| 322 | IN PEI_USB_HOST_CONTROLLER_PPI *This,\r | |
| 323 | IN UINT8 PortNumber,\r | |
| 324 | OUT EFI_USB_PORT_STATUS *PortStatus\r | |
| 325 | );\r | |
| 326 | \r | |
| 327 | /**\r | |
| 328 | Sets a feature for the specified root hub port.\r | |
| 329 | \r | |
| 330 | @param PeiServices The pointer of EFI_PEI_SERVICES\r | |
| 331 | @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI\r | |
| 332 | @param PortNumber Root hub port to set.\r | |
| 333 | @param PortFeature Feature to set.\r | |
| 334 | \r | |
| 335 | @retval EFI_SUCCESS The feature specified by PortFeature was set.\r | |
| 336 | @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.\r | |
| 337 | @retval EFI_TIMEOUT The time out occurred.\r | |
| 338 | \r | |
| 339 | **/\r | |
| 340 | EFI_STATUS\r | |
| 341 | EFIAPI\r | |
| 342 | UhcSetRootHubPortFeature (\r | |
| 343 | IN EFI_PEI_SERVICES **PeiServices,\r | |
| 344 | IN PEI_USB_HOST_CONTROLLER_PPI *This,\r | |
| 345 | IN UINT8 PortNumber,\r | |
| 346 | IN EFI_USB_PORT_FEATURE PortFeature\r | |
| 347 | );\r | |
| 348 | \r | |
| 349 | /**\r | |
| 350 | Clears a feature for the specified root hub port.\r | |
| 351 | \r | |
| 352 | @param PeiServices The pointer of EFI_PEI_SERVICES.\r | |
| 353 | @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.\r | |
| 354 | @param PortNumber Specifies the root hub port whose feature\r | |
| 355 | is requested to be cleared.\r | |
| 356 | @param PortFeature Indicates the feature selector associated with the\r | |
| 357 | feature clear request.\r | |
| 358 | \r | |
| 359 | @retval EFI_SUCCESS The feature specified by PortFeature was cleared \r | |
| 360 | for the USB root hub port specified by PortNumber.\r | |
| 361 | @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.\r | |
| 362 | \r | |
| 363 | **/\r | |
| 364 | EFI_STATUS\r | |
| 365 | EFIAPI\r | |
| 366 | UhcClearRootHubPortFeature (\r | |
| 367 | IN EFI_PEI_SERVICES **PeiServices,\r | |
| 368 | IN PEI_USB_HOST_CONTROLLER_PPI *This,\r | |
| 369 | IN UINT8 PortNumber,\r | |
| 370 | IN EFI_USB_PORT_FEATURE PortFeature\r | |
| 371 | );\r | |
| 372 | \r | |
| 373 | /**\r | |
| 374 | Initialize UHCI.\r | |
| 375 | \r | |
| 376 | @param UhcDev UHCI Device.\r | |
| 377 | \r | |
| 378 | @retval EFI_SUCCESS UHCI successfully initialized.\r | |
| 379 | @retval EFI_OUT_OF_RESOURCES Resource can not be allocated.\r | |
| 380 | \r | |
| 381 | **/\r | |
| 382 | EFI_STATUS\r | |
| 383 | InitializeUsbHC (\r | |
| 384 | IN USB_UHC_DEV *UhcDev\r | |
| 385 | );\r | |
| 386 | \r | |
| 387 | /**\r | |
| 388 | Create Frame List Structure.\r | |
| 389 | \r | |
| 390 | @param UhcDev UHCI device.\r | |
| 391 | \r | |
| 392 | @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r | |
| 393 | @retval EFI_SUCCESS Success.\r | |
| 394 | \r | |
| 395 | **/\r | |
| 396 | EFI_STATUS\r | |
| 397 | CreateFrameList (\r | |
| 398 | USB_UHC_DEV *UhcDev\r | |
| 399 | );\r | |
| 400 | \r | |
| 401 | /**\r | |
| 402 | Read a 16bit width data from Uhc HC IO space register.\r | |
| 403 | \r | |
| 404 | @param UhcDev The UHCI device.\r | |
| 405 | @param Port The IO space address of the register.\r | |
| 406 | \r | |
| 407 | @retval the register content read.\r | |
| 408 | \r | |
| 409 | **/\r | |
| 410 | UINT16\r | |
| 411 | USBReadPortW (\r | |
| 412 | IN USB_UHC_DEV *UhcDev,\r | |
| 413 | IN UINT32 Port\r | |
| 414 | );\r | |
| 415 | \r | |
| 416 | /**\r | |
| 417 | Write a 16bit width data into Uhc HC IO space register.\r | |
| 418 | \r | |
| 419 | @param UhcDev The UHCI device.\r | |
| 420 | @param Port The IO space address of the register.\r | |
| 421 | @param Data The data written into the register.\r | |
| 422 | \r | |
| 423 | **/\r | |
| 424 | VOID\r | |
| 425 | USBWritePortW (\r | |
| 426 | IN USB_UHC_DEV *UhcDev,\r | |
| 427 | IN UINT32 Port,\r | |
| 428 | IN UINT16 Data\r | |
| 429 | );\r | |
| 430 | \r | |
| 431 | /**\r | |
| 432 | Write a 32bit width data into Uhc HC IO space register.\r | |
| 433 | \r | |
| 434 | @param UhcDev The UHCI device.\r | |
| 435 | @param Port The IO space address of the register.\r | |
| 436 | @param Data The data written into the register.\r | |
| 437 | \r | |
| 438 | **/\r | |
| 439 | VOID\r | |
| 440 | USBWritePortDW (\r | |
| 441 | IN USB_UHC_DEV *UhcDev,\r | |
| 442 | IN UINT32 Port,\r | |
| 443 | IN UINT32 Data\r | |
| 444 | );\r | |
| 445 | \r | |
| 446 | /**\r | |
| 447 | Clear the content of UHCI's Status Register.\r | |
| 448 | \r | |
| 449 | @param UhcDev The UHCI device.\r | |
| 450 | @param StatusAddr The IO space address of the register.\r | |
| 451 | \r | |
| 452 | **/\r | |
| 453 | VOID\r | |
| 454 | ClearStatusReg (\r | |
| 455 | IN USB_UHC_DEV *UhcDev,\r | |
| 456 | IN UINT32 StatusAddr\r | |
| 457 | );\r | |
| 458 | \r | |
| 459 | /**\r | |
| 460 | Check whether the host controller operates well.\r | |
| 461 | \r | |
| 462 | @param UhcDev The UHCI device.\r | |
| 463 | @param StatusRegAddr The io address of status register.\r | |
| 464 | \r | |
| 465 | @retval TRUE Host controller is working.\r | |
| 466 | @retval FALSE Host controller is halted or system error.\r | |
| 467 | \r | |
| 468 | **/\r | |
| 469 | BOOLEAN\r | |
| 470 | IsStatusOK (\r | |
| 471 | IN USB_UHC_DEV *UhcDev,\r | |
| 472 | IN UINT32 StatusRegAddr\r | |
| 473 | );\r | |
| 474 | \r | |
| 475 | /**\r | |
| 476 | Get Current Frame Number.\r | |
| 477 | \r | |
| 478 | @param UhcDev The UHCI device.\r | |
| 479 | @param FrameNumberAddr The address of frame list register.\r | |
| 480 | \r | |
| 481 | @retval The content of the frame list register.\r | |
| 482 | \r | |
| 483 | **/\r | |
| 484 | UINT16\r | |
| 485 | GetCurrentFrameNumber (\r | |
| 486 | IN USB_UHC_DEV *UhcDev,\r | |
| 487 | IN UINT32 FrameNumberAddr\r | |
| 488 | );\r | |
| 489 | \r | |
| 490 | /**\r | |
| 491 | Set Frame List Base Address.\r | |
| 492 | \r | |
| 493 | @param UhcDev The UHCI device.\r | |
| 494 | @param FrameListRegAddr The address of frame list register.\r | |
| 495 | @param Addr The address of frame list table.\r | |
| 496 | \r | |
| 497 | **/\r | |
| 498 | VOID\r | |
| 499 | SetFrameListBaseAddress (\r | |
| 500 | IN USB_UHC_DEV *UhcDev,\r | |
| 501 | IN UINT32 FrameListRegAddr,\r | |
| 502 | IN UINT32 Addr\r | |
| 503 | );\r | |
| 504 | \r | |
| 505 | /**\r | |
| 506 | Create QH and initialize.\r | |
| 507 | \r | |
| 508 | @param UhcDev The UHCI device.\r | |
| 509 | @param PtrQH Place to store QH_STRUCT pointer.\r | |
| 510 | \r | |
| 511 | @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r | |
| 512 | @retval EFI_SUCCESS Success.\r | |
| 513 | \r | |
| 514 | **/\r | |
| 515 | EFI_STATUS\r | |
| 516 | CreateQH (\r | |
| 517 | IN USB_UHC_DEV *UhcDev,\r | |
| 518 | OUT QH_STRUCT **PtrQH\r | |
| 519 | );\r | |
| 520 | \r | |
| 521 | /**\r | |
| 522 | Set the horizontal link pointer in QH.\r | |
| 523 | \r | |
| 524 | @param PtrQH Place to store QH_STRUCT pointer.\r | |
| 525 | @param PtrNext Place to the next QH_STRUCT.\r | |
| 526 | \r | |
| 527 | **/\r | |
| 528 | VOID\r | |
| 529 | SetQHHorizontalLinkPtr (\r | |
| 530 | IN QH_STRUCT *PtrQH,\r | |
| 531 | IN VOID *PtrNext\r | |
| 532 | );\r | |
| 533 | \r | |
| 534 | /**\r | |
| 535 | Get the horizontal link pointer in QH.\r | |
| 536 | \r | |
| 537 | @param PtrQH Place to store QH_STRUCT pointer.\r | |
| 538 | \r | |
| 539 | @retval The horizontal link pointer in QH.\r | |
| 540 | \r | |
| 541 | **/\r | |
| 542 | VOID *\r | |
| 543 | GetQHHorizontalLinkPtr (\r | |
| 544 | IN QH_STRUCT *PtrQH\r | |
| 545 | );\r | |
| 546 | \r | |
| 547 | /**\r | |
| 548 | Set a QH or TD horizontally to be connected with a specific QH.\r | |
| 549 | \r | |
| 550 | @param PtrQH Place to store QH_STRUCT pointer.\r | |
| 551 | @param IsQH Specify QH or TD is connected.\r | |
| 552 | \r | |
| 553 | **/\r | |
| 554 | VOID\r | |
| 555 | SetQHHorizontalQHorTDSelect (\r | |
| 556 | IN QH_STRUCT *PtrQH,\r | |
| 557 | IN BOOLEAN IsQH\r | |
| 558 | );\r | |
| 559 | \r | |
| 560 | /**\r | |
| 561 | Set the horizontal validor bit in QH.\r | |
| 562 | \r | |
| 563 | @param PtrQH Place to store QH_STRUCT pointer.\r | |
| 564 | @param IsValid Specify the horizontal linker is valid or not.\r | |
| 565 | \r | |
| 566 | **/\r | |
| 567 | VOID\r | |
| 568 | SetQHHorizontalValidorInvalid (\r | |
| 569 | IN QH_STRUCT *PtrQH,\r | |
| 570 | IN BOOLEAN IsValid\r | |
| 571 | );\r | |
| 572 | \r | |
| 573 | /**\r | |
| 574 | Set the vertical link pointer in QH.\r | |
| 575 | \r | |
| 576 | @param PtrQH Place to store QH_STRUCT pointer.\r | |
| 577 | @param PtrNext Place to the next QH_STRUCT.\r | |
| 578 | \r | |
| 579 | **/\r | |
| 580 | VOID\r | |
| 581 | SetQHVerticalLinkPtr (\r | |
| 582 | IN QH_STRUCT *PtrQH,\r | |
| 583 | IN VOID *PtrNext\r | |
| 584 | );\r | |
| 585 | \r | |
| 586 | /**\r | |
| 587 | Set a QH or TD vertically to be connected with a specific QH.\r | |
| 588 | \r | |
| 589 | @param PtrQH Place to store QH_STRUCT pointer.\r | |
| 590 | @param IsQH Specify QH or TD is connected.\r | |
| 591 | \r | |
| 592 | **/\r | |
| 593 | VOID\r | |
| 594 | SetQHVerticalQHorTDSelect (\r | |
| 595 | IN QH_STRUCT *PtrQH,\r | |
| 596 | IN BOOLEAN IsQH\r | |
| 597 | );\r | |
| 598 | \r | |
| 599 | /**\r | |
| 600 | Set the vertical validor bit in QH.\r | |
| 601 | \r | |
| 602 | @param PtrQH Place to store QH_STRUCT pointer.\r | |
| 603 | @param IsValid Specify the vertical linker is valid or not.\r | |
| 604 | \r | |
| 605 | **/\r | |
| 606 | VOID\r | |
| 607 | SetQHVerticalValidorInvalid (\r | |
| 608 | IN QH_STRUCT *PtrQH,\r | |
| 609 | IN BOOLEAN IsValid\r | |
| 610 | );\r | |
| 611 | \r | |
| 612 | /**\r | |
| 613 | Get the vertical validor bit in QH.\r | |
| 614 | \r | |
| 615 | @param PtrQH Place to store QH_STRUCT pointer.\r | |
| 616 | \r | |
| 617 | @retval The vertical linker is valid or not.\r | |
| 618 | \r | |
| 619 | **/\r | |
| 620 | BOOLEAN\r | |
| 621 | GetQHHorizontalValidorInvalid (\r | |
| 622 | IN QH_STRUCT *PtrQH\r | |
| 623 | );\r | |
| 624 | \r | |
| 625 | /**\r | |
| 626 | Allocate TD or QH Struct.\r | |
| 627 | \r | |
| 628 | @param UhcDev The UHCI device.\r | |
| 629 | @param Size The size of allocation.\r | |
| 630 | @param PtrStruct Place to store TD_STRUCT pointer.\r | |
| 631 | \r | |
| 632 | @return EFI_SUCCESS Allocate successfully.\r | |
| 633 | @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.\r | |
| 634 | \r | |
| 635 | **/\r | |
| 636 | EFI_STATUS\r | |
| 637 | AllocateTDorQHStruct (\r | |
| 638 | IN USB_UHC_DEV *UhcDev,\r | |
| 639 | IN UINT32 Size,\r | |
| 640 | OUT VOID **PtrStruct\r | |
| 641 | );\r | |
| 642 | \r | |
| 643 | /**\r | |
| 644 | Create a TD Struct.\r | |
| 645 | \r | |
| 646 | @param UhcDev The UHCI device.\r | |
| 647 | @param PtrTD Place to store TD_STRUCT pointer.\r | |
| 648 | \r | |
| 649 | @return EFI_SUCCESS Allocate successfully.\r | |
| 650 | @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.\r | |
| 651 | \r | |
| 652 | **/\r | |
| 653 | EFI_STATUS\r | |
| 654 | CreateTD (\r | |
| 655 | IN USB_UHC_DEV *UhcDev,\r | |
| 656 | OUT TD_STRUCT **PtrTD\r | |
| 657 | );\r | |
| 658 | \r | |
| 659 | /**\r | |
| 660 | Generate Setup Stage TD.\r | |
| 661 | \r | |
| 662 | @param UhcDev The UHCI device.\r | |
| 663 | @param DevAddr Device address.\r | |
| 664 | @param Endpoint Endpoint number.\r | |
| 665 | @param DeviceSpeed Device Speed.\r | |
| 8284b179 SZ |
666 | @param DevRequest CPU memory address of request structure buffer to transfer.\r |
| 667 | @param RequestPhy PCI memory address of request structure buffer to transfer.\r | |
| 4b1bf81c | 668 | @param RequestLen Request length.\r |
| 669 | @param PtrTD TD_STRUCT generated.\r | |
| 670 | \r | |
| 671 | @return EFI_SUCCESS Generate setup stage TD successfully.\r | |
| 672 | @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.\r | |
| 673 | \r | |
| 674 | **/\r | |
| 675 | EFI_STATUS\r | |
| 676 | GenSetupStageTD (\r | |
| 677 | IN USB_UHC_DEV *UhcDev,\r | |
| 678 | IN UINT8 DevAddr,\r | |
| 679 | IN UINT8 Endpoint,\r | |
| 680 | IN UINT8 DeviceSpeed,\r | |
| 681 | IN UINT8 *DevRequest,\r | |
| 8284b179 | 682 | IN UINT8 *RequestPhy,\r |
| 4b1bf81c | 683 | IN UINT8 RequestLen,\r |
| 684 | OUT TD_STRUCT **PtrTD\r | |
| 685 | );\r | |
| 686 | \r | |
| 687 | /**\r | |
| 688 | Generate Data Stage TD.\r | |
| 689 | \r | |
| 690 | @param UhcDev The UHCI device.\r | |
| 691 | @param DevAddr Device address.\r | |
| 692 | @param Endpoint Endpoint number.\r | |
| 8284b179 SZ |
693 | @param PtrData CPU memory address of user data buffer to transfer.\r |
| 694 | @param DataPhy PCI memory address of user data buffer to transfer.\r | |
| 4b1bf81c | 695 | @param Len Data length.\r |
| 696 | @param PktID PacketID.\r | |
| 697 | @param Toggle Data toggle value.\r | |
| 698 | @param DeviceSpeed Device Speed.\r | |
| 699 | @param PtrTD TD_STRUCT generated.\r | |
| 700 | \r | |
| 701 | @return EFI_SUCCESS Generate data stage TD successfully.\r | |
| 702 | @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.\r | |
| 703 | \r | |
| 704 | **/\r | |
| 705 | EFI_STATUS\r | |
| 706 | GenDataTD (\r | |
| 707 | IN USB_UHC_DEV *UhcDev,\r | |
| 708 | IN UINT8 DevAddr,\r | |
| 709 | IN UINT8 Endpoint,\r | |
| 710 | IN UINT8 *PtrData,\r | |
| 8284b179 | 711 | IN UINT8 *DataPhy,\r |
| 4b1bf81c | 712 | IN UINT8 Len,\r |
| 713 | IN UINT8 PktID,\r | |
| 714 | IN UINT8 Toggle,\r | |
| 715 | IN UINT8 DeviceSpeed,\r | |
| 716 | OUT TD_STRUCT **PtrTD\r | |
| 717 | );\r | |
| 718 | \r | |
| 719 | /**\r | |
| 720 | Generate Status Stage TD.\r | |
| 721 | \r | |
| 722 | @param UhcDev The UHCI device.\r | |
| 723 | @param DevAddr Device address.\r | |
| 724 | @param Endpoint Endpoint number.\r | |
| 725 | @param PktID PacketID.\r | |
| 726 | @param DeviceSpeed Device Speed.\r | |
| 727 | @param PtrTD TD_STRUCT generated.\r | |
| 728 | \r | |
| 729 | @return EFI_SUCCESS Generate status stage TD successfully.\r | |
| 730 | @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.\r | |
| 731 | \r | |
| 732 | **/\r | |
| 733 | EFI_STATUS\r | |
| 734 | CreateStatusTD (\r | |
| 735 | IN USB_UHC_DEV *UhcDev,\r | |
| 736 | IN UINT8 DevAddr,\r | |
| 737 | IN UINT8 Endpoint,\r | |
| 738 | IN UINT8 PktID,\r | |
| 739 | IN UINT8 DeviceSpeed,\r | |
| 740 | OUT TD_STRUCT **PtrTD\r | |
| 741 | );\r | |
| 742 | \r | |
| 743 | /**\r | |
| 744 | Set the link pointer validor bit in TD.\r | |
| 745 | \r | |
| 746 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 747 | @param IsValid Specify the linker pointer is valid or not.\r | |
| 748 | \r | |
| 749 | **/\r | |
| 750 | VOID\r | |
| 751 | SetTDLinkPtrValidorInvalid (\r | |
| 752 | IN TD_STRUCT *PtrTDStruct,\r | |
| 753 | IN BOOLEAN IsValid\r | |
| 754 | );\r | |
| 755 | \r | |
| 756 | /**\r | |
| 757 | Set the Link Pointer pointing to a QH or TD.\r | |
| 758 | \r | |
| 759 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 760 | @param IsQH Specify QH or TD is connected.\r | |
| 761 | \r | |
| 762 | **/\r | |
| 763 | VOID\r | |
| 764 | SetTDLinkPtrQHorTDSelect (\r | |
| 765 | IN TD_STRUCT *PtrTDStruct,\r | |
| 766 | IN BOOLEAN IsQH\r | |
| 767 | );\r | |
| 768 | \r | |
| 769 | /**\r | |
| 770 | Set the traverse is depth-first or breadth-first.\r | |
| 771 | \r | |
| 772 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 773 | @param IsDepth Specify the traverse is depth-first or breadth-first.\r | |
| 774 | \r | |
| 775 | **/\r | |
| 776 | VOID\r | |
| 777 | SetTDLinkPtrDepthorBreadth (\r | |
| 778 | IN TD_STRUCT *PtrTDStruct,\r | |
| 779 | IN BOOLEAN IsDepth\r | |
| 780 | );\r | |
| 781 | \r | |
| 782 | /**\r | |
| 783 | Set TD Link Pointer in TD.\r | |
| 784 | \r | |
| 785 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 786 | @param PtrNext Place to the next TD_STRUCT.\r | |
| 787 | \r | |
| 788 | **/\r | |
| 789 | VOID\r | |
| 790 | SetTDLinkPtr (\r | |
| 791 | IN TD_STRUCT *PtrTDStruct,\r | |
| 792 | IN VOID *PtrNext\r | |
| 793 | );\r | |
| 794 | \r | |
| 795 | /**\r | |
| 796 | Get TD Link Pointer.\r | |
| 797 | \r | |
| 798 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 799 | \r | |
| 800 | @retval Get TD Link Pointer in TD.\r | |
| 801 | \r | |
| 802 | **/\r | |
| 803 | VOID*\r | |
| 804 | GetTDLinkPtr (\r | |
| 805 | IN TD_STRUCT *PtrTDStruct\r | |
| 806 | );\r | |
| 807 | \r | |
| 808 | /**\r | |
| 809 | Get the information about whether the Link Pointer field pointing to\r | |
| 810 | a QH or a TD.\r | |
| 811 | \r | |
| 812 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 813 | \r | |
| 814 | @retval whether the Link Pointer field pointing to a QH or a TD.\r | |
| 815 | \r | |
| 816 | **/\r | |
| 817 | BOOLEAN\r | |
| 818 | IsTDLinkPtrQHOrTD (\r | |
| 819 | IN TD_STRUCT *PtrTDStruct\r | |
| 820 | );\r | |
| 821 | \r | |
| 822 | /**\r | |
| 823 | Enable/Disable short packet detection mechanism.\r | |
| 824 | \r | |
| 825 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 826 | @param IsEnable Enable or disable short packet detection mechanism.\r | |
| 827 | \r | |
| 828 | **/\r | |
| 829 | VOID\r | |
| 830 | EnableorDisableTDShortPacket (\r | |
| 831 | IN TD_STRUCT *PtrTDStruct,\r | |
| 832 | IN BOOLEAN IsEnable\r | |
| 833 | );\r | |
| 834 | \r | |
| 835 | /**\r | |
| 836 | Set the max error counter in TD.\r | |
| 837 | \r | |
| 838 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 839 | @param MaxErrors The number of allowable error.\r | |
| 840 | \r | |
| 841 | **/\r | |
| 842 | VOID\r | |
| 843 | SetTDControlErrorCounter (\r | |
| 844 | IN TD_STRUCT *PtrTDStruct,\r | |
| 845 | IN UINT8 MaxErrors\r | |
| 846 | );\r | |
| 847 | \r | |
| 848 | /**\r | |
| 849 | Set the TD is targeting a low-speed device or not.\r | |
| 850 | \r | |
| 851 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 852 | @param IsLowSpeedDevice Whether The device is low-speed.\r | |
| 853 | \r | |
| 854 | **/\r | |
| 855 | VOID\r | |
| 856 | SetTDLoworFullSpeedDevice (\r | |
| 857 | IN TD_STRUCT *PtrTDStruct,\r | |
| 858 | IN BOOLEAN IsLowSpeedDevice\r | |
| 859 | );\r | |
| 860 | \r | |
| 861 | /**\r | |
| 862 | Set the TD is isochronous transfer type or not.\r | |
| 863 | \r | |
| 864 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 865 | @param IsIsochronous Whether the transaction isochronous transfer type.\r | |
| 866 | \r | |
| 867 | **/\r | |
| 868 | VOID\r | |
| 869 | SetTDControlIsochronousorNot (\r | |
| 870 | IN TD_STRUCT *PtrTDStruct,\r | |
| 871 | IN BOOLEAN IsIsochronous\r | |
| 872 | );\r | |
| 873 | \r | |
| 874 | /**\r | |
| 875 | Set if UCHI should issue an interrupt on completion of the frame\r | |
| 876 | in which this TD is executed\r | |
| 877 | \r | |
| 878 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 879 | @param IsSet Whether HC should issue an interrupt on completion.\r | |
| 880 | \r | |
| 881 | **/\r | |
| 882 | VOID\r | |
| 883 | SetorClearTDControlIOC (\r | |
| 884 | IN TD_STRUCT *PtrTDStruct,\r | |
| 885 | IN BOOLEAN IsSet\r | |
| 886 | );\r | |
| 887 | \r | |
| 888 | /**\r | |
| 889 | Set if the TD is active and can be executed.\r | |
| 890 | \r | |
| 891 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 892 | @param IsActive Whether the TD is active and can be executed.\r | |
| 893 | \r | |
| 894 | **/\r | |
| 895 | VOID\r | |
| 896 | SetTDStatusActiveorInactive (\r | |
| 897 | IN TD_STRUCT *PtrTDStruct,\r | |
| 898 | IN BOOLEAN IsActive\r | |
| 899 | );\r | |
| 900 | \r | |
| 901 | /**\r | |
| 902 | Specifies the maximum number of data bytes allowed for the transfer.\r | |
| 903 | \r | |
| 904 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 905 | @param MaxLen The maximum number of data bytes allowed.\r | |
| 906 | \r | |
| 907 | @retval The allowed maximum number of data.\r | |
| 908 | **/\r | |
| 909 | UINT16\r | |
| 910 | SetTDTokenMaxLength (\r | |
| 911 | IN TD_STRUCT *PtrTDStruct,\r | |
| 912 | IN UINT16 MaxLen\r | |
| 913 | );\r | |
| 914 | \r | |
| 915 | /**\r | |
| 916 | Set the data toggle bit to DATA1.\r | |
| 917 | \r | |
| 918 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 919 | \r | |
| 920 | **/\r | |
| 921 | VOID\r | |
| 922 | SetTDTokenDataToggle1 (\r | |
| 923 | IN TD_STRUCT *PtrTDStruct\r | |
| 924 | );\r | |
| 925 | \r | |
| 926 | /**\r | |
| 927 | Set the data toggle bit to DATA0.\r | |
| 928 | \r | |
| 929 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 930 | \r | |
| 931 | **/\r | |
| 932 | VOID\r | |
| 933 | SetTDTokenDataToggle0 (\r | |
| 934 | IN TD_STRUCT *PtrTDStruct\r | |
| 935 | );\r | |
| 936 | \r | |
| 937 | /**\r | |
| 938 | Set EndPoint Number the TD is targeting at.\r | |
| 939 | \r | |
| 940 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 941 | @param EndPoint The Endport number of the target.\r | |
| 942 | \r | |
| 943 | **/\r | |
| 944 | VOID\r | |
| 945 | SetTDTokenEndPoint (\r | |
| 946 | IN TD_STRUCT *PtrTDStruct,\r | |
| 947 | IN UINTN EndPoint\r | |
| 948 | );\r | |
| 949 | \r | |
| 950 | /**\r | |
| 951 | Set Device Address the TD is targeting at.\r | |
| 952 | \r | |
| 953 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 954 | @param DevAddr The Device Address of the target.\r | |
| 955 | \r | |
| 956 | **/\r | |
| 957 | VOID\r | |
| 958 | SetTDTokenDeviceAddress (\r | |
| 959 | IN TD_STRUCT *PtrTDStruct,\r | |
| 960 | IN UINTN DevAddr\r | |
| 961 | );\r | |
| 962 | \r | |
| 963 | /**\r | |
| 964 | Set Packet Identification the TD is targeting at.\r | |
| 965 | \r | |
| 966 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 967 | @param PacketID The Packet Identification of the target.\r | |
| 968 | \r | |
| 969 | **/\r | |
| 970 | VOID\r | |
| 971 | SetTDTokenPacketID (\r | |
| 972 | IN TD_STRUCT *PtrTDStruct,\r | |
| 973 | IN UINT8 PacketID\r | |
| 974 | );\r | |
| 975 | \r | |
| 976 | /**\r | |
| 977 | Set the beginning address of the data buffer that will be used\r | |
| 978 | during the transaction.\r | |
| 979 | \r | |
| 980 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 981 | \r | |
| 982 | **/\r | |
| 983 | VOID\r | |
| 984 | SetTDDataBuffer (\r | |
| 985 | IN TD_STRUCT *PtrTDStruct\r | |
| 986 | );\r | |
| 987 | \r | |
| 988 | /**\r | |
| 989 | Detect whether the TD is active.\r | |
| 990 | \r | |
| 991 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 992 | \r | |
| 993 | @retval The TD is active or not.\r | |
| 994 | \r | |
| 995 | **/\r | |
| 996 | BOOLEAN\r | |
| 997 | IsTDStatusActive (\r | |
| 998 | IN TD_STRUCT *PtrTDStruct\r | |
| 999 | );\r | |
| 1000 | \r | |
| 1001 | /**\r | |
| 1002 | Detect whether the TD is stalled.\r | |
| 1003 | \r | |
| 1004 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 1005 | \r | |
| 1006 | @retval The TD is stalled or not.\r | |
| 1007 | \r | |
| 1008 | **/\r | |
| 1009 | BOOLEAN\r | |
| 1010 | IsTDStatusStalled (\r | |
| 1011 | IN TD_STRUCT *PtrTDStruct\r | |
| 1012 | );\r | |
| 1013 | \r | |
| 1014 | /**\r | |
| 1015 | Detect whether Data Buffer Error is happened.\r | |
| 1016 | \r | |
| 1017 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 1018 | \r | |
| 1019 | @retval The Data Buffer Error is happened or not.\r | |
| 1020 | \r | |
| 1021 | **/\r | |
| 1022 | BOOLEAN\r | |
| 1023 | IsTDStatusBufferError (\r | |
| 1024 | IN TD_STRUCT *PtrTDStruct\r | |
| 1025 | );\r | |
| 1026 | \r | |
| 1027 | /**\r | |
| 1028 | Detect whether Babble Error is happened.\r | |
| 1029 | \r | |
| 1030 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 1031 | \r | |
| 1032 | @retval The Babble Error is happened or not.\r | |
| 1033 | \r | |
| 1034 | **/\r | |
| 1035 | BOOLEAN\r | |
| 1036 | IsTDStatusBabbleError (\r | |
| 1037 | IN TD_STRUCT *PtrTDStruct\r | |
| 1038 | );\r | |
| 1039 | \r | |
| 1040 | /**\r | |
| 1041 | Detect whether NAK is received.\r | |
| 1042 | \r | |
| 1043 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 1044 | \r | |
| 1045 | @retval The NAK is received or not.\r | |
| 1046 | \r | |
| 1047 | **/\r | |
| 1048 | BOOLEAN\r | |
| 1049 | IsTDStatusNAKReceived (\r | |
| 1050 | IN TD_STRUCT *PtrTDStruct\r | |
| 1051 | );\r | |
| 1052 | \r | |
| 1053 | /**\r | |
| 1054 | Detect whether CRC/Time Out Error is encountered.\r | |
| 1055 | \r | |
| 1056 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 1057 | \r | |
| 1058 | @retval The CRC/Time Out Error is encountered or not.\r | |
| 1059 | \r | |
| 1060 | **/\r | |
| 1061 | BOOLEAN\r | |
| 1062 | IsTDStatusCRCTimeOutError (\r | |
| 1063 | IN TD_STRUCT *PtrTDStruct\r | |
| 1064 | );\r | |
| 1065 | \r | |
| 1066 | /**\r | |
| 1067 | Detect whether Bitstuff Error is received.\r | |
| 1068 | \r | |
| 1069 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 1070 | \r | |
| 1071 | @retval The Bitstuff Error is received or not.\r | |
| 1072 | \r | |
| 1073 | **/\r | |
| 1074 | BOOLEAN\r | |
| 1075 | IsTDStatusBitStuffError (\r | |
| 1076 | IN TD_STRUCT *PtrTDStruct\r | |
| 1077 | );\r | |
| 1078 | \r | |
| 1079 | /**\r | |
| 1080 | Retrieve the actual number of bytes that were tansferred.\r | |
| 1081 | \r | |
| 1082 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 1083 | \r | |
| 1084 | @retval The actual number of bytes that were tansferred.\r | |
| 1085 | \r | |
| 1086 | **/\r | |
| 1087 | UINT16\r | |
| 1088 | GetTDStatusActualLength (\r | |
| 1089 | IN TD_STRUCT *PtrTDStruct\r | |
| 1090 | );\r | |
| 1091 | \r | |
| 1092 | /**\r | |
| 1093 | Retrieve the information of whether the Link Pointer field is valid or not.\r | |
| 1094 | \r | |
| 1095 | @param PtrTDStruct Place to store TD_STRUCT pointer.\r | |
| 1096 | \r | |
| 1097 | @retval The linker pointer field is valid or not.\r | |
| 1098 | \r | |
| 1099 | **/\r | |
| 1100 | BOOLEAN\r | |
| 1101 | GetTDLinkPtrValidorInvalid (\r | |
| 1102 | IN TD_STRUCT *PtrTDStruct\r | |
| 1103 | );\r | |
| 1104 | \r | |
| 1105 | /**\r | |
| 1106 | Count TD Number from PtrFirstTD.\r | |
| 1107 | \r | |
| 1108 | @param PtrFirstTD Place to store TD_STRUCT pointer.\r | |
| 1109 | \r | |
| 1110 | @retval The queued TDs number.\r | |
| 1111 | \r | |
| 1112 | **/\r | |
| 1113 | UINTN\r | |
| 1114 | CountTDsNumber (\r | |
| 1115 | IN TD_STRUCT *PtrFirstTD\r | |
| 1116 | );\r | |
| 1117 | \r | |
| 1118 | /**\r | |
| 1119 | Link TD To QH.\r | |
| 1120 | \r | |
| 1121 | @param PtrQH Place to store QH_STRUCT pointer.\r | |
| 1122 | @param PtrTD Place to store TD_STRUCT pointer.\r | |
| 1123 | \r | |
| 1124 | **/\r | |
| 1125 | VOID\r | |
| 1126 | LinkTDToQH (\r | |
| 1127 | IN QH_STRUCT *PtrQH,\r | |
| 1128 | IN TD_STRUCT *PtrTD\r | |
| 1129 | );\r | |
| 1130 | \r | |
| 1131 | /**\r | |
| 1132 | Link TD To TD.\r | |
| 1133 | \r | |
| 1134 | @param PtrPreTD Place to store TD_STRUCT pointer.\r | |
| 1135 | @param PtrTD Place to store TD_STRUCT pointer.\r | |
| 1136 | \r | |
| 1137 | **/\r | |
| 1138 | VOID\r | |
| 1139 | LinkTDToTD (\r | |
| 1140 | IN TD_STRUCT *PtrPreTD,\r | |
| 1141 | IN TD_STRUCT *PtrTD\r | |
| 1142 | );\r | |
| 1143 | \r | |
| 1144 | /**\r | |
| 1145 | Execute Control Transfer.\r | |
| 1146 | \r | |
| 1147 | @param UhcDev The UCHI device.\r | |
| 1148 | @param PtrTD A pointer to TD_STRUCT data.\r | |
| 1149 | @param ActualLen Actual transfer Length.\r | |
| 1150 | @param TimeOut TimeOut value.\r | |
| 1151 | @param TransferResult Transfer Result.\r | |
| 1152 | \r | |
| 1153 | @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r | |
| 1154 | @return EFI_TIMEOUT The transfer failed due to time out.\r | |
| 1155 | @return EFI_SUCCESS The transfer finished OK.\r | |
| 1156 | \r | |
| 1157 | **/\r | |
| 1158 | EFI_STATUS\r | |
| 1159 | ExecuteControlTransfer (\r | |
| 1160 | IN USB_UHC_DEV *UhcDev,\r | |
| 1161 | IN TD_STRUCT *PtrTD,\r | |
| 1162 | OUT UINTN *ActualLen,\r | |
| 1163 | IN UINTN TimeOut,\r | |
| 1164 | OUT UINT32 *TransferResult\r | |
| 1165 | );\r | |
| 1166 | \r | |
| 1167 | /**\r | |
| 1168 | Execute Bulk Transfer.\r | |
| 1169 | \r | |
| 1170 | @param UhcDev The UCHI device.\r | |
| 1171 | @param PtrTD A pointer to TD_STRUCT data.\r | |
| 1172 | @param ActualLen Actual transfer Length.\r | |
| 1173 | @param DataToggle DataToggle value.\r | |
| 1174 | @param TimeOut TimeOut value.\r | |
| 1175 | @param TransferResult Transfer Result.\r | |
| 1176 | \r | |
| 1177 | @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r | |
| 1178 | @return EFI_TIMEOUT The transfer failed due to time out.\r | |
| 1179 | @return EFI_SUCCESS The transfer finished OK.\r | |
| 1180 | \r | |
| 1181 | **/\r | |
| 1182 | EFI_STATUS\r | |
| 1183 | ExecBulkTransfer (\r | |
| 1184 | IN USB_UHC_DEV *UhcDev,\r | |
| 1185 | IN TD_STRUCT *PtrTD,\r | |
| 1186 | IN OUT UINTN *ActualLen,\r | |
| 1187 | IN UINT8 *DataToggle,\r | |
| 1188 | IN UINTN TimeOut,\r | |
| 1189 | OUT UINT32 *TransferResult\r | |
| 1190 | );\r | |
| 1191 | \r | |
| 1192 | /**\r | |
| 1193 | Delete Queued TDs.\r | |
| 1194 | \r | |
| 1195 | @param UhcDev The UCHI device.\r | |
| 1196 | @param PtrFirstTD Place to store TD_STRUCT pointer.\r | |
| 1197 | \r | |
| 1198 | **/\r | |
| 1199 | VOID\r | |
| 1200 | DeleteQueuedTDs (\r | |
| 1201 | IN USB_UHC_DEV *UhcDev,\r | |
| 1202 | IN TD_STRUCT *PtrFirstTD\r | |
| 1203 | );\r | |
| 1204 | \r | |
| 1205 | /**\r | |
| 1206 | Check TDs Results.\r | |
| 1207 | \r | |
| 1208 | @param PtrTD A pointer to TD_STRUCT data.\r | |
| 1209 | @param Result The result to return.\r | |
| 1210 | @param ErrTDPos The Error TD position.\r | |
| 1211 | @param ActualTransferSize Actual transfer size.\r | |
| 1212 | \r | |
| 1213 | @retval The TD is executed successfully or not.\r | |
| 1214 | \r | |
| 1215 | **/\r | |
| 1216 | BOOLEAN\r | |
| 1217 | CheckTDsResults (\r | |
| 1218 | IN TD_STRUCT *PtrTD,\r | |
| 1219 | OUT UINT32 *Result,\r | |
| 1220 | OUT UINTN *ErrTDPos,\r | |
| 1221 | OUT UINTN *ActualTransferSize\r | |
| 1222 | );\r | |
| 1223 | \r | |
| 1224 | /**\r | |
| 1225 | Create Memory Block.\r | |
| 1226 | \r | |
| 1227 | @param UhcDev The UCHI device.\r | |
| 1228 | @param MemoryHeader The Pointer to allocated memory block.\r | |
| 1229 | @param MemoryBlockSizeInPages The page size of memory block to be allocated.\r | |
| 1230 | \r | |
| 1231 | @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r | |
| 1232 | @retval EFI_SUCCESS Success.\r | |
| 1233 | \r | |
| 1234 | **/\r | |
| 1235 | EFI_STATUS\r | |
| 1236 | CreateMemoryBlock (\r | |
| 1237 | IN USB_UHC_DEV *UhcDev,\r | |
| 1238 | OUT MEMORY_MANAGE_HEADER **MemoryHeader,\r | |
| 1239 | IN UINTN MemoryBlockSizeInPages\r | |
| 1240 | );\r | |
| 1241 | \r | |
| 1242 | /**\r | |
| 1243 | Initialize UHCI memory management.\r | |
| 1244 | \r | |
| 1245 | @param UhcDev The UCHI device.\r | |
| 1246 | \r | |
| 1247 | @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r | |
| 1248 | @retval EFI_SUCCESS Success.\r | |
| 1249 | \r | |
| 1250 | **/\r | |
| 1251 | EFI_STATUS\r | |
| 1252 | InitializeMemoryManagement (\r | |
| 1253 | IN USB_UHC_DEV *UhcDev\r | |
| 1254 | );\r | |
| 1255 | \r | |
| 1256 | /**\r | |
| 1257 | Initialize UHCI memory management.\r | |
| 1258 | \r | |
| 1259 | @param UhcDev The UCHI device.\r | |
| 1260 | @param Pool Buffer pointer to store the buffer pointer.\r | |
| 1261 | @param AllocSize The size of the pool to be allocated.\r | |
| 1262 | \r | |
| 1263 | @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r | |
| 1264 | @retval EFI_SUCCESS Success.\r | |
| 1265 | \r | |
| 1266 | **/\r | |
| 1267 | EFI_STATUS\r | |
| 1268 | UhcAllocatePool (\r | |
| 1269 | IN USB_UHC_DEV *UhcDev,\r | |
| 1270 | OUT UINT8 **Pool,\r | |
| 1271 | IN UINTN AllocSize\r | |
| 1272 | );\r | |
| 1273 | \r | |
| 1274 | /**\r | |
| 1275 | Alloc Memory In MemoryBlock.\r | |
| 1276 | \r | |
| 1277 | @param MemoryHeader The pointer to memory manage header.\r | |
| 1278 | @param Pool Buffer pointer to store the buffer pointer.\r | |
| 1279 | @param NumberOfMemoryUnit The size of the pool to be allocated.\r | |
| 1280 | \r | |
| 1281 | @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r | |
| 1282 | @retval EFI_SUCCESS Success.\r | |
| 1283 | \r | |
| 1284 | **/\r | |
| 1285 | EFI_STATUS\r | |
| 1286 | AllocMemInMemoryBlock (\r | |
| 1287 | IN MEMORY_MANAGE_HEADER *MemoryHeader,\r | |
| 1288 | OUT VOID **Pool,\r | |
| 1289 | IN UINTN NumberOfMemoryUnit\r | |
| 1290 | );\r | |
| 1291 | \r | |
| 1292 | /**\r | |
| 1293 | Uhci Free Pool.\r | |
| 1294 | \r | |
| 1295 | @param UhcDev The UHCI device.\r | |
| 1296 | @param Pool A pointer to store the buffer address.\r | |
| 1297 | @param AllocSize The size of the pool to be freed.\r | |
| 1298 | \r | |
| 1299 | **/\r | |
| 1300 | VOID\r | |
| 1301 | UhcFreePool (\r | |
| 1302 | IN USB_UHC_DEV *UhcDev,\r | |
| 1303 | IN UINT8 *Pool,\r | |
| 1304 | IN UINTN AllocSize\r | |
| 1305 | );\r | |
| 1306 | \r | |
| 1307 | /**\r | |
| 1308 | Insert a new memory header into list.\r | |
| 1309 | \r | |
| 1310 | @param MemoryHeader A pointer to the memory header list.\r | |
| 1311 | @param NewMemoryHeader A new memory header to be inserted into the list.\r | |
| 1312 | \r | |
| 1313 | **/\r | |
| 1314 | VOID\r | |
| 1315 | InsertMemoryHeaderToList (\r | |
| 1316 | IN MEMORY_MANAGE_HEADER *MemoryHeader,\r | |
| 1317 | IN MEMORY_MANAGE_HEADER *NewMemoryHeader\r | |
| 1318 | );\r | |
| 1319 | \r | |
| 1320 | /**\r | |
| 1321 | Judge the memory block in the memory header is empty or not.\r | |
| 1322 | \r | |
| 1323 | @param MemoryHeaderPtr A pointer to the memory header list.\r | |
| 1324 | \r | |
| 1325 | @retval Whether the memory block in the memory header is empty or not.\r | |
| 1326 | \r | |
| 1327 | **/\r | |
| 1328 | BOOLEAN\r | |
| 1329 | IsMemoryBlockEmptied (\r | |
| 1330 | IN MEMORY_MANAGE_HEADER *MemoryHeaderPtr\r | |
| 1331 | );\r | |
| 1332 | \r | |
| 1333 | /**\r | |
| 1334 | remove a memory header from list.\r | |
| 1335 | \r | |
| 1336 | @param FirstMemoryHeader A pointer to the memory header list.\r | |
| 1337 | @param FreeMemoryHeader A memory header to be removed into the list.\r | |
| 1338 | \r | |
| 1339 | **/\r | |
| 1340 | VOID\r | |
| 1341 | DelinkMemoryBlock (\r | |
| 1342 | IN MEMORY_MANAGE_HEADER *FirstMemoryHeader,\r | |
| 1343 | IN MEMORY_MANAGE_HEADER *FreeMemoryHeader\r | |
| 1344 | );\r | |
| 1345 | \r | |
| 8284b179 SZ |
1346 | /**\r |
| 1347 | Map address of request structure buffer.\r | |
| 1348 | \r | |
| 1349 | @param Uhc The UHCI device.\r | |
| 1350 | @param Request The user request buffer.\r | |
| 1351 | @param MappedAddr Mapped address of request.\r | |
| 1352 | @param Map Identificaion of this mapping to return.\r | |
| 1353 | \r | |
| 1354 | @return EFI_SUCCESS Success.\r | |
| 1355 | @return EFI_DEVICE_ERROR Fail to map the user request.\r | |
| 1356 | \r | |
| 1357 | **/\r | |
| 1358 | EFI_STATUS\r | |
| 1359 | UhciMapUserRequest (\r | |
| 1360 | IN USB_UHC_DEV *Uhc,\r | |
| 1361 | IN OUT VOID *Request,\r | |
| 1362 | OUT UINT8 **MappedAddr,\r | |
| 1363 | OUT VOID **Map\r | |
| 1364 | );\r | |
| 1365 | \r | |
| 1366 | /**\r | |
| 1367 | Map address of user data buffer.\r | |
| 1368 | \r | |
| 1369 | @param Uhc The UHCI device.\r | |
| 1370 | @param Direction Direction of the data transfer.\r | |
| 1371 | @param Data The user data buffer.\r | |
| 1372 | @param Len Length of the user data.\r | |
| 1373 | @param PktId Packet identificaion.\r | |
| 1374 | @param MappedAddr Mapped address to return.\r | |
| 1375 | @param Map Identificaion of this mapping to return.\r | |
| 1376 | \r | |
| 1377 | @return EFI_SUCCESS Success.\r | |
| 1378 | @return EFI_DEVICE_ERROR Fail to map the user data.\r | |
| 1379 | \r | |
| 1380 | **/\r | |
| 1381 | EFI_STATUS\r | |
| 1382 | UhciMapUserData (\r | |
| 1383 | IN USB_UHC_DEV *Uhc,\r | |
| 1384 | IN EFI_USB_DATA_DIRECTION Direction,\r | |
| 1385 | IN VOID *Data,\r | |
| 1386 | IN OUT UINTN *Len,\r | |
| 1387 | OUT UINT8 *PktId,\r | |
| 1388 | OUT UINT8 **MappedAddr,\r | |
| 1389 | OUT VOID **Map\r | |
| 1390 | );\r | |
| 1391 | \r | |
| 1392 | /**\r | |
| 1393 | Provides the controller-specific addresses required to access system memory from a\r | |
| 1394 | DMA bus master.\r | |
| 1395 | \r | |
| 1396 | @param IoMmu Pointer to IOMMU PPI.\r | |
| 1397 | @param Operation Indicates if the bus master is going to read or write to system memory.\r | |
| 1398 | @param HostAddress The system memory address to map to the PCI controller.\r | |
| 1399 | @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r | |
| 1400 | that were mapped.\r | |
| 1401 | @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r | |
| 1402 | access the hosts HostAddress.\r | |
| 1403 | @param Mapping A resulting value to pass to Unmap().\r | |
| 1404 | \r | |
| 1405 | @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r | |
| 1406 | @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r | |
| 1407 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
| 1408 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
| 1409 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r | |
| 1410 | \r | |
| 1411 | **/\r | |
| 1412 | EFI_STATUS\r | |
| 1413 | IoMmuMap (\r | |
| 1414 | IN EDKII_IOMMU_PPI *IoMmu,\r | |
| 1415 | IN EDKII_IOMMU_OPERATION Operation,\r | |
| 1416 | IN VOID *HostAddress,\r | |
| 1417 | IN OUT UINTN *NumberOfBytes,\r | |
| 1418 | OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r | |
| 1419 | OUT VOID **Mapping\r | |
| 1420 | );\r | |
| 1421 | \r | |
| 1422 | /**\r | |
| 1423 | Completes the Map() operation and releases any corresponding resources.\r | |
| 1424 | \r | |
| 1425 | @param IoMmu Pointer to IOMMU PPI.\r | |
| 1426 | @param Mapping The mapping value returned from Map().\r | |
| 1427 | \r | |
| 1428 | **/\r | |
| 1429 | VOID\r | |
| 1430 | IoMmuUnmap (\r | |
| 1431 | IN EDKII_IOMMU_PPI *IoMmu,\r | |
| 1432 | IN VOID *Mapping\r | |
| 1433 | );\r | |
| 1434 | \r | |
| 1435 | /**\r | |
| 1436 | Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r | |
| 1437 | OperationBusMasterCommonBuffer64 mapping.\r | |
| 1438 | \r | |
| 1439 | @param IoMmu Pointer to IOMMU PPI.\r | |
| 1440 | @param Pages The number of pages to allocate.\r | |
| 1441 | @param HostAddress A pointer to store the base system memory address of the\r | |
| 1442 | allocated range.\r | |
| 1443 | @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r | |
| 1444 | access the hosts HostAddress.\r | |
| 1445 | @param Mapping A resulting value to pass to Unmap().\r | |
| 1446 | \r | |
| 1447 | @retval EFI_SUCCESS The requested memory pages were allocated.\r | |
| 1448 | @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r | |
| 1449 | MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r | |
| 1450 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
| 1451 | @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r | |
| 1452 | \r | |
| 1453 | **/\r | |
| 1454 | EFI_STATUS\r | |
| 1455 | IoMmuAllocateBuffer (\r | |
| 1456 | IN EDKII_IOMMU_PPI *IoMmu,\r | |
| 1457 | IN UINTN Pages,\r | |
| 1458 | OUT VOID **HostAddress,\r | |
| 1459 | OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r | |
| 1460 | OUT VOID **Mapping\r | |
| 1461 | );\r | |
| 1462 | \r | |
| 1463 | /**\r | |
| 1464 | Frees memory that was allocated with AllocateBuffer().\r | |
| 1465 | \r | |
| 1466 | @param IoMmu Pointer to IOMMU PPI.\r | |
| 1467 | @param Pages The number of pages to free.\r | |
| 1468 | @param HostAddress The base system memory address of the allocated range.\r | |
| 1469 | @param Mapping The mapping value returned from Map().\r | |
| 1470 | \r | |
| 1471 | **/\r | |
| 1472 | VOID\r | |
| 1473 | IoMmuFreeBuffer (\r | |
| 1474 | IN EDKII_IOMMU_PPI *IoMmu,\r | |
| 1475 | IN UINTN Pages,\r | |
| 1476 | IN VOID *HostAddress,\r | |
| 1477 | IN VOID *Mapping\r | |
| 1478 | );\r | |
| 1479 | \r | |
| 1480 | /**\r | |
| 1481 | Initialize IOMMU.\r | |
| 1482 | \r | |
| 1483 | @param IoMmu Pointer to pointer to IOMMU PPI.\r | |
| 1484 | \r | |
| 1485 | **/\r | |
| 1486 | VOID\r | |
| 1487 | IoMmuInit (\r | |
| 1488 | OUT EDKII_IOMMU_PPI **IoMmu\r | |
| 1489 | );\r | |
| 1490 | \r | |
| 4b1bf81c | 1491 | #endif\r |