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1 | /*++\r |
2 | \r |
41057d77 |
3 | Copyright (c) 2006 - 2007, Intel Corporation\r |
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4 | All rights reserved. This program and the accompanying materials\r |
5 | are licensed and made available under the terms and conditions of the BSD License\r |
6 | which accompanies this distribution. The full text of the license may be found at\r |
7 | http://opensource.org/licenses/bsd-license.php\r |
8 | \r |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
40834173 |
11 | \r |
12 | Module Name:\r |
13 | \r |
14 | E100B.H\r |
15 | \r |
16 | Abstract:\r |
17 | \r |
18 | \r |
19 | Revision History\r |
20 | \r |
21 | --*/\r |
22 | // pci config offsets:\r |
23 | \r |
24 | #define RX_BUFFER_COUNT 32\r |
25 | #define TX_BUFFER_COUNT 32\r |
26 | \r |
27 | #define PCI_VENDOR_ID_INTEL 0x8086\r |
28 | #define PCI_DEVICE_ID_INTEL_82557 0x1229\r |
29 | #define D100_VENDOR_ID 0x8086\r |
30 | #define D100_DEVICE_ID 0x1229\r |
31 | #define D102_DEVICE_ID 0x2449\r |
32 | \r |
33 | #define ICH3_DEVICE_ID_1 0x1031\r |
34 | #define ICH3_DEVICE_ID_2 0x1032\r |
35 | #define ICH3_DEVICE_ID_3 0x1033\r |
36 | #define ICH3_DEVICE_ID_4 0x1034\r |
37 | #define ICH3_DEVICE_ID_5 0x1035\r |
38 | #define ICH3_DEVICE_ID_6 0x1036\r |
39 | #define ICH3_DEVICE_ID_7 0x1037\r |
40 | #define ICH3_DEVICE_ID_8 0x1038\r |
41 | \r |
42 | #define SPEEDO_DEVICE_ID 0x1227\r |
43 | #define SPLASH1_DEVICE_ID 0x1226\r |
44 | \r |
45 | \r |
46 | // bit fields for the command\r |
47 | #define PCI_COMMAND_MASTER 0x04 // bit 2\r |
48 | #define PCI_COMMAND_IO 0x01 // bit 0\r |
49 | #define PCI_COMMAND 0x04\r |
50 | #define PCI_LATENCY_TIMER 0x0D\r |
51 | \r |
52 | #define ETHER_MAC_ADDR_LEN 6\r |
53 | #ifdef AVL_XXX\r |
54 | #define ETHER_HEADER_LEN 14\r |
55 | // media interface type\r |
56 | // #define INTERFACE_TYPE "\r |
57 | \r |
58 | // Hardware type values\r |
59 | #define HW_ETHER_TYPE 1\r |
60 | #define HW_EXPERIMENTAL_ETHER_TYPE 2\r |
61 | #define HW_IEEE_TYPE 6\r |
62 | #define HW_ARCNET_TYPE 7\r |
63 | \r |
64 | #endif // AVL_XXX\r |
65 | \r |
66 | #define MAX_ETHERNET_PKT_SIZE 1514 // including eth header\r |
67 | #define RX_BUFFER_SIZE 1536 // including crc and padding\r |
68 | #define TX_BUFFER_SIZE 64\r |
69 | #define ETH_MTU 1500 // does not include ethernet header length\r |
70 | \r |
71 | #define SPEEDO3_TOTAL_SIZE 0x20\r |
72 | \r |
73 | #pragma pack(1)\r |
74 | \r |
75 | typedef struct eth {\r |
76 | UINT8 dest_addr[PXE_HWADDR_LEN_ETHER];\r |
77 | UINT8 src_addr[PXE_HWADDR_LEN_ETHER];\r |
78 | UINT16 type;\r |
79 | } EtherHeader;\r |
80 | \r |
81 | #pragma pack(1)\r |
82 | typedef struct CONFIG_HEADER {\r |
83 | UINT16 VendorID;\r |
84 | UINT16 DeviceID;\r |
85 | UINT16 Command;\r |
86 | UINT16 Status;\r |
87 | UINT16 RevID;\r |
88 | UINT16 ClassID;\r |
89 | UINT8 CacheLineSize;\r |
90 | UINT8 LatencyTimer;\r |
91 | UINT8 HeaderType; // must be zero to impose this structure...\r |
92 | UINT8 BIST; // built-in self test\r |
93 | UINT32 BaseAddressReg_0; // memory mapped address\r |
94 | UINT32 BaseAddressReg_1; //io mapped address, Base IO address\r |
95 | UINT32 BaseAddressReg_2; // option rom address\r |
96 | UINT32 BaseAddressReg_3;\r |
97 | UINT32 BaseAddressReg_4;\r |
98 | UINT32 BaseAddressReg_5;\r |
99 | UINT32 CardBusCISPtr;\r |
100 | UINT16 SubVendorID;\r |
101 | UINT16 SubSystemID;\r |
102 | UINT32 ExpansionROMBaseAddr;\r |
103 | UINT8 CapabilitiesPtr;\r |
104 | UINT8 reserved1;\r |
105 | UINT16 Reserved2;\r |
106 | UINT32 Reserved3;\r |
107 | UINT8 int_line;\r |
108 | UINT8 int_pin;\r |
109 | UINT8 Min_gnt;\r |
110 | UINT8 Max_lat;\r |
111 | } PCI_CONFIG_HEADER;\r |
112 | #pragma pack()\r |
113 | \r |
114 | //-------------------------------------------------------------------------\r |
115 | // Offsets to the various registers.\r |
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116 | // All accesses need not be longword aligned.\r |
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117 | //-------------------------------------------------------------------------\r |
118 | enum speedo_offsets {\r |
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119 | SCBStatus = 0, SCBCmd = 2, // Rx/Command Unit command and status.\r |
120 | SCBPointer = 4, // General purpose pointer.\r |
121 | SCBPort = 8, // Misc. commands and operands.\r |
122 | SCBflash = 12, SCBeeprom = 14, // EEPROM and flash memory control.\r |
123 | SCBCtrlMDI = 16, // MDI interface control.\r |
124 | SCBEarlyRx = 20, // Early receive byte count.\r |
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125 | SCBEarlyRxInt = 24, SCBFlowCtrlReg = 25, SCBPmdr = 27,\r |
126 | // offsets for general control registers (GCRs)\r |
127 | SCBGenCtrl = 28, SCBGenStatus = 29, SCBGenCtrl2 = 30, SCBRsvd = 31\r |
128 | };\r |
129 | \r |
130 | #define GCR2_EEPROM_ACCESS_SEMAPHORE 0x80 // bit offset into the gcr2\r |
131 | \r |
132 | //-------------------------------------------------------------------------\r |
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133 | // Action commands - Commands that can be put in a command list entry.\r |
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134 | //-------------------------------------------------------------------------\r |
135 | enum commands {\r |
136 | CmdNOp = 0, CmdIASetup = 1, CmdConfigure = 2, CmdMulticastList = 3,\r |
137 | CmdTx = 4, CmdTDR = 5, CmdDump = 6, CmdDiagnose = 7,\r |
138 | CmdSuspend = 0x4000, /* Suspend after completion. */\r |
139 | CmdIntr = 0x2000, /* Interrupt after completion. */\r |
140 | CmdTxFlex = 0x0008 /* Use "Flexible mode" for CmdTx command. */\r |
141 | };\r |
142 | \r |
143 | //-------------------------------------------------------------------------\r |
144 | // port commands\r |
145 | //-------------------------------------------------------------------------\r |
146 | #define PORT_RESET 0\r |
147 | #define PORT_SELF_TEST 1\r |
148 | #define POR_SELECTIVE_RESET 2\r |
149 | #define PORT_DUMP_POINTER 2\r |
150 | \r |
151 | //-------------------------------------------------------------------------\r |
152 | // SCB Command Word bit definitions\r |
153 | //-------------------------------------------------------------------------\r |
154 | //- CUC fields\r |
155 | #define CU_START 0x0010\r |
156 | #define CU_RESUME 0x0020\r |
157 | #define CU_STATSADDR 0x0040\r |
158 | #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */\r |
159 | #define CU_CMD_BASE 0x0060 /* Base address to add to add CU commands. */\r |
160 | #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */\r |
161 | \r |
162 | //- RUC fields\r |
163 | #define RX_START 0x0001\r |
164 | #define RX_RESUME 0x0002\r |
165 | #define RX_ABORT 0x0004\r |
166 | #define RX_ADDR_LOAD 0x0006 /* load ru_base_reg */\r |
167 | #define RX_RESUMENR 0x0007\r |
168 | \r |
169 | // Interrupt fields (assuming byte addressing)\r |
170 | #define INT_MASK 0x0100\r |
171 | #define DRVR_INT 0x0200 /* Driver generated interrupt. */\r |
172 | \r |
173 | //- CB Status Word\r |
174 | #define CMD_STATUS_COMPLETE 0x8000\r |
175 | #define RX_STATUS_COMPLETE 0x8000\r |
176 | #define CMD_STATUS_MASK 0xF000\r |
177 | \r |
178 | //-------------------------------------------------------------------------\r |
179 | //- SCB Status bits:\r |
180 | // Interrupts are ACKed by writing to the upper 6 interrupt bits\r |
181 | //-------------------------------------------------------------------------\r |
182 | #define SCB_STATUS_MASK 0xFC00 // bits 2-7 - STATUS/ACK Mask\r |
183 | #define SCB_STATUS_CX_TNO 0x8000 // BIT_15 - CX or TNO Interrupt\r |
184 | #define SCB_STATUS_FR 0x4000 // BIT_14 - FR Interrupt\r |
185 | #define SCB_STATUS_CNA 0x2000 // BIT_13 - CNA Interrupt\r |
186 | #define SCB_STATUS_RNR 0x1000 // BIT_12 - RNR Interrupt\r |
187 | #define SCB_STATUS_MDI 0x0800 // BIT_11 - MDI R/W Done Interrupt\r |
188 | #define SCB_STATUS_SWI 0x0400 // BIT_10 - SWI Interrupt\r |
189 | \r |
190 | // CU STATUS: bits 6 & 7\r |
191 | #define SCB_STATUS_CU_MASK 0x00C0 // bits 6 & 7\r |
192 | #define SCB_STATUS_CU_IDLE 0x0000 // 00\r |
193 | #define SCB_STATUS_CU_SUSPEND 0x0040 // 01\r |
194 | #define SCB_STATUS_CU_ACTIVE 0x0080 // 10\r |
195 | \r |
196 | // RU STATUS: bits 2-5\r |
197 | #define SCB_RUS_IDLE 0x0000\r |
198 | #define SCB_RUS_SUSPENDED 0x0004 // bit 2\r |
199 | #define SCB_RUS_NO_RESOURCES 0x0008 // bit 3\r |
200 | #define SCB_RUS_READY 0x0010 // bit 4\r |
201 | \r |
202 | //-------------------------------------------------------------------------\r |
203 | // Bit Mask definitions\r |
204 | //-------------------------------------------------------------------------\r |
205 | #define BIT_0 0x0001\r |
206 | #define BIT_1 0x0002\r |
207 | #define BIT_2 0x0004\r |
208 | #define BIT_3 0x0008\r |
209 | #define BIT_4 0x0010\r |
210 | #define BIT_5 0x0020\r |
211 | #define BIT_6 0x0040\r |
212 | #define BIT_7 0x0080\r |
213 | #define BIT_8 0x0100\r |
214 | #define BIT_9 0x0200\r |
215 | #define BIT_10 0x0400\r |
216 | #define BIT_11 0x0800\r |
217 | #define BIT_12 0x1000\r |
218 | #define BIT_13 0x2000\r |
219 | #define BIT_14 0x4000\r |
220 | #define BIT_15 0x8000\r |
221 | #define BIT_24 0x01000000\r |
222 | #define BIT_28 0x10000000\r |
223 | \r |
224 | \r |
225 | //-------------------------------------------------------------------------\r |
226 | // MDI Control register bit definitions\r |
227 | //-------------------------------------------------------------------------\r |
228 | #define MDI_DATA_MASK BIT_0_15 // MDI Data port\r |
229 | #define MDI_REG_ADDR BIT_16_20 // which MDI register to read/write\r |
230 | #define MDI_PHY_ADDR BIT_21_25 // which PHY to read/write\r |
231 | #define MDI_PHY_OPCODE BIT_26_27 // which PHY to read/write\r |
232 | #define MDI_PHY_READY BIT_28 // PHY is ready for another MDI cycle\r |
233 | #define MDI_PHY_INT_ENABLE BIT_29 // Assert INT at MDI cycle completion\r |
234 | \r |
235 | #define BIT_0_2 0x0007\r |
236 | #define BIT_0_3 0x000F\r |
237 | #define BIT_0_4 0x001F\r |
238 | #define BIT_0_5 0x003F\r |
239 | #define BIT_0_6 0x007F\r |
240 | #define BIT_0_7 0x00FF\r |
241 | #define BIT_0_8 0x01FF\r |
242 | #define BIT_0_13 0x3FFF\r |
243 | #define BIT_0_15 0xFFFF\r |
244 | #define BIT_1_2 0x0006\r |
245 | #define BIT_1_3 0x000E\r |
246 | #define BIT_2_5 0x003C\r |
247 | #define BIT_3_4 0x0018\r |
248 | #define BIT_4_5 0x0030\r |
249 | #define BIT_4_6 0x0070\r |
250 | #define BIT_4_7 0x00F0\r |
251 | #define BIT_5_7 0x00E0\r |
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252 | #define BIT_5_9 0x03E0\r |
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253 | #define BIT_5_12 0x1FE0\r |
254 | #define BIT_5_15 0xFFE0\r |
255 | #define BIT_6_7 0x00c0\r |
256 | #define BIT_7_11 0x0F80\r |
257 | #define BIT_8_10 0x0700\r |
258 | #define BIT_9_13 0x3E00\r |
259 | #define BIT_12_15 0xF000\r |
260 | \r |
261 | #define BIT_16_20 0x001F0000\r |
262 | #define BIT_21_25 0x03E00000\r |
263 | #define BIT_26_27 0x0C000000\r |
264 | \r |
265 | //-------------------------------------------------------------------------\r |
266 | // MDI Control register opcode definitions\r |
267 | //-------------------------------------------------------------------------\r |
268 | #define MDI_WRITE 1 // Phy Write\r |
269 | #define MDI_READ 2 // Phy read\r |
270 | \r |
271 | //-------------------------------------------------------------------------\r |
272 | // PHY 100 MDI Register/Bit Definitions\r |
273 | //-------------------------------------------------------------------------\r |
274 | // MDI register set\r |
275 | #define MDI_CONTROL_REG 0x00 // MDI control register\r |
276 | #define MDI_STATUS_REG 0x01 // MDI Status regiser\r |
277 | #define PHY_ID_REG_1 0x02 // Phy indentification reg (word 1)\r |
278 | #define PHY_ID_REG_2 0x03 // Phy indentification reg (word 2)\r |
279 | #define AUTO_NEG_ADVERTISE_REG 0x04 // Auto-negotiation advertisement\r |
280 | #define AUTO_NEG_LINK_PARTNER_REG 0x05 // Auto-negotiation link partner ability\r |
281 | #define AUTO_NEG_EXPANSION_REG 0x06 // Auto-negotiation expansion\r |
282 | #define AUTO_NEG_NEXT_PAGE_REG 0x07 // Auto-negotiation next page transmit\r |
283 | #define EXTENDED_REG_0 0x10 // Extended reg 0 (Phy 100 modes)\r |
284 | #define EXTENDED_REG_1 0x14 // Extended reg 1 (Phy 100 error indications)\r |
285 | #define NSC_CONG_CONTROL_REG 0x17 // National (TX) congestion control\r |
286 | #define NSC_SPEED_IND_REG 0x19 // National (TX) speed indication\r |
287 | \r |
288 | // MDI Control register bit definitions\r |
289 | #define MDI_CR_COLL_TEST_ENABLE BIT_7 // Collision test enable\r |
290 | #define MDI_CR_FULL_HALF BIT_8 // FDX =1, half duplex =0\r |
291 | #define MDI_CR_RESTART_AUTO_NEG BIT_9 // Restart auto negotiation\r |
292 | #define MDI_CR_ISOLATE BIT_10 // Isolate PHY from MII\r |
293 | #define MDI_CR_POWER_DOWN BIT_11 // Power down\r |
294 | #define MDI_CR_AUTO_SELECT BIT_12 // Auto speed select enable\r |
295 | #define MDI_CR_10_100 BIT_13 // 0 = 10Mbs, 1 = 100Mbs\r |
296 | #define MDI_CR_LOOPBACK BIT_14 // 0 = normal, 1 = loopback\r |
297 | #define MDI_CR_RESET BIT_15 // 0 = normal, 1 = PHY reset\r |
298 | \r |
299 | // MDI Status register bit definitions\r |
300 | #define MDI_SR_EXT_REG_CAPABLE BIT_0 // Extended register capabilities\r |
301 | #define MDI_SR_JABBER_DETECT BIT_1 // Jabber detected\r |
302 | #define MDI_SR_LINK_STATUS BIT_2 // Link Status -- 1 = link\r |
303 | #define MDI_SR_AUTO_SELECT_CAPABLE BIT_3 // Auto speed select capable\r |
304 | #define MDI_SR_REMOTE_FAULT_DETECT BIT_4 // Remote fault detect\r |
305 | #define MDI_SR_AUTO_NEG_COMPLETE BIT_5 // Auto negotiation complete\r |
306 | #define MDI_SR_10T_HALF_DPX BIT_11 // 10BaseT Half Duplex capable\r |
307 | #define MDI_SR_10T_FULL_DPX BIT_12 // 10BaseT full duplex capable\r |
308 | #define MDI_SR_TX_HALF_DPX BIT_13 // TX Half Duplex capable\r |
309 | #define MDI_SR_TX_FULL_DPX BIT_14 // TX full duplex capable\r |
310 | #define MDI_SR_T4_CAPABLE BIT_15 // T4 capable\r |
311 | \r |
312 | // Auto-Negotiation advertisement register bit definitions\r |
313 | #define NWAY_AD_SELCTOR_FIELD BIT_0_4 // identifies supported protocol\r |
314 | #define NWAY_AD_ABILITY BIT_5_12 // technologies that are supported\r |
315 | #define NWAY_AD_10T_HALF_DPX BIT_5 // 10BaseT Half Duplex capable\r |
316 | #define NWAY_AD_10T_FULL_DPX BIT_6 // 10BaseT full duplex capable\r |
317 | #define NWAY_AD_TX_HALF_DPX BIT_7 // TX Half Duplex capable\r |
318 | #define NWAY_AD_TX_FULL_DPX BIT_8 // TX full duplex capable\r |
319 | #define NWAY_AD_T4_CAPABLE BIT_9 // T4 capable\r |
320 | #define NWAY_AD_REMOTE_FAULT BIT_13 // indicates local remote fault\r |
321 | #define NWAY_AD_RESERVED BIT_14 // reserved\r |
322 | #define NWAY_AD_NEXT_PAGE BIT_15 // Next page (not supported)\r |
323 | \r |
324 | // Auto-Negotiation link partner ability register bit definitions\r |
325 | #define NWAY_LP_SELCTOR_FIELD BIT_0_4 // identifies supported protocol\r |
326 | #define NWAY_LP_ABILITY BIT_5_9 // technologies that are supported\r |
327 | #define NWAY_LP_REMOTE_FAULT BIT_13 // indicates partner remote fault\r |
328 | #define NWAY_LP_ACKNOWLEDGE BIT_14 // acknowledge\r |
329 | #define NWAY_LP_NEXT_PAGE BIT_15 // Next page (not supported)\r |
330 | \r |
331 | // Auto-Negotiation expansion register bit definitions\r |
332 | #define NWAY_EX_LP_NWAY BIT_0 // link partner is NWAY\r |
333 | #define NWAY_EX_PAGE_RECEIVED BIT_1 // link code word received\r |
334 | #define NWAY_EX_NEXT_PAGE_ABLE BIT_2 // local is next page able\r |
335 | #define NWAY_EX_LP_NEXT_PAGE_ABLE BIT_3 // partner is next page able\r |
336 | #define NWAY_EX_PARALLEL_DET_FLT BIT_4 // parallel detection fault\r |
337 | #define NWAY_EX_RESERVED BIT_5_15 // reserved\r |
338 | \r |
339 | \r |
340 | // PHY 100 Extended Register 0 bit definitions\r |
341 | #define PHY_100_ER0_FDX_INDIC BIT_0 // 1 = FDX, 0 = half duplex\r |
342 | #define PHY_100_ER0_SPEED_INDIC BIT_1 // 1 = 100mbs, 0= 10mbs\r |
343 | #define PHY_100_ER0_WAKE_UP BIT_2 // Wake up DAC\r |
344 | #define PHY_100_ER0_RESERVED BIT_3_4 // Reserved\r |
345 | #define PHY_100_ER0_REV_CNTRL BIT_5_7 // Revsion control (A step = 000)\r |
346 | #define PHY_100_ER0_FORCE_FAIL BIT_8 // Force Fail is enabled\r |
347 | #define PHY_100_ER0_TEST BIT_9_13 // Revsion control (A step = 000)\r |
348 | #define PHY_100_ER0_LINKDIS BIT_14 // Link integrity test is disabled\r |
349 | #define PHY_100_ER0_JABDIS BIT_15 // Jabber function is disabled\r |
350 | \r |
351 | \r |
352 | // PHY 100 Extended Register 1 bit definitions\r |
353 | #define PHY_100_ER1_RESERVED BIT_0_8 // Reserved\r |
354 | #define PHY_100_ER1_CH2_DET_ERR BIT_9 // Channel 2 EOF detection error\r |
355 | #define PHY_100_ER1_MANCH_CODE_ERR BIT_10 // Manchester code error\r |
356 | #define PHY_100_ER1_EOP_ERR BIT_11 // EOP error\r |
357 | #define PHY_100_ER1_BAD_CODE_ERR BIT_12 // bad code error\r |
358 | #define PHY_100_ER1_INV_CODE_ERR BIT_13 // invalid code error\r |
359 | #define PHY_100_ER1_DC_BAL_ERR BIT_14 // DC balance error\r |
360 | #define PHY_100_ER1_PAIR_SKEW_ERR BIT_15 // Pair skew error\r |
361 | \r |
362 | // National Semiconductor TX phy congestion control register bit definitions\r |
363 | #define NSC_TX_CONG_TXREADY BIT_10 // Makes TxReady an input\r |
364 | #define NSC_TX_CONG_ENABLE BIT_8 // Enables congestion control\r |
365 | #define NSC_TX_CONG_F_CONNECT BIT_5 // Enables congestion control\r |
366 | \r |
367 | // National Semiconductor TX phy speed indication register bit definitions\r |
368 | #define NSC_TX_SPD_INDC_SPEED BIT_6 // 0 = 100mb, 1=10mb\r |
369 | \r |
370 | //-------------------------------------------------------------------------\r |
371 | // Phy related constants\r |
372 | //-------------------------------------------------------------------------\r |
373 | #define PHY_503 0\r |
374 | #define PHY_100_A 0x000003E0\r |
375 | #define PHY_100_C 0x035002A8\r |
376 | #define PHY_TX_ID 0x015002A8\r |
377 | #define PHY_NSC_TX 0x5c002000\r |
378 | #define PHY_OTHER 0xFFFF\r |
379 | \r |
380 | #define PHY_MODEL_REV_ID_MASK 0xFFF0FFFF\r |
381 | #define PARALLEL_DETECT 0\r |
382 | #define N_WAY 1\r |
383 | \r |
384 | #define RENEGOTIATE_TIME 35 // (3.5 Seconds)\r |
385 | \r |
386 | #define CONNECTOR_AUTO 0\r |
387 | #define CONNECTOR_TPE 1\r |
388 | #define CONNECTOR_MII 2\r |
389 | \r |
390 | //-------------------------------------------------------------------------\r |
391 | \r |
392 | /* The Speedo3 Rx and Tx frame/buffer descriptors. */\r |
393 | #pragma pack(1)\r |
394 | struct CB_Header { /* A generic descriptor. */\r |
395 | UINT16 status; /* Offset 0. */\r |
396 | UINT16 command; /* Offset 2. */\r |
397 | UINT32 link; /* struct descriptor * */\r |
398 | };\r |
399 | \r |
400 | /* transmit command block structure */\r |
401 | #pragma pack(1)\r |
402 | typedef struct s_TxCB {\r |
403 | struct CB_Header cb_header;\r |
404 | UINT32 PhysTBDArrayAddres; /* address of an array that contains\r |
405 | physical TBD pointers */\r |
406 | UINT16 ByteCount; /* immediate data count = 0 always */\r |
407 | UINT8 Threshold;\r |
408 | UINT8 TBDCount;\r |
409 | UINT8 ImmediateData[TX_BUFFER_SIZE];\r |
410 | /* following fields are not seen by the 82557 */\r |
411 | struct TBD {\r |
412 | UINT32 phys_buf_addr;\r |
413 | UINT32 buf_len;\r |
414 | } TBDArray[MAX_XMIT_FRAGMENTS];\r |
415 | UINT32 PhysArrayAddr; /* in case the one in the header is lost */\r |
416 | UINT32 PhysTCBAddress; /* for this TCB */\r |
417 | struct s_TxCB *NextTCBVirtualLinkPtr;\r |
418 | struct s_TxCB *PrevTCBVirtualLinkPtr;\r |
419 | UINT64 free_data_ptr; // to be given to the upper layer when this xmit completes1\r |
420 | }TxCB;\r |
421 | \r |
422 | /* The Speedo3 Rx and Tx buffer descriptors. */\r |
423 | #pragma pack(1)\r |
424 | typedef struct s_RxFD { /* Receive frame descriptor. */\r |
425 | struct CB_Header cb_header;\r |
426 | UINT32 rx_buf_addr; /* VOID * */\r |
427 | UINT16 ActualCount;\r |
428 | UINT16 RFDSize;\r |
429 | UINT8 RFDBuffer[RX_BUFFER_SIZE];\r |
430 | UINT8 forwarded;\r |
431 | UINT8 junk[3];\r |
432 | }RxFD;\r |
433 | \r |
434 | /* Elements of the RxFD.status word. */\r |
435 | #define RX_COMPLETE 0x8000\r |
436 | #define RX_FRAME_OK 0x2000\r |
437 | \r |
438 | /* Elements of the dump_statistics block. This block must be lword aligned. */\r |
439 | #pragma pack(1)\r |
440 | struct speedo_stats {\r |
441 | UINT32 tx_good_frames;\r |
442 | UINT32 tx_coll16_errs;\r |
443 | UINT32 tx_late_colls;\r |
444 | UINT32 tx_underruns;\r |
445 | UINT32 tx_lost_carrier;\r |
446 | UINT32 tx_deferred;\r |
447 | UINT32 tx_one_colls;\r |
448 | UINT32 tx_multi_colls;\r |
449 | UINT32 tx_total_colls;\r |
450 | UINT32 rx_good_frames;\r |
451 | UINT32 rx_crc_errs;\r |
452 | UINT32 rx_align_errs;\r |
453 | UINT32 rx_resource_errs;\r |
454 | UINT32 rx_overrun_errs;\r |
455 | UINT32 rx_colls_errs;\r |
456 | UINT32 rx_runt_errs;\r |
457 | UINT32 done_marker;\r |
458 | };\r |
459 | #pragma pack()\r |
460 | \r |
461 | \r |
462 | struct Krn_Mem{\r |
463 | RxFD rx_ring[RX_BUFFER_COUNT];\r |
464 | TxCB tx_ring[TX_BUFFER_COUNT];\r |
465 | struct speedo_stats statistics;\r |
466 | };\r |
467 | #define MEMORY_NEEDED sizeof(struct Krn_Mem)\r |
468 | \r |
469 | /* The parameters for a CmdConfigure operation.\r |
470 | There are so many options that it would be difficult to document each bit.\r |
471 | We mostly use the default or recommended settings.\r |
472 | */\r |
473 | \r |
474 | /*\r |
475 | *--------------------------------------------------------------------------\r |
476 | * Configuration CB Parameter Bit Definitions\r |
477 | *--------------------------------------------------------------------------\r |
478 | */\r |
479 | // - Byte 0 (Default Value = 16h)\r |
480 | #define CFIG_BYTE_COUNT 0x16 // 22 Configuration Bytes\r |
481 | \r |
482 | //- Byte 1 (Default Value = 88h)\r |
483 | #define CFIG_TXRX_FIFO_LIMIT 0x88\r |
484 | \r |
485 | //- Byte 2 (Default Value = 0)\r |
486 | #define CFIG_ADAPTIVE_IFS 0\r |
487 | \r |
488 | //- Byte 3 (Default Value = 0, ALWAYS. This byte is RESERVED)\r |
489 | #define CFIG_RESERVED 0\r |
490 | \r |
491 | //- Byte 4 (Default Value = 0. Default implies that Rx DMA cannot be\r |
492 | //- preempted).\r |
493 | #define CFIG_RXDMA_BYTE_COUNT 0\r |
494 | \r |
495 | //- Byte 5 (Default Value = 80h. Default implies that Tx DMA cannot be\r |
496 | //- preempted. However, setting these counters is enabled.)\r |
497 | #define CFIG_DMBC_ENABLE 0x80\r |
498 | \r |
499 | //- Byte 6 (Default Value = 33h. Late SCB enabled, No TNO interrupts,\r |
500 | //- CNA interrupts and do not save bad frames.)\r |
501 | #define CFIG_LATE_SCB 1 // BIT 0\r |
502 | #define CFIG_TNO_INTERRUPT 0x4 // BIT 2\r |
503 | #define CFIG_CI_INTERRUPT 0x8 // BIT 3\r |
504 | #define CFIG_SAVE_BAD_FRAMES 0x80 // BIT_7\r |
505 | \r |
506 | //- Byte 7 (Default Value = 7h. Discard short frames automatically and\r |
507 | //- attempt upto 3 retries on transmit.)\r |
508 | #define CFIG_DISCARD_SHORTRX 0x00001\r |
509 | #define CFIG_URUN_RETRY BIT_1 OR BIT_2\r |
510 | \r |
511 | //- Byte 8 (Default Value = 1. Enable MII mode.)\r |
512 | #define CFIG_503_MII BIT_0\r |
513 | \r |
514 | //- Byte 9 (Default Value = 0, ALWAYS)\r |
515 | \r |
516 | //- Byte 10 (Default Value = 2Eh)\r |
517 | #define CFIG_NSAI BIT_3\r |
518 | #define CFIG_PREAMBLE_LENGTH BIT_5 ;- Bit 5-4 = 1-0\r |
519 | #define CFIG_NO_LOOPBACK 0\r |
520 | #define CFIG_INTERNAL_LOOPBACK BIT_6\r |
521 | #define CFIG_EXT_LOOPBACK BIT_7\r |
522 | #define CFIG_EXT_PIN_LOOPBACK BIT_6 OR BIT_7\r |
523 | \r |
524 | //- Byte 11 (Default Value = 0)\r |
525 | #define CFIG_LINEAR_PRIORITY 0\r |
526 | \r |
527 | //- Byte 12 (Default Value = 60h)\r |
528 | #define CFIG_LPRIORITY_MODE 0\r |
529 | #define CFIG_IFS 6 ;- 6 * 16 = 96\r |
530 | \r |
531 | //- Byte 13 (Default Value = 0, ALWAYS)\r |
532 | \r |
533 | //- Byte 14 (Default Value = 0F2h, ALWAYS)\r |
534 | \r |
535 | //- Byte 15 (Default Value = E8h)\r |
536 | #define CFIG_PROMISCUOUS_MODE BIT_0\r |
537 | #define CFIG_BROADCAST_DISABLE BIT_1\r |
538 | #define CFIG_CRS_CDT BIT_7\r |
539 | \r |
540 | //- Byte 16 (Default Value = 0, ALWAYS)\r |
541 | \r |
542 | //- Byte 17 (Default Value = 40h, ALWAYS)\r |
543 | \r |
544 | //- Byte 18 (Default Value = F2h)\r |
545 | #define CFIG_STRIPPING BIT_0\r |
546 | #define CFIG_PADDING BIT_1\r |
547 | #define CFIG_RX_CRC_TRANSFER BIT_2\r |
548 | \r |
549 | //- Byte 19 (Default Value = 80h)\r |
550 | #define CFIG_FORCE_FDX BIT_6\r |
551 | #define CFIG_FDX_PIN_ENABLE BIT_7\r |
552 | \r |
553 | //- Byte 20 (Default Value = 3Fh)\r |
554 | #define CFIG_MULTI_IA BIT_6\r |
555 | \r |
556 | //- Byte 21 (Default Value = 05)\r |
557 | #define CFIG_MC_ALL BIT_3\r |
558 | \r |
559 | /*-----------------------------------------------------------------------*/\r |
560 | #define D102_REVID 0x0b\r |
561 | \r |
562 | #define HALF_DUPLEX 1\r |
563 | #define FULL_DUPLEX 2\r |
564 | \r |
565 | typedef struct s_data_instance {\r |
566 | \r |
567 | UINT16 State; // stopped, started or initialized\r |
568 | UINT16 Bus;\r |
569 | UINT8 Device;\r |
570 | UINT8 Function;\r |
571 | UINT16 VendorID;\r |
572 | UINT16 DeviceID;\r |
573 | UINT16 RevID;\r |
574 | UINT16 SubVendorID;\r |
575 | UINT16 SubSystemID;\r |
576 | \r |
577 | UINT8 PermNodeAddress[PXE_MAC_LENGTH];\r |
578 | UINT8 CurrentNodeAddress[PXE_MAC_LENGTH];\r |
579 | UINT8 BroadcastNodeAddress[PXE_MAC_LENGTH];\r |
580 | UINT32 Config[MAX_PCI_CONFIG_LEN];\r |
581 | UINT32 NVData[MAX_EEPROM_LEN];\r |
582 | \r |
583 | UINT32 ioaddr;\r |
584 | UINT32 flash_addr;\r |
585 | \r |
586 | UINT16 LinkSpeed; // actual link speed setting\r |
587 | UINT16 LinkSpeedReq; // requested (forced) link speed\r |
588 | UINT8 DuplexReq; // requested duplex\r |
589 | UINT8 Duplex; // Duplex set\r |
590 | UINT8 CableDetect; // 1 to detect and 0 not to detect the cable\r |
591 | UINT8 LoopBack;\r |
592 | \r |
593 | UINT16 TxBufCnt;\r |
594 | UINT16 TxBufSize;\r |
595 | UINT16 RxBufCnt;\r |
596 | UINT16 RxBufSize;\r |
597 | UINT32 RxTotals;\r |
598 | UINT32 TxTotals;\r |
599 | \r |
600 | UINT16 int_mask;\r |
601 | UINT16 Int_Status;\r |
602 | UINT16 PhyRecord[2]; // primary and secondary PHY record registers from eeprom\r |
603 | UINT8 PhyAddress;\r |
604 | UINT8 int_num;\r |
605 | UINT16 NVData_Len;\r |
606 | UINT32 MemoryLength;\r |
607 | \r |
608 | RxFD *rx_ring; // array of rx buffers\r |
609 | TxCB *tx_ring; // array of tx buffers\r |
610 | struct speedo_stats *statistics;\r |
611 | TxCB *FreeTxHeadPtr;\r |
612 | TxCB *FreeTxTailPtr;\r |
613 | RxFD *RFDTailPtr;\r |
614 | \r |
615 | UINT64 rx_phy_addr; // physical addresses\r |
616 | UINT64 tx_phy_addr;\r |
617 | UINT64 stat_phy_addr;\r |
618 | UINT64 MemoryPtr;\r |
619 | UINT64 Mapped_MemoryPtr;\r |
620 | \r |
621 | UINT64 xmit_done[TX_BUFFER_COUNT << 1]; // circular buffer\r |
622 | UINT16 xmit_done_head; // index into the xmit_done array\r |
623 | UINT16 xmit_done_tail; // where are we filling now (index into xmit_done)\r |
624 | UINT16 cur_rx_ind; // current RX Q head index\r |
625 | UINT16 FreeCBCount;\r |
626 | \r |
627 | BOOLEAN in_interrupt;\r |
628 | BOOLEAN in_transmit;\r |
629 | BOOLEAN Receive_Started;\r |
630 | UINT8 Rx_Filter;\r |
631 | UINT8 VersionFlag; // UNDI30 or UNDI31??\r |
632 | UINT8 rsvd[3];\r |
41057d77 |
633 | \r |
40834173 |
634 | struct mc{\r |
635 | UINT16 reserved [3]; // padding for this structure to make it 8 byte aligned\r |
636 | UINT16 list_len;\r |
637 | UINT8 mc_list[MAX_MCAST_ADDRESS_CNT][PXE_MAC_LENGTH]; // 8*32 is the size\r |
638 | } mcast_list;\r |
639 | \r |
640 | UINT64 Unique_ID;\r |
641 | \r |
642 | EFI_PCI_IO_PROTOCOL *Io_Function;\r |
68246fa8 |
643 | //\r |
644 | // Original PCI attributes\r |
645 | //\r |
646 | UINT64 OriginalPciAttributes;\r |
40834173 |
647 | \r |
648 | VOID (*Delay_30)(UINTN); // call back routine\r |
649 | VOID (*Virt2Phys_30)(UINT64 virtual_addr, UINT64 physical_ptr); // call back routine\r |
650 | VOID (*Block_30)(UINT32 enable); // call back routine\r |
651 | VOID (*Mem_Io_30)(UINT8 read_write, UINT8 len, UINT64 port, UINT64 buf_addr);\r |
652 | VOID (*Delay)(UINT64, UINTN); // call back routine\r |
653 | VOID (*Virt2Phys)(UINT64 unq_id, UINT64 virtual_addr, UINT64 physical_ptr); // call back routine\r |
654 | VOID (*Block)(UINT64 unq_id, UINT32 enable); // call back routine\r |
655 | VOID (*Mem_Io)(UINT64 unq_id, UINT8 read_write, UINT8 len, UINT64 port,\r |
656 | UINT64 buf_addr);\r |
657 | VOID (*Map_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r |
658 | UINT32 Direction, UINT64 mapped_addr);\r |
659 | VOID (*UnMap_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r |
660 | UINT32 Direction, UINT64 mapped_addr);\r |
661 | VOID (*Sync_Mem)(UINT64 unq_id, UINT64 virtual_addr,\r |
662 | UINT32 size, UINT32 Direction, UINT64 mapped_addr);\r |
663 | } NIC_DATA_INSTANCE;\r |
664 | \r |
665 | #pragma pack(1)\r |
666 | struct MC_CB_STRUCT{\r |
667 | UINT16 count;\r |
668 | UINT8 m_list[MAX_MCAST_ADDRESS_CNT][ETHER_MAC_ADDR_LEN];\r |
669 | };\r |
670 | #pragma pack()\r |
671 | \r |
672 | #define FOUR_GIGABYTE (UINT64)0x100000000ULL\r |