MdeModulePkg Xhci: Correct description of Timeout param in XhciReg.h
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.h
CommitLineData
92870c98 1/** @file\r
2\r
3 This file contains the register definition of XHCI host controller.\r
4\r
2f6ef874 5Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>\r
92870c98 6This program and the accompanying materials\r
7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#ifndef _EFI_XHCI_REG_H_\r
17#define _EFI_XHCI_REG_H_\r
18\r
19#define PCI_IF_XHCI 0x30\r
20\r
21//\r
22// PCI Configuration Registers\r
23//\r
24#define XHC_BAR_INDEX 0x00\r
25\r
26#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset\r
27#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask\r
28\r
29#define USB_HUB_CLASS_CODE 0x09\r
30#define USB_HUB_SUBCLASS_CODE 0x00\r
31\r
5bcb62a4
EL
32#define XHC_CAP_USB_LEGACY 0x01\r
33#define XHC_CAP_USB_DEBUG 0x0A\r
34\r
92870c98 35//============================================//\r
36// XHCI register offset //\r
37//============================================//\r
38\r
39//\r
40// Capability registers offset\r
41//\r
42#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset\r
43#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h\r
44#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1\r
45#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2\r
46#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3\r
47#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters\r
48#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset\r
49#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset\r
50\r
51//\r
52// Operational registers offset\r
53//\r
54#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset\r
55#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset\r
56#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset\r
57#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset\r
58#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset\r
59#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset\r
60#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset\r
61#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset\r
62\r
63//\r
64// Runtime registers offset\r
65//\r
66#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset\r
67#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset\r
68#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset\r
69#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset\r
70#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset\r
71#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset\r
72\r
5bcb62a4
EL
73//\r
74// Debug registers offset\r
75//\r
76#define XHC_DC_DCCTRL 0x20\r
77\r
92870c98 78#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore\r
79#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore\r
80\r
81#pragma pack (1)\r
a9292c13 82typedef struct {\r
83 UINT8 MaxSlots; // Number of Device Slots\r
84 UINT16 MaxIntrs:11; // Number of Interrupters\r
85 UINT16 Rsvd:5;\r
86 UINT8 MaxPorts; // Number of Ports\r
87} HCSPARAMS1;\r
88\r
92870c98 89//\r
90// Structural Parameters 1 Register Bitmap Definition\r
91//\r
a9292c13 92typedef union {\r
93 UINT32 Dword;\r
94 HCSPARAMS1 Data;\r
92870c98 95} XHC_HCSPARAMS1;\r
96\r
a9292c13 97typedef struct {\r
98 UINT32 Ist:4; // Isochronous Scheduling Threshold\r
99 UINT32 Erst:4; // Event Ring Segment Table Max\r
100 UINT32 Rsvd:13;\r
101 UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi\r
102 UINT32 Spr:1; // Scratchpad Restore\r
103 UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo\r
104} HCSPARAMS2;\r
105\r
92870c98 106//\r
107// Structural Parameters 2 Register Bitmap Definition\r
108//\r
a9292c13 109typedef union {\r
110 UINT32 Dword;\r
111 HCSPARAMS2 Data;\r
92870c98 112} XHC_HCSPARAMS2;\r
113\r
a9292c13 114typedef struct {\r
115 UINT16 Ac64:1; // 64-bit Addressing Capability\r
116 UINT16 Bnc:1; // BW Negotiation Capability\r
117 UINT16 Csz:1; // Context Size\r
118 UINT16 Ppc:1; // Port Power Control\r
119 UINT16 Pind:1; // Port Indicators\r
120 UINT16 Lhrc:1; // Light HC Reset Capability\r
121 UINT16 Ltc:1; // Latency Tolerance Messaging Capability\r
122 UINT16 Nss:1; // No Secondary SID Support\r
123 UINT16 Pae:1; // Parse All Event Data\r
124 UINT16 Rsvd:3;\r
125 UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size\r
126 UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer\r
127} HCCPARAMS;\r
128\r
92870c98 129//\r
130// Capability Parameters Register Bitmap Definition\r
131//\r
a9292c13 132typedef union {\r
133 UINT32 Dword;\r
134 HCCPARAMS Data;\r
92870c98 135} XHC_HCCPARAMS;\r
136\r
137#pragma pack ()\r
138\r
139//\r
140// Register Bit Definition\r
141//\r
142#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
143#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
144#define XHC_USBCMD_INTE BIT2 // Interrupter Enable\r
145#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable\r
146\r
147#define XHC_USBSTS_HALT BIT0 // Host Controller Halted\r
148#define XHC_USBSTS_HSE BIT2 // Host System Error\r
149#define XHC_USBSTS_EINT BIT3 // Event Interrupt\r
150#define XHC_USBSTS_PCD BIT4 // Port Change Detect\r
151#define XHC_USBSTS_SSS BIT8 // Save State Status\r
152#define XHC_USBSTS_RSS BIT9 // Restore State Status\r
153#define XHC_USBSTS_SRE BIT10 // Save/Restore Error\r
154#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready\r
155#define XHC_USBSTS_HCE BIT12 // Host Controller Error\r
156\r
157#define XHC_PAGESIZE_MASK 0xFFFF // Page Size\r
158\r
159#define XHC_CRCR_RCS BIT0 // Ring Cycle State\r
160#define XHC_CRCR_CS BIT1 // Command Stop\r
161#define XHC_CRCR_CA BIT2 // Command Abort\r
162#define XHC_CRCR_CRR BIT3 // Command Ring Running\r
163\r
164#define XHC_CONFIG_MASK 0xFF // Command Ring Running\r
165\r
166#define XHC_PORTSC_CCS BIT0 // Current Connect Status\r
167#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled\r
168#define XHC_PORTSC_OCA BIT3 // Over-current Active\r
169#define XHC_PORTSC_RESET BIT4 // Port Reset\r
170#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State\r
171#define XHC_PORTSC_PP BIT9 // Port Power\r
c3f44a77 172#define XHC_PORTSC_PS (BIT10|BIT11|BIT12) // Port Speed\r
92870c98 173#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe\r
174#define XHC_PORTSC_CSC BIT17 // Connect Status Change\r
175#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change\r
176#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change\r
177#define XHC_PORTSC_OCC BIT20 // Over-Current Change\r
178#define XHC_PORTSC_PRC BIT21 // Port Reset Change\r
179#define XHC_PORTSC_PLC BIT22 // Port Link State Change\r
180#define XHC_PORTSC_CEC BIT23 // Port Config Error Change\r
181#define XHC_PORTSC_CAS BIT24 // Cold Attach Status\r
182\r
a50f7c4c 183#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status\r
184#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled\r
185#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active\r
186#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset\r
187#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power\r
188#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change\r
189#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change\r
190#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change\r
191#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change\r
c3f44a77 192#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change\r
92870c98 193#define XHC_IMAN_IP BIT0 // Interrupt Pending\r
194#define XHC_IMAN_IE BIT1 // Interrupt Enable\r
195\r
196#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval\r
197#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter\r
198\r
c3f44a77
FT
199//\r
200// Hub Class Feature Selector for Clear Port Feature Request\r
8d84dbe9
FT
201// It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
202// For more details, Please refer to USB 3.0 Spec Table 10-7.\r
c3f44a77 203//\r
8d84dbe9
FT
204typedef enum {\r
205 Usb3PortBHPortReset = 28,\r
206 Usb3PortBHPortResetChange = 29\r
207} XHC_PORT_FEATURE;\r
c3f44a77 208\r
92870c98 209//\r
210// Structure to map the hardware port states to the\r
211// UEFI's port states.\r
212//\r
213typedef struct {\r
214 UINT32 HwState;\r
215 UINT16 UefiState;\r
216} USB_PORT_STATE_MAP;\r
217\r
c3f44a77
FT
218//\r
219// Structure to map the hardware port states to feature selector for clear port feature request.\r
220//\r
221typedef struct {\r
222 UINT32 HwState;\r
223 UINT16 Selector;\r
224} USB_CLEAR_PORT_MAP;\r
225\r
92870c98 226/**\r
227 Read 1-byte width XHCI capability register.\r
228\r
a9292c13 229 @param Xhc The XHCI Instance.\r
92870c98 230 @param Offset The offset of the 1-byte width capability register.\r
231\r
232 @return The register content read.\r
233 @retval If err, return 0xFFFF.\r
234\r
235**/\r
236UINT8\r
237XhcReadCapReg8 (\r
a9292c13 238 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 239 IN UINT32 Offset\r
240 );\r
241\r
242/**\r
243 Read 4-bytes width XHCI capability register.\r
244\r
a9292c13 245 @param Xhc The XHCI Instance.\r
92870c98 246 @param Offset The offset of the 4-bytes width capability register.\r
247\r
248 @return The register content read.\r
249 @retval If err, return 0xFFFFFFFF.\r
250\r
251**/\r
252UINT32\r
253XhcReadCapReg (\r
a9292c13 254 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 255 IN UINT32 Offset\r
256 );\r
257\r
258/**\r
259 Read 4-bytes width XHCI Operational register.\r
260\r
a9292c13 261 @param Xhc The XHCI Instance.\r
92870c98 262 @param Offset The offset of the 4-bytes width operational register.\r
263\r
264 @return The register content read.\r
265 @retval If err, return 0xFFFFFFFF.\r
266\r
267**/\r
268UINT32\r
269XhcReadOpReg (\r
a9292c13 270 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 271 IN UINT32 Offset\r
272 );\r
273\r
274/**\r
275 Write the data to the 4-bytes width XHCI operational register.\r
276\r
a9292c13 277 @param Xhc The XHCI Instance.\r
92870c98 278 @param Offset The offset of the 4-bytes width operational register.\r
279 @param Data The data to write.\r
280\r
281**/\r
282VOID\r
283XhcWriteOpReg (\r
a9292c13 284 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 285 IN UINT32 Offset,\r
286 IN UINT32 Data\r
287 );\r
288\r
289/**\r
290 Write the data to the 2-bytes width XHCI operational register.\r
291\r
a9292c13 292 @param Xhc The XHCI Instance.\r
92870c98 293 @param Offset The offset of the 2-bytes width operational register.\r
294 @param Data The data to write.\r
295\r
296**/\r
297VOID\r
298XhcWriteOpReg16 (\r
a9292c13 299 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 300 IN UINT32 Offset,\r
301 IN UINT16 Data\r
302 );\r
303\r
92870c98 304/**\r
305 Read XHCI runtime register.\r
306\r
a9292c13 307 @param Xhc The XHCI Instance.\r
92870c98 308 @param Offset The offset of the runtime register.\r
309\r
310 @return The register content read\r
311\r
312**/\r
313UINT32\r
314XhcReadRuntimeReg (\r
a9292c13 315 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 316 IN UINT32 Offset\r
317 );\r
318\r
92870c98 319/**\r
320 Write the data to the XHCI runtime register.\r
321\r
a9292c13 322 @param Xhc The XHCI Instance.\r
92870c98 323 @param Offset The offset of the runtime register.\r
324 @param Data The data to write.\r
325\r
326**/\r
327VOID\r
328XhcWriteRuntimeReg (\r
a9292c13 329 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 330 IN UINT32 Offset,\r
331 IN UINT32 Data\r
332 );\r
333\r
92870c98 334/**\r
335 Read XHCI door bell register.\r
336\r
a9292c13 337 @param Xhc The XHCI Instance.\r
92870c98 338 @param Offset The offset of the door bell register.\r
339\r
340 @return The register content read\r
341\r
342**/\r
343UINT32\r
344XhcReadDoorBellReg (\r
a9292c13 345 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 346 IN UINT32 Offset\r
347 );\r
348\r
349/**\r
350 Write the data to the XHCI door bell register.\r
351\r
a9292c13 352 @param Xhc The XHCI Instance.\r
92870c98 353 @param Offset The offset of the door bell register.\r
354 @param Data The data to write.\r
355\r
356**/\r
357VOID\r
358XhcWriteDoorBellReg (\r
a9292c13 359 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 360 IN UINT32 Offset,\r
361 IN UINT32 Data\r
362 );\r
363\r
364/**\r
365 Set one bit of the operational register while keeping other bits.\r
366\r
a9292c13 367 @param Xhc The XHCI Instance.\r
92870c98 368 @param Offset The offset of the operational register.\r
369 @param Bit The bit mask of the register to set.\r
370\r
371**/\r
372VOID\r
373XhcSetOpRegBit (\r
a9292c13 374 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 375 IN UINT32 Offset,\r
376 IN UINT32 Bit\r
377 );\r
378\r
379/**\r
380 Clear one bit of the operational register while keeping other bits.\r
381\r
a9292c13 382 @param Xhc The XHCI Instance.\r
92870c98 383 @param Offset The offset of the operational register.\r
384 @param Bit The bit mask of the register to clear.\r
385\r
386**/\r
387VOID\r
388XhcClearOpRegBit (\r
a9292c13 389 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 390 IN UINT32 Offset,\r
391 IN UINT32 Bit\r
392 );\r
393\r
394/**\r
395 Wait the operation register's bit as specified by Bit\r
396 to be set (or clear).\r
397\r
a9292c13 398 @param Xhc The XHCI Instance.\r
92870c98 399 @param Offset The offset of the operational register.\r
400 @param Bit The bit of the register to wait for.\r
401 @param WaitToSet Wait the bit to set or clear.\r
2f6ef874 402 @param Timeout The time to wait before abort (in millisecond, ms).\r
92870c98 403\r
404 @retval EFI_SUCCESS The bit successfully changed by host controller.\r
405 @retval EFI_TIMEOUT The time out occurred.\r
406\r
407**/\r
408EFI_STATUS\r
409XhcWaitOpRegBit (\r
a9292c13 410 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 411 IN UINT32 Offset,\r
412 IN UINT32 Bit,\r
413 IN BOOLEAN WaitToSet,\r
414 IN UINT32 Timeout\r
415 );\r
416\r
417/**\r
418 Read XHCI runtime register.\r
419\r
a9292c13 420 @param Xhc The XHCI Instance.\r
92870c98 421 @param Offset The offset of the runtime register.\r
422\r
423 @return The register content read\r
424\r
425**/\r
426UINT32\r
427XhcReadRuntimeReg (\r
a9292c13 428 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 429 IN UINT32 Offset\r
430 );\r
431\r
432/**\r
433 Write the data to the XHCI runtime register.\r
434\r
a9292c13 435 @param Xhc The XHCI Instance.\r
92870c98 436 @param Offset The offset of the runtime register.\r
437 @param Data The data to write.\r
438\r
439**/\r
440VOID\r
441XhcWriteRuntimeReg (\r
a9292c13 442 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 443 IN UINT32 Offset,\r
444 IN UINT32 Data\r
445 );\r
446\r
447/**\r
448 Set one bit of the runtime register while keeping other bits.\r
449\r
a9292c13 450 @param Xhc The XHCI Instance.\r
92870c98 451 @param Offset The offset of the runtime register.\r
452 @param Bit The bit mask of the register to set.\r
453\r
454**/\r
455VOID\r
456XhcSetRuntimeRegBit (\r
a9292c13 457 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 458 IN UINT32 Offset,\r
459 IN UINT32 Bit\r
460 );\r
461\r
462/**\r
463 Clear one bit of the runtime register while keeping other bits.\r
464\r
a9292c13 465 @param Xhc The XHCI Instance.\r
92870c98 466 @param Offset The offset of the runtime register.\r
467 @param Bit The bit mask of the register to set.\r
468\r
469**/\r
470VOID\r
471XhcClearRuntimeRegBit (\r
a9292c13 472 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 473 IN UINT32 Offset,\r
474 IN UINT32 Bit\r
475 );\r
476\r
5bcb62a4
EL
477/**\r
478 Read XHCI extended capability register.\r
479\r
480 @param Xhc The XHCI Instance.\r
481 @param Offset The offset of the extended capability register.\r
482\r
483 @return The register content read\r
484\r
485**/\r
486UINT32\r
487XhcReadExtCapReg (\r
488 IN USB_XHCI_INSTANCE *Xhc,\r
489 IN UINT32 Offset\r
490 );\r
491\r
92870c98 492/**\r
493 Whether the XHCI host controller is halted.\r
494\r
a9292c13 495 @param Xhc The XHCI Instance.\r
92870c98 496\r
497 @retval TRUE The controller is halted.\r
498 @retval FALSE It isn't halted.\r
499\r
500**/\r
501BOOLEAN\r
502XhcIsHalt (\r
a9292c13 503 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 504 );\r
505\r
506/**\r
507 Whether system error occurred.\r
508\r
a9292c13 509 @param Xhc The XHCI Instance.\r
92870c98 510\r
511 @retval TRUE System error happened.\r
512 @retval FALSE No system error.\r
513\r
514**/\r
515BOOLEAN\r
516XhcIsSysError (\r
a9292c13 517 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 518 );\r
519\r
520/**\r
521 Reset the XHCI host controller.\r
522\r
a9292c13 523 @param Xhc The XHCI Instance.\r
2f6ef874 524 @param Timeout Time to wait before abort (in millisecond, ms).\r
92870c98 525\r
526 @retval EFI_SUCCESS The XHCI host controller is reset.\r
527 @return Others Failed to reset the XHCI before Timeout.\r
528\r
529**/\r
530EFI_STATUS\r
531XhcResetHC (\r
a9292c13 532 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 533 IN UINT32 Timeout\r
534 );\r
535\r
536/**\r
537 Halt the XHCI host controller.\r
538\r
a9292c13 539 @param Xhc The XHCI Instance.\r
2f6ef874 540 @param Timeout Time to wait before abort (in millisecond, ms).\r
92870c98 541\r
542 @return EFI_SUCCESS The XHCI host controller is halt.\r
543 @return EFI_TIMEOUT Failed to halt the XHCI before Timeout.\r
544\r
545**/\r
546EFI_STATUS\r
547XhcHaltHC (\r
a9292c13 548 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 549 IN UINT32 Timeout\r
550 );\r
551\r
552/**\r
553 Set the XHCI host controller to run.\r
554\r
a9292c13 555 @param Xhc The XHCI Instance.\r
2f6ef874 556 @param Timeout Time to wait before abort (in millisecond, ms).\r
92870c98 557\r
558 @return EFI_SUCCESS The XHCI host controller is running.\r
559 @return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.\r
560\r
561**/\r
562EFI_STATUS\r
563XhcRunHC (\r
a9292c13 564 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 565 IN UINT32 Timeout\r
566 );\r
567\r
568/**\r
5bcb62a4 569 Calculate the offset of the XHCI capability.\r
92870c98 570\r
a9292c13 571 @param Xhc The XHCI Instance.\r
5bcb62a4 572 @param CapId The XHCI Capability ID.\r
92870c98 573\r
574 @return The offset of XHCI legacy support capability register.\r
575\r
576**/\r
577UINT32\r
5bcb62a4
EL
578XhcGetCapabilityAddr (\r
579 IN USB_XHCI_INSTANCE *Xhc,\r
580 IN UINT8 CapId\r
92870c98 581 );\r
582\r
583#endif\r