92870c98 |
1 | /** @file\r |
2 | \r |
3 | This file contains the register definition of XHCI host controller.\r |
4 | \r |
a50f7c4c |
5 | Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>\r |
92870c98 |
6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r |
8 | which accompanies this distribution. The full text of the license may be found at\r |
9 | http://opensource.org/licenses/bsd-license.php\r |
10 | \r |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
13 | \r |
14 | **/\r |
15 | \r |
16 | #ifndef _EFI_XHCI_REG_H_\r |
17 | #define _EFI_XHCI_REG_H_\r |
18 | \r |
19 | #define PCI_IF_XHCI 0x30\r |
20 | \r |
21 | //\r |
22 | // PCI Configuration Registers\r |
23 | //\r |
24 | #define XHC_BAR_INDEX 0x00\r |
25 | \r |
26 | #define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset\r |
27 | #define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask\r |
28 | \r |
29 | #define USB_HUB_CLASS_CODE 0x09\r |
30 | #define USB_HUB_SUBCLASS_CODE 0x00\r |
31 | \r |
32 | //============================================//\r |
33 | // XHCI register offset //\r |
34 | //============================================//\r |
35 | \r |
36 | //\r |
37 | // Capability registers offset\r |
38 | //\r |
39 | #define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset\r |
40 | #define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h\r |
41 | #define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1\r |
42 | #define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2\r |
43 | #define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3\r |
44 | #define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters\r |
45 | #define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset\r |
46 | #define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset\r |
47 | \r |
48 | //\r |
49 | // Operational registers offset\r |
50 | //\r |
51 | #define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset\r |
52 | #define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset\r |
53 | #define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset\r |
54 | #define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset\r |
55 | #define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset\r |
56 | #define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset\r |
57 | #define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset\r |
58 | #define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset\r |
59 | \r |
60 | //\r |
61 | // Runtime registers offset\r |
62 | //\r |
63 | #define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset\r |
64 | #define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset\r |
65 | #define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset\r |
66 | #define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset\r |
67 | #define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset\r |
68 | #define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset\r |
69 | \r |
70 | #define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore\r |
71 | #define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore\r |
72 | \r |
73 | #pragma pack (1)\r |
a9292c13 |
74 | typedef struct {\r |
75 | UINT8 MaxSlots; // Number of Device Slots\r |
76 | UINT16 MaxIntrs:11; // Number of Interrupters\r |
77 | UINT16 Rsvd:5;\r |
78 | UINT8 MaxPorts; // Number of Ports\r |
79 | } HCSPARAMS1;\r |
80 | \r |
92870c98 |
81 | //\r |
82 | // Structural Parameters 1 Register Bitmap Definition\r |
83 | //\r |
a9292c13 |
84 | typedef union {\r |
85 | UINT32 Dword;\r |
86 | HCSPARAMS1 Data;\r |
92870c98 |
87 | } XHC_HCSPARAMS1;\r |
88 | \r |
a9292c13 |
89 | typedef struct {\r |
90 | UINT32 Ist:4; // Isochronous Scheduling Threshold\r |
91 | UINT32 Erst:4; // Event Ring Segment Table Max\r |
92 | UINT32 Rsvd:13;\r |
93 | UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi\r |
94 | UINT32 Spr:1; // Scratchpad Restore\r |
95 | UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo\r |
96 | } HCSPARAMS2;\r |
97 | \r |
92870c98 |
98 | //\r |
99 | // Structural Parameters 2 Register Bitmap Definition\r |
100 | //\r |
a9292c13 |
101 | typedef union {\r |
102 | UINT32 Dword;\r |
103 | HCSPARAMS2 Data;\r |
92870c98 |
104 | } XHC_HCSPARAMS2;\r |
105 | \r |
a9292c13 |
106 | typedef struct {\r |
107 | UINT16 Ac64:1; // 64-bit Addressing Capability\r |
108 | UINT16 Bnc:1; // BW Negotiation Capability\r |
109 | UINT16 Csz:1; // Context Size\r |
110 | UINT16 Ppc:1; // Port Power Control\r |
111 | UINT16 Pind:1; // Port Indicators\r |
112 | UINT16 Lhrc:1; // Light HC Reset Capability\r |
113 | UINT16 Ltc:1; // Latency Tolerance Messaging Capability\r |
114 | UINT16 Nss:1; // No Secondary SID Support\r |
115 | UINT16 Pae:1; // Parse All Event Data\r |
116 | UINT16 Rsvd:3;\r |
117 | UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size\r |
118 | UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer\r |
119 | } HCCPARAMS;\r |
120 | \r |
92870c98 |
121 | //\r |
122 | // Capability Parameters Register Bitmap Definition\r |
123 | //\r |
a9292c13 |
124 | typedef union {\r |
125 | UINT32 Dword;\r |
126 | HCCPARAMS Data;\r |
92870c98 |
127 | } XHC_HCCPARAMS;\r |
128 | \r |
129 | #pragma pack ()\r |
130 | \r |
131 | //\r |
132 | // Register Bit Definition\r |
133 | //\r |
134 | #define XHC_USBCMD_RUN BIT0 // Run/Stop\r |
135 | #define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r |
136 | #define XHC_USBCMD_INTE BIT2 // Interrupter Enable\r |
137 | #define XHC_USBCMD_HSEE BIT3 // Host System Error Enable\r |
138 | \r |
139 | #define XHC_USBSTS_HALT BIT0 // Host Controller Halted\r |
140 | #define XHC_USBSTS_HSE BIT2 // Host System Error\r |
141 | #define XHC_USBSTS_EINT BIT3 // Event Interrupt\r |
142 | #define XHC_USBSTS_PCD BIT4 // Port Change Detect\r |
143 | #define XHC_USBSTS_SSS BIT8 // Save State Status\r |
144 | #define XHC_USBSTS_RSS BIT9 // Restore State Status\r |
145 | #define XHC_USBSTS_SRE BIT10 // Save/Restore Error\r |
146 | #define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready\r |
147 | #define XHC_USBSTS_HCE BIT12 // Host Controller Error\r |
148 | \r |
149 | #define XHC_PAGESIZE_MASK 0xFFFF // Page Size\r |
150 | \r |
151 | #define XHC_CRCR_RCS BIT0 // Ring Cycle State\r |
152 | #define XHC_CRCR_CS BIT1 // Command Stop\r |
153 | #define XHC_CRCR_CA BIT2 // Command Abort\r |
154 | #define XHC_CRCR_CRR BIT3 // Command Ring Running\r |
155 | \r |
156 | #define XHC_CONFIG_MASK 0xFF // Command Ring Running\r |
157 | \r |
158 | #define XHC_PORTSC_CCS BIT0 // Current Connect Status\r |
159 | #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled\r |
160 | #define XHC_PORTSC_OCA BIT3 // Over-current Active\r |
161 | #define XHC_PORTSC_RESET BIT4 // Port Reset\r |
162 | #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State\r |
163 | #define XHC_PORTSC_PP BIT9 // Port Power\r |
164 | #define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed\r |
165 | #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe\r |
166 | #define XHC_PORTSC_CSC BIT17 // Connect Status Change\r |
167 | #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change\r |
168 | #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change\r |
169 | #define XHC_PORTSC_OCC BIT20 // Over-Current Change\r |
170 | #define XHC_PORTSC_PRC BIT21 // Port Reset Change\r |
171 | #define XHC_PORTSC_PLC BIT22 // Port Link State Change\r |
172 | #define XHC_PORTSC_CEC BIT23 // Port Config Error Change\r |
173 | #define XHC_PORTSC_CAS BIT24 // Cold Attach Status\r |
174 | \r |
a50f7c4c |
175 | #define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status\r |
176 | #define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled\r |
177 | #define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active\r |
178 | #define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset\r |
179 | #define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power\r |
180 | #define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change\r |
181 | #define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change\r |
182 | #define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change\r |
183 | #define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change\r |
92870c98 |
184 | #define XHC_IMAN_IP BIT0 // Interrupt Pending\r |
185 | #define XHC_IMAN_IE BIT1 // Interrupt Enable\r |
186 | \r |
187 | #define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval\r |
188 | #define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter\r |
189 | \r |
190 | //\r |
191 | // Structure to map the hardware port states to the\r |
192 | // UEFI's port states.\r |
193 | //\r |
194 | typedef struct {\r |
195 | UINT32 HwState;\r |
196 | UINT16 UefiState;\r |
197 | } USB_PORT_STATE_MAP;\r |
198 | \r |
199 | /**\r |
200 | Read 1-byte width XHCI capability register.\r |
201 | \r |
a9292c13 |
202 | @param Xhc The XHCI Instance.\r |
92870c98 |
203 | @param Offset The offset of the 1-byte width capability register.\r |
204 | \r |
205 | @return The register content read.\r |
206 | @retval If err, return 0xFFFF.\r |
207 | \r |
208 | **/\r |
209 | UINT8\r |
210 | XhcReadCapReg8 (\r |
a9292c13 |
211 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
212 | IN UINT32 Offset\r |
213 | );\r |
214 | \r |
215 | /**\r |
216 | Read 4-bytes width XHCI capability register.\r |
217 | \r |
a9292c13 |
218 | @param Xhc The XHCI Instance.\r |
92870c98 |
219 | @param Offset The offset of the 4-bytes width capability register.\r |
220 | \r |
221 | @return The register content read.\r |
222 | @retval If err, return 0xFFFFFFFF.\r |
223 | \r |
224 | **/\r |
225 | UINT32\r |
226 | XhcReadCapReg (\r |
a9292c13 |
227 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
228 | IN UINT32 Offset\r |
229 | );\r |
230 | \r |
231 | /**\r |
232 | Read 4-bytes width XHCI Operational register.\r |
233 | \r |
a9292c13 |
234 | @param Xhc The XHCI Instance.\r |
92870c98 |
235 | @param Offset The offset of the 4-bytes width operational register.\r |
236 | \r |
237 | @return The register content read.\r |
238 | @retval If err, return 0xFFFFFFFF.\r |
239 | \r |
240 | **/\r |
241 | UINT32\r |
242 | XhcReadOpReg (\r |
a9292c13 |
243 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
244 | IN UINT32 Offset\r |
245 | );\r |
246 | \r |
247 | /**\r |
248 | Write the data to the 4-bytes width XHCI operational register.\r |
249 | \r |
a9292c13 |
250 | @param Xhc The XHCI Instance.\r |
92870c98 |
251 | @param Offset The offset of the 4-bytes width operational register.\r |
252 | @param Data The data to write.\r |
253 | \r |
254 | **/\r |
255 | VOID\r |
256 | XhcWriteOpReg (\r |
a9292c13 |
257 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
258 | IN UINT32 Offset,\r |
259 | IN UINT32 Data\r |
260 | );\r |
261 | \r |
262 | /**\r |
263 | Write the data to the 2-bytes width XHCI operational register.\r |
264 | \r |
a9292c13 |
265 | @param Xhc The XHCI Instance.\r |
92870c98 |
266 | @param Offset The offset of the 2-bytes width operational register.\r |
267 | @param Data The data to write.\r |
268 | \r |
269 | **/\r |
270 | VOID\r |
271 | XhcWriteOpReg16 (\r |
a9292c13 |
272 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
273 | IN UINT32 Offset,\r |
274 | IN UINT16 Data\r |
275 | );\r |
276 | \r |
92870c98 |
277 | /**\r |
278 | Read XHCI runtime register.\r |
279 | \r |
a9292c13 |
280 | @param Xhc The XHCI Instance.\r |
92870c98 |
281 | @param Offset The offset of the runtime register.\r |
282 | \r |
283 | @return The register content read\r |
284 | \r |
285 | **/\r |
286 | UINT32\r |
287 | XhcReadRuntimeReg (\r |
a9292c13 |
288 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
289 | IN UINT32 Offset\r |
290 | );\r |
291 | \r |
92870c98 |
292 | /**\r |
293 | Write the data to the XHCI runtime register.\r |
294 | \r |
a9292c13 |
295 | @param Xhc The XHCI Instance.\r |
92870c98 |
296 | @param Offset The offset of the runtime register.\r |
297 | @param Data The data to write.\r |
298 | \r |
299 | **/\r |
300 | VOID\r |
301 | XhcWriteRuntimeReg (\r |
a9292c13 |
302 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
303 | IN UINT32 Offset,\r |
304 | IN UINT32 Data\r |
305 | );\r |
306 | \r |
92870c98 |
307 | /**\r |
308 | Read XHCI door bell register.\r |
309 | \r |
a9292c13 |
310 | @param Xhc The XHCI Instance.\r |
92870c98 |
311 | @param Offset The offset of the door bell register.\r |
312 | \r |
313 | @return The register content read\r |
314 | \r |
315 | **/\r |
316 | UINT32\r |
317 | XhcReadDoorBellReg (\r |
a9292c13 |
318 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
319 | IN UINT32 Offset\r |
320 | );\r |
321 | \r |
322 | /**\r |
323 | Write the data to the XHCI door bell register.\r |
324 | \r |
a9292c13 |
325 | @param Xhc The XHCI Instance.\r |
92870c98 |
326 | @param Offset The offset of the door bell register.\r |
327 | @param Data The data to write.\r |
328 | \r |
329 | **/\r |
330 | VOID\r |
331 | XhcWriteDoorBellReg (\r |
a9292c13 |
332 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
333 | IN UINT32 Offset,\r |
334 | IN UINT32 Data\r |
335 | );\r |
336 | \r |
337 | /**\r |
338 | Set one bit of the operational register while keeping other bits.\r |
339 | \r |
a9292c13 |
340 | @param Xhc The XHCI Instance.\r |
92870c98 |
341 | @param Offset The offset of the operational register.\r |
342 | @param Bit The bit mask of the register to set.\r |
343 | \r |
344 | **/\r |
345 | VOID\r |
346 | XhcSetOpRegBit (\r |
a9292c13 |
347 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
348 | IN UINT32 Offset,\r |
349 | IN UINT32 Bit\r |
350 | );\r |
351 | \r |
352 | /**\r |
353 | Clear one bit of the operational register while keeping other bits.\r |
354 | \r |
a9292c13 |
355 | @param Xhc The XHCI Instance.\r |
92870c98 |
356 | @param Offset The offset of the operational register.\r |
357 | @param Bit The bit mask of the register to clear.\r |
358 | \r |
359 | **/\r |
360 | VOID\r |
361 | XhcClearOpRegBit (\r |
a9292c13 |
362 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
363 | IN UINT32 Offset,\r |
364 | IN UINT32 Bit\r |
365 | );\r |
366 | \r |
367 | /**\r |
368 | Wait the operation register's bit as specified by Bit\r |
369 | to be set (or clear).\r |
370 | \r |
a9292c13 |
371 | @param Xhc The XHCI Instance.\r |
92870c98 |
372 | @param Offset The offset of the operational register.\r |
373 | @param Bit The bit of the register to wait for.\r |
374 | @param WaitToSet Wait the bit to set or clear.\r |
375 | @param Timeout The time to wait before abort (in millisecond, ms).\r |
376 | \r |
377 | @retval EFI_SUCCESS The bit successfully changed by host controller.\r |
378 | @retval EFI_TIMEOUT The time out occurred.\r |
379 | \r |
380 | **/\r |
381 | EFI_STATUS\r |
382 | XhcWaitOpRegBit (\r |
a9292c13 |
383 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
384 | IN UINT32 Offset,\r |
385 | IN UINT32 Bit,\r |
386 | IN BOOLEAN WaitToSet,\r |
387 | IN UINT32 Timeout\r |
388 | );\r |
389 | \r |
390 | /**\r |
391 | Read XHCI runtime register.\r |
392 | \r |
a9292c13 |
393 | @param Xhc The XHCI Instance.\r |
92870c98 |
394 | @param Offset The offset of the runtime register.\r |
395 | \r |
396 | @return The register content read\r |
397 | \r |
398 | **/\r |
399 | UINT32\r |
400 | XhcReadRuntimeReg (\r |
a9292c13 |
401 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
402 | IN UINT32 Offset\r |
403 | );\r |
404 | \r |
405 | /**\r |
406 | Write the data to the XHCI runtime register.\r |
407 | \r |
a9292c13 |
408 | @param Xhc The XHCI Instance.\r |
92870c98 |
409 | @param Offset The offset of the runtime register.\r |
410 | @param Data The data to write.\r |
411 | \r |
412 | **/\r |
413 | VOID\r |
414 | XhcWriteRuntimeReg (\r |
a9292c13 |
415 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
416 | IN UINT32 Offset,\r |
417 | IN UINT32 Data\r |
418 | );\r |
419 | \r |
420 | /**\r |
421 | Set one bit of the runtime register while keeping other bits.\r |
422 | \r |
a9292c13 |
423 | @param Xhc The XHCI Instance.\r |
92870c98 |
424 | @param Offset The offset of the runtime register.\r |
425 | @param Bit The bit mask of the register to set.\r |
426 | \r |
427 | **/\r |
428 | VOID\r |
429 | XhcSetRuntimeRegBit (\r |
a9292c13 |
430 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
431 | IN UINT32 Offset,\r |
432 | IN UINT32 Bit\r |
433 | );\r |
434 | \r |
435 | /**\r |
436 | Clear one bit of the runtime register while keeping other bits.\r |
437 | \r |
a9292c13 |
438 | @param Xhc The XHCI Instance.\r |
92870c98 |
439 | @param Offset The offset of the runtime register.\r |
440 | @param Bit The bit mask of the register to set.\r |
441 | \r |
442 | **/\r |
443 | VOID\r |
444 | XhcClearRuntimeRegBit (\r |
a9292c13 |
445 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
446 | IN UINT32 Offset,\r |
447 | IN UINT32 Bit\r |
448 | );\r |
449 | \r |
450 | /**\r |
451 | Whether the XHCI host controller is halted.\r |
452 | \r |
a9292c13 |
453 | @param Xhc The XHCI Instance.\r |
92870c98 |
454 | \r |
455 | @retval TRUE The controller is halted.\r |
456 | @retval FALSE It isn't halted.\r |
457 | \r |
458 | **/\r |
459 | BOOLEAN\r |
460 | XhcIsHalt (\r |
a9292c13 |
461 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 |
462 | );\r |
463 | \r |
464 | /**\r |
465 | Whether system error occurred.\r |
466 | \r |
a9292c13 |
467 | @param Xhc The XHCI Instance.\r |
92870c98 |
468 | \r |
469 | @retval TRUE System error happened.\r |
470 | @retval FALSE No system error.\r |
471 | \r |
472 | **/\r |
473 | BOOLEAN\r |
474 | XhcIsSysError (\r |
a9292c13 |
475 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 |
476 | );\r |
477 | \r |
478 | /**\r |
479 | Reset the XHCI host controller.\r |
480 | \r |
a9292c13 |
481 | @param Xhc The XHCI Instance.\r |
92870c98 |
482 | @param Timeout Time to wait before abort (in millisecond, ms).\r |
483 | \r |
484 | @retval EFI_SUCCESS The XHCI host controller is reset.\r |
485 | @return Others Failed to reset the XHCI before Timeout.\r |
486 | \r |
487 | **/\r |
488 | EFI_STATUS\r |
489 | XhcResetHC (\r |
a9292c13 |
490 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
491 | IN UINT32 Timeout\r |
492 | );\r |
493 | \r |
494 | /**\r |
495 | Halt the XHCI host controller.\r |
496 | \r |
a9292c13 |
497 | @param Xhc The XHCI Instance.\r |
92870c98 |
498 | @param Timeout Time to wait before abort (in millisecond, ms).\r |
499 | \r |
500 | @return EFI_SUCCESS The XHCI host controller is halt.\r |
501 | @return EFI_TIMEOUT Failed to halt the XHCI before Timeout.\r |
502 | \r |
503 | **/\r |
504 | EFI_STATUS\r |
505 | XhcHaltHC (\r |
a9292c13 |
506 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
507 | IN UINT32 Timeout\r |
508 | );\r |
509 | \r |
510 | /**\r |
511 | Set the XHCI host controller to run.\r |
512 | \r |
a9292c13 |
513 | @param Xhc The XHCI Instance.\r |
92870c98 |
514 | @param Timeout Time to wait before abort (in millisecond, ms).\r |
515 | \r |
516 | @return EFI_SUCCESS The XHCI host controller is running.\r |
517 | @return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.\r |
518 | \r |
519 | **/\r |
520 | EFI_STATUS\r |
521 | XhcRunHC (\r |
a9292c13 |
522 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 |
523 | IN UINT32 Timeout\r |
524 | );\r |
525 | \r |
526 | /**\r |
527 | Calculate the XHCI legacy support capability register offset.\r |
528 | \r |
a9292c13 |
529 | @param Xhc The XHCI Instance.\r |
92870c98 |
530 | \r |
531 | @return The offset of XHCI legacy support capability register.\r |
532 | \r |
533 | **/\r |
534 | UINT32\r |
535 | XhcGetLegSupCapAddr (\r |
a9292c13 |
536 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 |
537 | );\r |
538 | \r |
539 | #endif\r |