Commit | Line | Data |
---|---|---|
92870c98 | 1 | /** @file\r |
2 | \r | |
3 | This file contains the definition for XHCI host controller schedule routines.\r | |
4 | \r | |
49be9c3c | 5 | Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>\r |
92870c98 | 6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef _EFI_XHCI_SCHED_H_\r | |
17 | #define _EFI_XHCI_SCHED_H_\r | |
18 | \r | |
19 | #define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')\r | |
20 | \r | |
21 | //\r | |
22 | // Transfer types, used in URB to identify the transfer type\r | |
23 | //\r | |
24 | #define XHC_CTRL_TRANSFER 0x01\r | |
25 | #define XHC_BULK_TRANSFER 0x02\r | |
26 | #define XHC_INT_TRANSFER_SYNC 0x04\r | |
27 | #define XHC_INT_TRANSFER_ASYNC 0x08\r | |
28 | #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r | |
29 | \r | |
30 | //\r | |
31 | // 6.4.6 TRB Types\r | |
32 | //\r | |
33 | #define TRB_TYPE_NORMAL 1\r | |
34 | #define TRB_TYPE_SETUP_STAGE 2\r | |
35 | #define TRB_TYPE_DATA_STAGE 3\r | |
36 | #define TRB_TYPE_STATUS_STAGE 4\r | |
37 | #define TRB_TYPE_ISOCH 5\r | |
38 | #define TRB_TYPE_LINK 6\r | |
39 | #define TRB_TYPE_EVENT_DATA 7\r | |
40 | #define TRB_TYPE_NO_OP 8\r | |
41 | #define TRB_TYPE_EN_SLOT 9\r | |
42 | #define TRB_TYPE_DIS_SLOT 10\r | |
43 | #define TRB_TYPE_ADDRESS_DEV 11\r | |
44 | #define TRB_TYPE_CON_ENDPOINT 12\r | |
45 | #define TRB_TYPE_EVALU_CONTXT 13\r | |
46 | #define TRB_TYPE_RESET_ENDPOINT 14\r | |
47 | #define TRB_TYPE_STOP_ENDPOINT 15\r | |
48 | #define TRB_TYPE_SET_TR_DEQUE 16\r | |
49 | #define TRB_TYPE_RESET_DEV 17\r | |
50 | #define TRB_TYPE_GET_PORT_BANW 21\r | |
51 | #define TRB_TYPE_FORCE_HEADER 22\r | |
52 | #define TRB_TYPE_NO_OP_COMMAND 23\r | |
53 | #define TRB_TYPE_TRANS_EVENT 32\r | |
54 | #define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r | |
55 | #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r | |
56 | #define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r | |
57 | #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r | |
58 | #define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r | |
59 | \r | |
60 | //\r | |
61 | // Endpoint Type (EP Type).\r | |
62 | //\r | |
63 | #define ED_NOT_VALID 0\r | |
64 | #define ED_ISOCH_OUT 1\r | |
65 | #define ED_BULK_OUT 2\r | |
66 | #define ED_INTERRUPT_OUT 3\r | |
67 | #define ED_CONTROL_BIDIR 4\r | |
68 | #define ED_ISOCH_IN 5\r | |
69 | #define ED_BULK_IN 6\r | |
70 | #define ED_INTERRUPT_IN 7\r | |
71 | \r | |
72 | //\r | |
73 | // 6.4.5 TRB Completion Codes\r | |
74 | //\r | |
75 | #define TRB_COMPLETION_INVALID 0\r | |
76 | #define TRB_COMPLETION_SUCCESS 1\r | |
77 | #define TRB_COMPLETION_DATA_BUFFER_ERROR 2\r | |
78 | #define TRB_COMPLETION_BABBLE_ERROR 3\r | |
79 | #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4\r | |
80 | #define TRB_COMPLETION_TRB_ERROR 5\r | |
81 | #define TRB_COMPLETION_STALL_ERROR 6\r | |
82 | #define TRB_COMPLETION_SHORT_PACKET 13\r | |
49be9c3c RN |
83 | #define TRB_COMPLETION_STOPPED 26\r |
84 | #define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27\r | |
92870c98 | 85 | \r |
86 | //\r | |
a9292c13 | 87 | // The topology string used to present usb device location\r |
92870c98 | 88 | //\r |
a9292c13 | 89 | typedef struct _USB_DEV_TOPOLOGY {\r |
90 | //\r | |
91 | // The tier concatenation of down stream port.\r | |
92 | //\r | |
93 | UINT32 RouteString:20;\r | |
94 | //\r | |
95 | // The root port number of the chain.\r | |
96 | //\r | |
97 | UINT32 RootPortNum:8;\r | |
98 | //\r | |
99 | // The Tier the device reside.\r | |
100 | //\r | |
101 | UINT32 TierNum:4;\r | |
102 | } USB_DEV_TOPOLOGY;\r | |
103 | \r | |
104 | //\r | |
105 | // USB Device's RouteChart\r | |
106 | //\r | |
107 | typedef union _USB_DEV_ROUTE {\r | |
108 | UINT32 Dword;\r | |
109 | USB_DEV_TOPOLOGY Route;\r | |
92870c98 | 110 | } USB_DEV_ROUTE;\r |
111 | \r | |
112 | //\r | |
113 | // Endpoint address and its capabilities\r | |
114 | //\r | |
115 | typedef struct _USB_ENDPOINT {\r | |
6b4483cd | 116 | //\r |
117 | // Store logical device address assigned by UsbBus\r | |
118 | // It's because some XHCI host controllers may assign the same physcial device\r | |
119 | // address for those devices inserted at different root port.\r | |
120 | //\r | |
121 | UINT8 BusAddr;\r | |
92870c98 | 122 | UINT8 DevAddr;\r |
123 | UINT8 EpAddr;\r | |
124 | EFI_USB_DATA_DIRECTION Direction;\r | |
125 | UINT8 DevSpeed;\r | |
126 | UINTN MaxPacket;\r | |
127 | UINTN Type;\r | |
128 | } USB_ENDPOINT;\r | |
129 | \r | |
130 | //\r | |
a9292c13 | 131 | // TRB Template\r |
92870c98 | 132 | //\r |
a9292c13 | 133 | typedef struct _TRB_TEMPLATE {\r |
134 | UINT32 Parameter1;\r | |
135 | \r | |
136 | UINT32 Parameter2;\r | |
137 | \r | |
138 | UINT32 Status;\r | |
139 | \r | |
92870c98 | 140 | UINT32 CycleBit:1;\r |
141 | UINT32 RsvdZ1:9;\r | |
142 | UINT32 Type:6;\r | |
a9292c13 | 143 | UINT32 Control:16;\r |
144 | } TRB_TEMPLATE;\r | |
92870c98 | 145 | \r |
146 | typedef struct _TRANSFER_RING {\r | |
147 | VOID *RingSeg0;\r | |
148 | UINTN TrbNumber;\r | |
a9292c13 | 149 | TRB_TEMPLATE *RingEnqueue;\r |
150 | TRB_TEMPLATE *RingDequeue;\r | |
92870c98 | 151 | UINT32 RingPCS;\r |
152 | } TRANSFER_RING;\r | |
153 | \r | |
154 | typedef struct _EVENT_RING {\r | |
92870c98 | 155 | VOID *ERSTBase;\r |
156 | VOID *EventRingSeg0;\r | |
157 | UINTN TrbNumber;\r | |
a9292c13 | 158 | TRB_TEMPLATE *EventRingEnqueue;\r |
159 | TRB_TEMPLATE *EventRingDequeue;\r | |
92870c98 | 160 | UINT32 EventRingCCS;\r |
161 | } EVENT_RING;\r | |
162 | \r | |
163 | //\r | |
164 | // URB (Usb Request Block) contains information for all kinds of\r | |
165 | // usb requests.\r | |
166 | //\r | |
167 | typedef struct _URB {\r | |
168 | UINT32 Signature;\r | |
169 | LIST_ENTRY UrbList;\r | |
170 | //\r | |
171 | // Usb Device URB related information\r | |
172 | //\r | |
173 | USB_ENDPOINT Ep;\r | |
174 | EFI_USB_DEVICE_REQUEST *Request;\r | |
175 | VOID *Data;\r | |
176 | UINTN DataLen;\r | |
1847ed0b EL |
177 | VOID *DataPhy;\r |
178 | VOID *DataMap;\r | |
92870c98 | 179 | EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r |
180 | VOID *Context;\r | |
181 | //\r | |
182 | // Execute result\r | |
183 | //\r | |
184 | UINT32 Result;\r | |
185 | //\r | |
186 | // completed data length\r | |
187 | //\r | |
188 | UINTN Completed;\r | |
189 | //\r | |
190 | // Command/Tranfer Ring info\r | |
191 | //\r | |
192 | TRANSFER_RING *Ring;\r | |
a9292c13 | 193 | TRB_TEMPLATE *TrbStart;\r |
194 | TRB_TEMPLATE *TrbEnd;\r | |
92870c98 | 195 | UINTN TrbNum;\r |
a50f7c4c | 196 | BOOLEAN StartDone;\r |
197 | BOOLEAN EndDone;\r | |
198 | BOOLEAN Finished;\r | |
199 | \r | |
200 | TRB_TEMPLATE *EvtTrb;\r | |
92870c98 | 201 | } URB;\r |
202 | \r | |
92870c98 | 203 | //\r |
204 | // 6.5 Event Ring Segment Table\r | |
205 | // The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime\r | |
206 | // expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the\r | |
207 | // Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table\r | |
208 | // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).\r | |
209 | //\r | |
210 | typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r | |
211 | UINT32 PtrLo;\r | |
212 | UINT32 PtrHi;\r | |
213 | UINT32 RingTrbSize:16;\r | |
214 | UINT32 RsvdZ1:16;\r | |
215 | UINT32 RsvdZ2;\r | |
216 | } EVENT_RING_SEG_TABLE_ENTRY;\r | |
217 | \r | |
218 | //\r | |
219 | // 6.4.1.1 Normal TRB\r | |
220 | // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r | |
221 | // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r | |
222 | // Rings, and to define the Data stage information for Control Transfer Rings.\r | |
223 | //\r | |
224 | typedef struct _TRANSFER_TRB_NORMAL {\r | |
225 | UINT32 TRBPtrLo;\r | |
a9292c13 | 226 | \r |
92870c98 | 227 | UINT32 TRBPtrHi;\r |
a9292c13 | 228 | \r |
39e97c39 | 229 | UINT32 Length:17;\r |
92870c98 | 230 | UINT32 TDSize:5;\r |
231 | UINT32 IntTarget:10;\r | |
a9292c13 | 232 | \r |
92870c98 | 233 | UINT32 CycleBit:1;\r |
234 | UINT32 ENT:1;\r | |
235 | UINT32 ISP:1;\r | |
236 | UINT32 NS:1;\r | |
237 | UINT32 CH:1;\r | |
238 | UINT32 IOC:1;\r | |
239 | UINT32 IDT:1;\r | |
240 | UINT32 RsvdZ1:2;\r | |
241 | UINT32 BEI:1;\r | |
242 | UINT32 Type:6;\r | |
243 | UINT32 RsvdZ2:16;\r | |
244 | } TRANSFER_TRB_NORMAL;\r | |
245 | \r | |
246 | //\r | |
247 | // 6.4.1.2.1 Setup Stage TRB\r | |
248 | // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.\r | |
249 | //\r | |
a9292c13 | 250 | typedef struct _TRANSFER_TRB_CONTROL_SETUP {\r |
92870c98 | 251 | UINT32 bmRequestType:8;\r |
252 | UINT32 bRequest:8;\r | |
253 | UINT32 wValue:16;\r | |
254 | \r | |
255 | UINT32 wIndex:16;\r | |
256 | UINT32 wLength:16;\r | |
257 | \r | |
39e97c39 | 258 | UINT32 Length:17;\r |
92870c98 | 259 | UINT32 RsvdZ1:5;\r |
260 | UINT32 IntTarget:10;\r | |
261 | \r | |
262 | UINT32 CycleBit:1;\r | |
263 | UINT32 RsvdZ2:4;\r | |
264 | UINT32 IOC:1;\r | |
265 | UINT32 IDT:1;\r | |
266 | UINT32 RsvdZ3:3;\r | |
267 | UINT32 Type:6;\r | |
268 | UINT32 TRT:2;\r | |
269 | UINT32 RsvdZ4:14;\r | |
270 | } TRANSFER_TRB_CONTROL_SETUP;\r | |
271 | \r | |
272 | //\r | |
273 | // 6.4.1.2.2 Data Stage TRB\r | |
274 | // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r | |
275 | //\r | |
276 | typedef struct _TRANSFER_TRB_CONTROL_DATA {\r | |
277 | UINT32 TRBPtrLo;\r | |
a9292c13 | 278 | \r |
92870c98 | 279 | UINT32 TRBPtrHi;\r |
a9292c13 | 280 | \r |
39e97c39 | 281 | UINT32 Length:17;\r |
92870c98 | 282 | UINT32 TDSize:5;\r |
283 | UINT32 IntTarget:10;\r | |
a9292c13 | 284 | \r |
92870c98 | 285 | UINT32 CycleBit:1;\r |
286 | UINT32 ENT:1;\r | |
287 | UINT32 ISP:1;\r | |
288 | UINT32 NS:1;\r | |
289 | UINT32 CH:1;\r | |
290 | UINT32 IOC:1;\r | |
291 | UINT32 IDT:1;\r | |
292 | UINT32 RsvdZ1:3;\r | |
293 | UINT32 Type:6;\r | |
294 | UINT32 DIR:1;\r | |
295 | UINT32 RsvdZ2:15;\r | |
296 | } TRANSFER_TRB_CONTROL_DATA;\r | |
297 | \r | |
298 | //\r | |
299 | // 6.4.1.2.2 Data Stage TRB\r | |
300 | // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r | |
301 | //\r | |
302 | typedef struct _TRANSFER_TRB_CONTROL_STATUS {\r | |
303 | UINT32 RsvdZ1;\r | |
304 | UINT32 RsvdZ2;\r | |
a9292c13 | 305 | \r |
92870c98 | 306 | UINT32 RsvdZ3:22;\r |
307 | UINT32 IntTarget:10;\r | |
a9292c13 | 308 | \r |
92870c98 | 309 | UINT32 CycleBit:1;\r |
310 | UINT32 ENT:1;\r | |
311 | UINT32 RsvdZ4:2;\r | |
312 | UINT32 CH:1;\r | |
313 | UINT32 IOC:1;\r | |
314 | UINT32 RsvdZ5:4;\r | |
315 | UINT32 Type:6;\r | |
316 | UINT32 DIR:1;\r | |
317 | UINT32 RsvdZ6:15;\r | |
318 | } TRANSFER_TRB_CONTROL_STATUS;\r | |
319 | \r | |
320 | //\r | |
321 | // 6.4.2.1 Transfer Event TRB\r | |
322 | // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r | |
323 | // for more information on the use and operation of Transfer Events.\r | |
324 | //\r | |
325 | typedef struct _EVT_TRB_TRANSFER {\r | |
326 | UINT32 TRBPtrLo;\r | |
a9292c13 | 327 | \r |
92870c98 | 328 | UINT32 TRBPtrHi;\r |
a9292c13 | 329 | \r |
39e97c39 | 330 | UINT32 Length:24;\r |
a9292c13 | 331 | UINT32 Completecode:8;\r |
332 | \r | |
92870c98 | 333 | UINT32 CycleBit:1;\r |
334 | UINT32 RsvdZ1:1;\r | |
335 | UINT32 ED:1;\r | |
336 | UINT32 RsvdZ2:7;\r | |
337 | UINT32 Type:6;\r | |
a9292c13 | 338 | UINT32 EndpointId:5;\r |
92870c98 | 339 | UINT32 RsvdZ3:3;\r |
340 | UINT32 SlotId:8;\r | |
341 | } EVT_TRB_TRANSFER;\r | |
342 | \r | |
343 | //\r | |
344 | // 6.4.2.2 Command Completion Event TRB\r | |
345 | // A Command Completion Event TRB shall be generated by the xHC when a command completes on the\r | |
346 | // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.\r | |
347 | //\r | |
a9292c13 | 348 | typedef struct _EVT_TRB_COMMAND_COMPLETION {\r |
92870c98 | 349 | UINT32 TRBPtrLo;\r |
a9292c13 | 350 | \r |
92870c98 | 351 | UINT32 TRBPtrHi;\r |
a9292c13 | 352 | \r |
92870c98 | 353 | UINT32 RsvdZ2:24;\r |
a9292c13 | 354 | UINT32 Completecode:8;\r |
355 | \r | |
92870c98 | 356 | UINT32 CycleBit:1;\r |
357 | UINT32 RsvdZ3:9;\r | |
358 | UINT32 Type:6;\r | |
359 | UINT32 VFID:8;\r | |
360 | UINT32 SlotId:8;\r | |
a9292c13 | 361 | } EVT_TRB_COMMAND_COMPLETION;\r |
362 | \r | |
363 | typedef union _TRB {\r | |
364 | TRB_TEMPLATE TrbTemplate;\r | |
365 | TRANSFER_TRB_NORMAL TrbNormal;\r | |
366 | TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;\r | |
367 | TRANSFER_TRB_CONTROL_DATA TrbCtrData;\r | |
368 | TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;\r | |
369 | } TRB;\r | |
92870c98 | 370 | \r |
371 | //\r | |
372 | // 6.4.3.1 No Op Command TRB\r | |
373 | // The No Op Command TRB provides a simple means for verifying the operation of the Command Ring\r | |
a9292c13 | 374 | // mechanisms offered by the xHCI.\r |
92870c98 | 375 | //\r |
376 | typedef struct _CMD_TRB_NO_OP {\r | |
377 | UINT32 RsvdZ0;\r | |
378 | UINT32 RsvdZ1;\r | |
379 | UINT32 RsvdZ2;\r | |
a9292c13 | 380 | \r |
92870c98 | 381 | UINT32 CycleBit:1;\r |
382 | UINT32 RsvdZ3:9;\r | |
383 | UINT32 Type:6;\r | |
384 | UINT32 RsvdZ4:16;\r | |
385 | } CMD_TRB_NO_OP;\r | |
386 | \r | |
387 | //\r | |
388 | // 6.4.3.2 Enable Slot Command TRB\r | |
389 | // The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the\r | |
390 | // selected slot to the host in a Command Completion Event.\r | |
391 | //\r | |
a9292c13 | 392 | typedef struct _CMD_TRB_ENABLE_SLOT {\r |
92870c98 | 393 | UINT32 RsvdZ0;\r |
394 | UINT32 RsvdZ1;\r | |
395 | UINT32 RsvdZ2;\r | |
a9292c13 | 396 | \r |
92870c98 | 397 | UINT32 CycleBit:1;\r |
398 | UINT32 RsvdZ3:9;\r | |
399 | UINT32 Type:6;\r | |
400 | UINT32 RsvdZ4:16;\r | |
a9292c13 | 401 | } CMD_TRB_ENABLE_SLOT;\r |
92870c98 | 402 | \r |
403 | //\r | |
404 | // 6.4.3.3 Disable Slot Command TRB\r | |
405 | // The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any\r | |
406 | // internal xHC resources assigned to the slot.\r | |
407 | //\r | |
a9292c13 | 408 | typedef struct _CMD_TRB_DISABLE_SLOT {\r |
92870c98 | 409 | UINT32 RsvdZ0;\r |
410 | UINT32 RsvdZ1;\r | |
411 | UINT32 RsvdZ2;\r | |
a9292c13 | 412 | \r |
92870c98 | 413 | UINT32 CycleBit:1;\r |
414 | UINT32 RsvdZ3:9;\r | |
415 | UINT32 Type:6;\r | |
416 | UINT32 RsvdZ4:8;\r | |
417 | UINT32 SlotId:8;\r | |
a9292c13 | 418 | } CMD_TRB_DISABLE_SLOT;\r |
92870c98 | 419 | \r |
420 | //\r | |
421 | // 6.4.3.4 Address Device Command TRB\r | |
422 | // The Address Device Command TRB transitions the selected Device Context from the Default to the\r | |
423 | // Addressed state and causes the xHC to select an address for the USB device in the Default State and\r | |
424 | // issue a SET_ADDRESS request to the USB device.\r | |
425 | //\r | |
a9292c13 | 426 | typedef struct _CMD_TRB_ADDRESS_DEVICE {\r |
92870c98 | 427 | UINT32 PtrLo;\r |
a9292c13 | 428 | \r |
92870c98 | 429 | UINT32 PtrHi;\r |
a9292c13 | 430 | \r |
92870c98 | 431 | UINT32 RsvdZ1;\r |
a9292c13 | 432 | \r |
92870c98 | 433 | UINT32 CycleBit:1;\r |
434 | UINT32 RsvdZ2:8;\r | |
435 | UINT32 BSR:1;\r | |
436 | UINT32 Type:6;\r | |
437 | UINT32 RsvdZ3:8;\r | |
438 | UINT32 SlotId:8;\r | |
a9292c13 | 439 | } CMD_TRB_ADDRESS_DEVICE;\r |
92870c98 | 440 | \r |
441 | //\r | |
442 | // 6.4.3.5 Configure Endpoint Command TRB\r | |
443 | // The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the\r | |
444 | // endpoints selected by the command.\r | |
445 | //\r | |
a9292c13 | 446 | typedef struct _CMD_TRB_CONFIG_ENDPOINT {\r |
92870c98 | 447 | UINT32 PtrLo;\r |
a9292c13 | 448 | \r |
92870c98 | 449 | UINT32 PtrHi;\r |
a9292c13 | 450 | \r |
92870c98 | 451 | UINT32 RsvdZ1;\r |
a9292c13 | 452 | \r |
92870c98 | 453 | UINT32 CycleBit:1;\r |
454 | UINT32 RsvdZ2:8;\r | |
455 | UINT32 DC:1;\r | |
456 | UINT32 Type:6;\r | |
457 | UINT32 RsvdZ3:8;\r | |
458 | UINT32 SlotId:8;\r | |
a9292c13 | 459 | } CMD_TRB_CONFIG_ENDPOINT;\r |
92870c98 | 460 | \r |
461 | //\r | |
462 | // 6.4.3.6 Evaluate Context Command TRB\r | |
463 | // The Evaluate Context Command TRB is used by system software to inform the xHC that the selected\r | |
464 | // Context data structures in the Device Context have been modified by system software and that the xHC\r | |
465 | // shall evaluate any changes\r | |
466 | //\r | |
a9292c13 | 467 | typedef struct _CMD_TRB_EVALUATE_CONTEXT {\r |
92870c98 | 468 | UINT32 PtrLo;\r |
a9292c13 | 469 | \r |
92870c98 | 470 | UINT32 PtrHi;\r |
a9292c13 | 471 | \r |
92870c98 | 472 | UINT32 RsvdZ1;\r |
a9292c13 | 473 | \r |
92870c98 | 474 | UINT32 CycleBit:1;\r |
475 | UINT32 RsvdZ2:9;\r | |
476 | UINT32 Type:6;\r | |
477 | UINT32 RsvdZ3:8;\r | |
478 | UINT32 SlotId:8;\r | |
a9292c13 | 479 | } CMD_TRB_EVALUATE_CONTEXT;\r |
92870c98 | 480 | \r |
481 | //\r | |
482 | // 6.4.3.7 Reset Endpoint Command TRB\r | |
483 | // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring\r | |
484 | //\r | |
a9292c13 | 485 | typedef struct _CMD_TRB_RESET_ENDPOINT {\r |
92870c98 | 486 | UINT32 RsvdZ0;\r |
487 | UINT32 RsvdZ1;\r | |
488 | UINT32 RsvdZ2;\r | |
a9292c13 | 489 | \r |
92870c98 | 490 | UINT32 CycleBit:1;\r |
491 | UINT32 RsvdZ3:8;\r | |
492 | UINT32 TSP:1;\r | |
493 | UINT32 Type:6;\r | |
494 | UINT32 EDID:5;\r | |
495 | UINT32 RsvdZ4:3;\r | |
496 | UINT32 SlotId:8;\r | |
a9292c13 | 497 | } CMD_TRB_RESET_ENDPOINT;\r |
92870c98 | 498 | \r |
499 | //\r | |
500 | // 6.4.3.8 Stop Endpoint Command TRB\r | |
501 | // The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a\r | |
502 | // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.\r | |
503 | //\r | |
a9292c13 | 504 | typedef struct _CMD_TRB_STOP_ENDPOINT {\r |
92870c98 | 505 | UINT32 RsvdZ0;\r |
506 | UINT32 RsvdZ1;\r | |
507 | UINT32 RsvdZ2;\r | |
a9292c13 | 508 | \r |
92870c98 | 509 | UINT32 CycleBit:1;\r |
510 | UINT32 RsvdZ3:9;\r | |
511 | UINT32 Type:6;\r | |
512 | UINT32 EDID:5;\r | |
513 | UINT32 RsvdZ4:2;\r | |
514 | UINT32 SP:1;\r | |
515 | UINT32 SlotId:8;\r | |
a9292c13 | 516 | } CMD_TRB_STOP_ENDPOINT;\r |
92870c98 | 517 | \r |
518 | //\r | |
519 | // 6.4.3.9 Set TR Dequeue Pointer Command TRB\r | |
520 | // The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue\r | |
521 | // Pointer and DCS fields of an Endpoint or Stream Context.\r | |
522 | //\r | |
a9292c13 | 523 | typedef struct _CMD_SET_TR_DEQ_POINTER {\r |
92870c98 | 524 | UINT32 PtrLo;\r |
a9292c13 | 525 | \r |
92870c98 | 526 | UINT32 PtrHi;\r |
a9292c13 | 527 | \r |
92870c98 | 528 | UINT32 RsvdZ1:16;\r |
529 | UINT32 StreamID:16;\r | |
a9292c13 | 530 | \r |
92870c98 | 531 | UINT32 CycleBit:1;\r |
532 | UINT32 RsvdZ2:9;\r | |
533 | UINT32 Type:6;\r | |
534 | UINT32 Endpoint:5;\r | |
535 | UINT32 RsvdZ3:3;\r | |
536 | UINT32 SlotId:8;\r | |
a9292c13 | 537 | } CMD_SET_TR_DEQ_POINTER;\r |
92870c98 | 538 | \r |
539 | //\r | |
a9292c13 | 540 | // 6.4.4.1 Link TRB\r |
92870c98 | 541 | // A Link TRB provides support for non-contiguous TRB Rings.\r |
542 | //\r | |
a9292c13 | 543 | typedef struct _LINK_TRB {\r |
92870c98 | 544 | UINT32 PtrLo;\r |
a9292c13 | 545 | \r |
92870c98 | 546 | UINT32 PtrHi;\r |
a9292c13 | 547 | \r |
92870c98 | 548 | UINT32 RsvdZ1:22;\r |
549 | UINT32 InterTarget:10;\r | |
a9292c13 | 550 | \r |
92870c98 | 551 | UINT32 CycleBit:1;\r |
552 | UINT32 TC:1;\r | |
553 | UINT32 RsvdZ2:2;\r | |
554 | UINT32 CH:1;\r | |
555 | UINT32 IOC:1;\r | |
556 | UINT32 RsvdZ3:4;\r | |
557 | UINT32 Type:6;\r | |
558 | UINT32 RsvdZ4:16;\r | |
a9292c13 | 559 | } LINK_TRB;\r |
92870c98 | 560 | \r |
561 | //\r | |
562 | // 6.2.2 Slot Context\r | |
563 | //\r | |
564 | typedef struct _SLOT_CONTEXT {\r | |
a9292c13 | 565 | UINT32 RouteString:20;\r |
92870c98 | 566 | UINT32 Speed:4;\r |
567 | UINT32 RsvdZ1:1;\r | |
568 | UINT32 MTT:1;\r | |
569 | UINT32 Hub:1;\r | |
570 | UINT32 ContextEntries:5;\r | |
571 | \r | |
572 | UINT32 MaxExitLatency:16;\r | |
573 | UINT32 RootHubPortNum:8;\r | |
574 | UINT32 PortNum:8;\r | |
575 | \r | |
576 | UINT32 TTHubSlotId:8;\r | |
577 | UINT32 TTPortNum:8;\r | |
578 | UINT32 TTT:2;\r | |
579 | UINT32 RsvdZ2:4;\r | |
580 | UINT32 InterTarget:10;\r | |
581 | \r | |
582 | UINT32 DeviceAddress:8;\r | |
583 | UINT32 RsvdZ3:19;\r | |
584 | UINT32 SlotState:5;\r | |
585 | \r | |
586 | UINT32 RsvdZ4;\r | |
587 | UINT32 RsvdZ5;\r | |
588 | UINT32 RsvdZ6;\r | |
589 | UINT32 RsvdZ7;\r | |
590 | } SLOT_CONTEXT;\r | |
591 | \r | |
6b4483cd | 592 | typedef struct _SLOT_CONTEXT_64 {\r |
593 | UINT32 RouteString:20;\r | |
594 | UINT32 Speed:4;\r | |
595 | UINT32 RsvdZ1:1;\r | |
596 | UINT32 MTT:1;\r | |
597 | UINT32 Hub:1;\r | |
598 | UINT32 ContextEntries:5;\r | |
599 | \r | |
600 | UINT32 MaxExitLatency:16;\r | |
601 | UINT32 RootHubPortNum:8;\r | |
602 | UINT32 PortNum:8;\r | |
603 | \r | |
604 | UINT32 TTHubSlotId:8;\r | |
605 | UINT32 TTPortNum:8;\r | |
606 | UINT32 TTT:2;\r | |
607 | UINT32 RsvdZ2:4;\r | |
608 | UINT32 InterTarget:10;\r | |
609 | \r | |
610 | UINT32 DeviceAddress:8;\r | |
611 | UINT32 RsvdZ3:19;\r | |
612 | UINT32 SlotState:5;\r | |
613 | \r | |
614 | UINT32 RsvdZ4;\r | |
615 | UINT32 RsvdZ5;\r | |
616 | UINT32 RsvdZ6;\r | |
617 | UINT32 RsvdZ7;\r | |
618 | \r | |
619 | UINT32 RsvdZ8;\r | |
620 | UINT32 RsvdZ9;\r | |
621 | UINT32 RsvdZ10;\r | |
622 | UINT32 RsvdZ11;\r | |
623 | \r | |
624 | UINT32 RsvdZ12;\r | |
625 | UINT32 RsvdZ13;\r | |
626 | UINT32 RsvdZ14;\r | |
627 | UINT32 RsvdZ15;\r | |
628 | \r | |
629 | } SLOT_CONTEXT_64;\r | |
630 | \r | |
631 | \r | |
92870c98 | 632 | //\r |
633 | // 6.2.3 Endpoint Context\r | |
634 | //\r | |
635 | typedef struct _ENDPOINT_CONTEXT {\r | |
636 | UINT32 EPState:3;\r | |
637 | UINT32 RsvdZ1:5;\r | |
638 | UINT32 Mult:2;\r | |
639 | UINT32 MaxPStreams:5;\r | |
640 | UINT32 LSA:1;\r | |
641 | UINT32 Interval:8;\r | |
642 | UINT32 RsvdZ2:8;\r | |
643 | \r | |
644 | UINT32 RsvdZ3:1;\r | |
645 | UINT32 CErr:2;\r | |
646 | UINT32 EPType:3;\r | |
647 | UINT32 RsvdZ4:1;\r | |
648 | UINT32 HID:1;\r | |
649 | UINT32 MaxBurstSize:8;\r | |
650 | UINT32 MaxPacketSize:16;\r | |
651 | \r | |
652 | UINT32 PtrLo;\r | |
653 | \r | |
654 | UINT32 PtrHi;\r | |
655 | \r | |
656 | UINT32 AverageTRBLength:16;\r | |
657 | UINT32 MaxESITPayload:16;\r | |
658 | \r | |
659 | UINT32 RsvdZ5;\r | |
660 | UINT32 RsvdZ6;\r | |
661 | UINT32 RsvdZ7;\r | |
662 | } ENDPOINT_CONTEXT;\r | |
663 | \r | |
6b4483cd | 664 | typedef struct _ENDPOINT_CONTEXT_64 {\r |
665 | UINT32 EPState:3;\r | |
666 | UINT32 RsvdZ1:5;\r | |
667 | UINT32 Mult:2;\r | |
668 | UINT32 MaxPStreams:5;\r | |
669 | UINT32 LSA:1;\r | |
670 | UINT32 Interval:8;\r | |
671 | UINT32 RsvdZ2:8;\r | |
672 | \r | |
673 | UINT32 RsvdZ3:1;\r | |
674 | UINT32 CErr:2;\r | |
675 | UINT32 EPType:3;\r | |
676 | UINT32 RsvdZ4:1;\r | |
677 | UINT32 HID:1;\r | |
678 | UINT32 MaxBurstSize:8;\r | |
679 | UINT32 MaxPacketSize:16;\r | |
680 | \r | |
681 | UINT32 PtrLo;\r | |
682 | \r | |
683 | UINT32 PtrHi;\r | |
684 | \r | |
685 | UINT32 AverageTRBLength:16;\r | |
686 | UINT32 MaxESITPayload:16;\r | |
687 | \r | |
688 | UINT32 RsvdZ5;\r | |
689 | UINT32 RsvdZ6;\r | |
690 | UINT32 RsvdZ7;\r | |
691 | \r | |
692 | UINT32 RsvdZ8;\r | |
693 | UINT32 RsvdZ9;\r | |
694 | UINT32 RsvdZ10;\r | |
695 | UINT32 RsvdZ11;\r | |
696 | \r | |
697 | UINT32 RsvdZ12;\r | |
698 | UINT32 RsvdZ13;\r | |
699 | UINT32 RsvdZ14;\r | |
700 | UINT32 RsvdZ15;\r | |
701 | \r | |
702 | } ENDPOINT_CONTEXT_64;\r | |
703 | \r | |
704 | \r | |
92870c98 | 705 | //\r |
706 | // 6.2.5.1 Input Control Context\r | |
707 | //\r | |
708 | typedef struct _INPUT_CONTRL_CONTEXT {\r | |
709 | UINT32 Dword1;\r | |
710 | UINT32 Dword2;\r | |
711 | UINT32 RsvdZ1;\r | |
712 | UINT32 RsvdZ2;\r | |
713 | UINT32 RsvdZ3;\r | |
714 | UINT32 RsvdZ4;\r | |
715 | UINT32 RsvdZ5;\r | |
716 | UINT32 RsvdZ6;\r | |
717 | } INPUT_CONTRL_CONTEXT;\r | |
718 | \r | |
6b4483cd | 719 | typedef struct _INPUT_CONTRL_CONTEXT_64 {\r |
720 | UINT32 Dword1;\r | |
721 | UINT32 Dword2;\r | |
722 | UINT32 RsvdZ1;\r | |
723 | UINT32 RsvdZ2;\r | |
724 | UINT32 RsvdZ3;\r | |
725 | UINT32 RsvdZ4;\r | |
726 | UINT32 RsvdZ5;\r | |
727 | UINT32 RsvdZ6;\r | |
728 | UINT32 RsvdZ7;\r | |
729 | UINT32 RsvdZ8;\r | |
730 | UINT32 RsvdZ9;\r | |
731 | UINT32 RsvdZ10;\r | |
732 | UINT32 RsvdZ11;\r | |
733 | UINT32 RsvdZ12;\r | |
734 | UINT32 RsvdZ13;\r | |
735 | UINT32 RsvdZ14;\r | |
736 | } INPUT_CONTRL_CONTEXT_64;\r | |
737 | \r | |
92870c98 | 738 | //\r |
739 | // 6.2.1 Device Context\r | |
740 | //\r | |
741 | typedef struct _DEVICE_CONTEXT {\r | |
742 | SLOT_CONTEXT Slot;\r | |
743 | ENDPOINT_CONTEXT EP[31];\r | |
744 | } DEVICE_CONTEXT;\r | |
745 | \r | |
6b4483cd | 746 | typedef struct _DEVICE_CONTEXT_64 {\r |
747 | SLOT_CONTEXT_64 Slot;\r | |
748 | ENDPOINT_CONTEXT_64 EP[31];\r | |
749 | } DEVICE_CONTEXT_64;\r | |
750 | \r | |
92870c98 | 751 | //\r |
752 | // 6.2.5 Input Context\r | |
753 | //\r | |
754 | typedef struct _INPUT_CONTEXT {\r | |
755 | INPUT_CONTRL_CONTEXT InputControlContext;\r | |
756 | SLOT_CONTEXT Slot;\r | |
757 | ENDPOINT_CONTEXT EP[31];\r | |
758 | } INPUT_CONTEXT;\r | |
759 | \r | |
6b4483cd | 760 | typedef struct _INPUT_CONTEXT_64 {\r |
761 | INPUT_CONTRL_CONTEXT_64 InputControlContext;\r | |
762 | SLOT_CONTEXT_64 Slot;\r | |
763 | ENDPOINT_CONTEXT_64 EP[31];\r | |
764 | } INPUT_CONTEXT_64;\r | |
765 | \r | |
766 | \r | |
92870c98 | 767 | /**\r |
768 | Initialize the XHCI host controller for schedule.\r | |
769 | \r | |
a9292c13 | 770 | @param Xhc The XHCI Instance to be initialized.\r |
92870c98 | 771 | \r |
772 | **/\r | |
773 | VOID\r | |
774 | XhcInitSched (\r | |
a9292c13 | 775 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 776 | );\r |
777 | \r | |
778 | /**\r | |
779 | Free the resouce allocated at initializing schedule.\r | |
780 | \r | |
a9292c13 | 781 | @param Xhc The XHCI Instance.\r |
92870c98 | 782 | \r |
783 | **/\r | |
784 | VOID\r | |
785 | XhcFreeSched (\r | |
a9292c13 | 786 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 787 | );\r |
788 | \r | |
789 | /**\r | |
790 | Ring the door bell to notify XHCI there is a transaction to be executed through URB.\r | |
791 | \r | |
a9292c13 | 792 | @param Xhc The XHCI Instance.\r |
92870c98 | 793 | @param Urb The URB to be rung.\r |
794 | \r | |
795 | @retval EFI_SUCCESS Successfully ring the door bell.\r | |
796 | \r | |
797 | **/\r | |
798 | EFI_STATUS\r | |
799 | RingIntTransferDoorBell (\r | |
a9292c13 | 800 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 801 | IN URB *Urb\r |
802 | );\r | |
803 | \r | |
804 | /**\r | |
805 | Execute the transfer by polling the URB. This is a synchronous operation.\r | |
806 | \r | |
a9292c13 | 807 | @param Xhc The XHCI Instance.\r |
92870c98 | 808 | @param CmdTransfer The executed URB is for cmd transfer or not.\r |
809 | @param Urb The URB to execute.\r | |
a9292c13 | 810 | @param Timeout The time to wait before abort, in millisecond.\r |
92870c98 | 811 | \r |
812 | @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r | |
813 | @return EFI_TIMEOUT The transfer failed due to time out.\r | |
814 | @return EFI_SUCCESS The transfer finished OK.\r | |
815 | \r | |
816 | **/\r | |
817 | EFI_STATUS\r | |
818 | XhcExecTransfer (\r | |
a9292c13 | 819 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 820 | IN BOOLEAN CmdTransfer,\r |
821 | IN URB *Urb,\r | |
a9292c13 | 822 | IN UINTN Timeout\r |
92870c98 | 823 | );\r |
824 | \r | |
825 | /**\r | |
826 | Delete a single asynchronous interrupt transfer for\r | |
827 | the device and endpoint.\r | |
828 | \r | |
a9292c13 | 829 | @param Xhc The XHCI Instance.\r |
6b4483cd | 830 | @param BusAddr The logical device address assigned by UsbBus driver.\r |
92870c98 | 831 | @param EpNum The endpoint of the target.\r |
832 | \r | |
833 | @retval EFI_SUCCESS An asynchronous transfer is removed.\r | |
834 | @retval EFI_NOT_FOUND No transfer for the device is found.\r | |
835 | \r | |
836 | **/\r | |
837 | EFI_STATUS\r | |
838 | XhciDelAsyncIntTransfer (\r | |
a9292c13 | 839 | IN USB_XHCI_INSTANCE *Xhc,\r |
6b4483cd | 840 | IN UINT8 BusAddr,\r |
92870c98 | 841 | IN UINT8 EpNum\r |
842 | );\r | |
843 | \r | |
844 | /**\r | |
845 | Remove all the asynchronous interrupt transfers.\r | |
846 | \r | |
a9292c13 | 847 | @param Xhc The XHCI Instance.\r |
92870c98 | 848 | \r |
849 | **/\r | |
850 | VOID\r | |
851 | XhciDelAllAsyncIntTransfers (\r | |
a9292c13 | 852 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 853 | );\r |
854 | \r | |
855 | /**\r | |
856 | Set Bios Ownership\r | |
857 | \r | |
a9292c13 | 858 | @param Xhc The XHCI Instance.\r |
92870c98 | 859 | \r |
860 | **/\r | |
861 | VOID\r | |
862 | XhcSetBiosOwnership (\r | |
a9292c13 | 863 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 864 | );\r |
865 | \r | |
866 | /**\r | |
867 | Clear Bios Ownership\r | |
868 | \r | |
a9292c13 | 869 | @param Xhc The XHCI Instance.\r |
92870c98 | 870 | \r |
871 | **/\r | |
872 | VOID\r | |
873 | XhcClearBiosOwnership (\r | |
a9292c13 | 874 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 875 | );\r |
876 | \r | |
92870c98 | 877 | /**\r |
878 | Find out the slot id according to the device's route string.\r | |
879 | \r | |
a9292c13 | 880 | @param Xhc The XHCI Instance.\r |
881 | @param RouteString The route string described the device location.\r | |
92870c98 | 882 | \r |
883 | @return The slot id used by the device.\r | |
884 | \r | |
885 | **/\r | |
886 | UINT8\r | |
887 | EFIAPI\r | |
888 | XhcRouteStringToSlotId (\r | |
a9292c13 | 889 | IN USB_XHCI_INSTANCE *Xhc,\r |
890 | IN USB_DEV_ROUTE RouteString\r | |
92870c98 | 891 | );\r |
892 | \r | |
893 | /**\r | |
894 | Calculate the device context index by endpoint address and direction.\r | |
895 | \r | |
896 | @param EpAddr The target endpoint number.\r | |
897 | @param Direction The direction of the target endpoint.\r | |
898 | \r | |
899 | @return The device context index of endpoint.\r | |
900 | \r | |
901 | **/\r | |
902 | UINT8\r | |
903 | XhcEndpointToDci (\r | |
904 | IN UINT8 EpAddr,\r | |
905 | IN UINT8 Direction\r | |
906 | );\r | |
907 | \r | |
908 | /**\r | |
909 | Ring the door bell to notify XHCI there is a transaction to be executed.\r | |
910 | \r | |
a9292c13 | 911 | @param Xhc The XHCI Instance.\r |
92870c98 | 912 | @param SlotId The slot id of the target device.\r |
913 | @param Dci The device context index of the target slot or endpoint.\r | |
914 | \r | |
915 | @retval EFI_SUCCESS Successfully ring the door bell.\r | |
916 | \r | |
917 | **/\r | |
918 | EFI_STATUS\r | |
919 | EFIAPI\r | |
920 | XhcRingDoorBell (\r | |
a9292c13 | 921 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 922 | IN UINT8 SlotId,\r |
923 | IN UINT8 Dci\r | |
924 | );\r | |
925 | \r | |
926 | /**\r | |
927 | Interrupt transfer periodic check handler.\r | |
928 | \r | |
929 | @param Event Interrupt event.\r | |
a9292c13 | 930 | @param Context Pointer to USB_XHCI_INSTANCE.\r |
92870c98 | 931 | \r |
932 | **/\r | |
933 | VOID\r | |
934 | EFIAPI\r | |
935 | XhcMonitorAsyncRequests (\r | |
936 | IN EFI_EVENT Event,\r | |
937 | IN VOID *Context\r | |
938 | );\r | |
939 | \r | |
940 | /**\r | |
941 | Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.\r | |
942 | \r | |
a9292c13 | 943 | @param Xhc The XHCI Instance.\r |
92870c98 | 944 | @param ParentRouteChart The route string pointed to the parent device if it exists.\r |
945 | @param Port The port to be polled.\r | |
946 | @param PortState The port state.\r | |
947 | \r | |
948 | @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.\r | |
949 | @retval Others Should not appear.\r | |
950 | \r | |
951 | **/\r | |
952 | EFI_STATUS\r | |
953 | EFIAPI\r | |
954 | XhcPollPortStatusChange (\r | |
a9292c13 | 955 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 956 | IN USB_DEV_ROUTE ParentRouteChart,\r |
957 | IN UINT8 Port,\r | |
958 | IN EFI_USB_PORT_STATUS *PortState\r | |
959 | );\r | |
960 | \r | |
961 | /**\r | |
962 | Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r | |
963 | \r | |
a9292c13 | 964 | @param Xhc The XHCI Instance.\r |
92870c98 | 965 | @param SlotId The slot id to be configured.\r |
966 | @param PortNum The total number of downstream port supported by the hub.\r | |
967 | @param TTT The TT think time of the hub device.\r | |
968 | @param MTT The multi-TT of the hub device.\r | |
969 | \r | |
970 | @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r | |
971 | \r | |
972 | **/\r | |
973 | EFI_STATUS\r | |
974 | XhcConfigHubContext (\r | |
a9292c13 | 975 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 976 | IN UINT8 SlotId,\r |
977 | IN UINT8 PortNum,\r | |
978 | IN UINT8 TTT,\r | |
979 | IN UINT8 MTT\r | |
980 | );\r | |
981 | \r | |
6b4483cd | 982 | \r |
983 | /**\r | |
984 | Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r | |
985 | \r | |
986 | @param Xhc The XHCI Instance.\r | |
987 | @param SlotId The slot id to be configured.\r | |
988 | @param PortNum The total number of downstream port supported by the hub.\r | |
989 | @param TTT The TT think time of the hub device.\r | |
990 | @param MTT The multi-TT of the hub device.\r | |
991 | \r | |
992 | @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r | |
993 | \r | |
994 | **/\r | |
995 | EFI_STATUS\r | |
996 | XhcConfigHubContext64 (\r | |
997 | IN USB_XHCI_INSTANCE *Xhc,\r | |
998 | IN UINT8 SlotId,\r | |
999 | IN UINT8 PortNum,\r | |
1000 | IN UINT8 TTT,\r | |
1001 | IN UINT8 MTT\r | |
1002 | );\r | |
1003 | \r | |
1004 | \r | |
92870c98 | 1005 | /**\r |
1006 | Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r | |
1007 | \r | |
a9292c13 | 1008 | @param Xhc The XHCI Instance.\r |
92870c98 | 1009 | @param SlotId The slot id to be configured.\r |
1010 | @param DeviceSpeed The device's speed.\r | |
1011 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
1012 | \r | |
1013 | @retval EFI_SUCCESS Successfully configure all the device endpoints.\r | |
1014 | \r | |
1015 | **/\r | |
1016 | EFI_STATUS\r | |
1017 | EFIAPI\r | |
1018 | XhcSetConfigCmd (\r | |
a9292c13 | 1019 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1020 | IN UINT8 SlotId,\r |
1021 | IN UINT8 DeviceSpeed,\r | |
1022 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r | |
1023 | );\r | |
1024 | \r | |
6b4483cd | 1025 | \r |
1026 | /**\r | |
1027 | Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r | |
1028 | \r | |
1029 | @param Xhc The XHCI Instance.\r | |
1030 | @param SlotId The slot id to be configured.\r | |
1031 | @param DeviceSpeed The device's speed.\r | |
1032 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
1033 | \r | |
1034 | @retval EFI_SUCCESS Successfully configure all the device endpoints.\r | |
1035 | \r | |
1036 | **/\r | |
1037 | EFI_STATUS\r | |
1038 | EFIAPI\r | |
1039 | XhcSetConfigCmd64 (\r | |
1040 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1041 | IN UINT8 SlotId,\r | |
1042 | IN UINT8 DeviceSpeed,\r | |
1043 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r | |
1044 | );\r | |
1045 | \r | |
e1f2dfec SZ |
1046 | /**\r |
1047 | Set interface through XHCI's Configure_Endpoint cmd.\r | |
1048 | \r | |
1049 | @param Xhc The XHCI Instance.\r | |
1050 | @param SlotId The slot id to be configured.\r | |
1051 | @param DeviceSpeed The device's speed.\r | |
1052 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
1053 | @param Request USB device request to send.\r | |
1054 | \r | |
1055 | @retval EFI_SUCCESS Successfully set interface.\r | |
1056 | \r | |
1057 | **/\r | |
1058 | EFI_STATUS\r | |
1059 | EFIAPI\r | |
1060 | XhcSetInterface (\r | |
1061 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1062 | IN UINT8 SlotId,\r | |
1063 | IN UINT8 DeviceSpeed,\r | |
1064 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r | |
1065 | IN EFI_USB_DEVICE_REQUEST *Request\r | |
1066 | );\r | |
1067 | \r | |
1068 | /**\r | |
1069 | Set interface through XHCI's Configure_Endpoint cmd.\r | |
1070 | \r | |
1071 | @param Xhc The XHCI Instance.\r | |
1072 | @param SlotId The slot id to be configured.\r | |
1073 | @param DeviceSpeed The device's speed.\r | |
1074 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
1075 | @param Request USB device request to send.\r | |
1076 | \r | |
1077 | @retval EFI_SUCCESS Successfully set interface.\r | |
1078 | \r | |
1079 | **/\r | |
1080 | EFI_STATUS\r | |
1081 | EFIAPI\r | |
1082 | XhcSetInterface64 (\r | |
1083 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1084 | IN UINT8 SlotId,\r | |
1085 | IN UINT8 DeviceSpeed,\r | |
1086 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r | |
1087 | IN EFI_USB_DEVICE_REQUEST *Request\r | |
1088 | );\r | |
6b4483cd | 1089 | \r |
92870c98 | 1090 | /**\r |
1091 | Find out the actual device address according to the requested device address from UsbBus.\r | |
1092 | \r | |
a9292c13 | 1093 | @param Xhc The XHCI Instance.\r |
1094 | @param BusDevAddr The requested device address by UsbBus upper driver.\r | |
92870c98 | 1095 | \r |
1096 | @return The actual device address assigned to the device.\r | |
1097 | \r | |
1098 | **/\r | |
1099 | UINT8\r | |
1100 | EFIAPI\r | |
1101 | XhcBusDevAddrToSlotId (\r | |
a9292c13 | 1102 | IN USB_XHCI_INSTANCE *Xhc,\r |
1103 | IN UINT8 BusDevAddr\r | |
92870c98 | 1104 | );\r |
1105 | \r | |
1106 | /**\r | |
1107 | Assign and initialize the device slot for a new device.\r | |
1108 | \r | |
a9292c13 | 1109 | @param Xhc The XHCI Instance.\r |
92870c98 | 1110 | @param ParentRouteChart The route string pointed to the parent device.\r |
1111 | @param ParentPort The port at which the device is located.\r | |
1112 | @param RouteChart The route string pointed to the device.\r | |
1113 | @param DeviceSpeed The device speed.\r | |
1114 | \r | |
1115 | @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r | |
1116 | \r | |
1117 | **/\r | |
1118 | EFI_STATUS\r | |
1119 | EFIAPI\r | |
1120 | XhcInitializeDeviceSlot (\r | |
a9292c13 | 1121 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1122 | IN USB_DEV_ROUTE ParentRouteChart,\r |
1123 | IN UINT16 ParentPort,\r | |
1124 | IN USB_DEV_ROUTE RouteChart,\r | |
1125 | IN UINT8 DeviceSpeed\r | |
1126 | );\r | |
1127 | \r | |
6b4483cd | 1128 | /**\r |
1129 | Assign and initialize the device slot for a new device.\r | |
1130 | \r | |
1131 | @param Xhc The XHCI Instance.\r | |
1132 | @param ParentRouteChart The route string pointed to the parent device.\r | |
1133 | @param ParentPort The port at which the device is located.\r | |
1134 | @param RouteChart The route string pointed to the device.\r | |
1135 | @param DeviceSpeed The device speed.\r | |
1136 | \r | |
1137 | @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r | |
1138 | \r | |
1139 | **/\r | |
1140 | EFI_STATUS\r | |
1141 | EFIAPI\r | |
1142 | XhcInitializeDeviceSlot64 (\r | |
1143 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1144 | IN USB_DEV_ROUTE ParentRouteChart,\r | |
1145 | IN UINT16 ParentPort,\r | |
1146 | IN USB_DEV_ROUTE RouteChart,\r | |
1147 | IN UINT8 DeviceSpeed\r | |
1148 | );\r | |
1149 | \r | |
92870c98 | 1150 | /**\r |
1151 | Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r | |
1152 | \r | |
a9292c13 | 1153 | @param Xhc The XHCI Instance.\r |
92870c98 | 1154 | @param SlotId The slot id to be evaluated.\r |
1155 | @param MaxPacketSize The max packet size supported by the device control transfer.\r | |
1156 | \r | |
1157 | @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r | |
1158 | \r | |
1159 | **/\r | |
1160 | EFI_STATUS\r | |
1161 | EFIAPI\r | |
1162 | XhcEvaluateContext (\r | |
a9292c13 | 1163 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1164 | IN UINT8 SlotId,\r |
1165 | IN UINT32 MaxPacketSize\r | |
1166 | );\r | |
1167 | \r | |
6b4483cd | 1168 | \r |
1169 | /**\r | |
1170 | Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r | |
1171 | \r | |
1172 | @param Xhc The XHCI Instance.\r | |
1173 | @param SlotId The slot id to be evaluated.\r | |
1174 | @param MaxPacketSize The max packet size supported by the device control transfer.\r | |
1175 | \r | |
1176 | @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r | |
1177 | \r | |
1178 | **/\r | |
1179 | EFI_STATUS\r | |
1180 | EFIAPI\r | |
1181 | XhcEvaluateContext64 (\r | |
1182 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1183 | IN UINT8 SlotId,\r | |
1184 | IN UINT32 MaxPacketSize\r | |
1185 | );\r | |
1186 | \r | |
1187 | \r | |
92870c98 | 1188 | /**\r |
1189 | Disable the specified device slot.\r | |
1190 | \r | |
a9292c13 | 1191 | @param Xhc The XHCI Instance.\r |
92870c98 | 1192 | @param SlotId The slot id to be disabled.\r |
1193 | \r | |
1194 | @retval EFI_SUCCESS Successfully disable the device slot.\r | |
1195 | \r | |
1196 | **/\r | |
1197 | EFI_STATUS\r | |
1198 | EFIAPI\r | |
1199 | XhcDisableSlotCmd (\r | |
a9292c13 | 1200 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1201 | IN UINT8 SlotId\r |
1202 | );\r | |
1203 | \r | |
6b4483cd | 1204 | \r |
1205 | /**\r | |
1206 | Disable the specified device slot.\r | |
1207 | \r | |
1208 | @param Xhc The XHCI Instance.\r | |
1209 | @param SlotId The slot id to be disabled.\r | |
1210 | \r | |
1211 | @retval EFI_SUCCESS Successfully disable the device slot.\r | |
1212 | \r | |
1213 | **/\r | |
1214 | EFI_STATUS\r | |
1215 | EFIAPI\r | |
1216 | XhcDisableSlotCmd64 (\r | |
1217 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1218 | IN UINT8 SlotId\r | |
1219 | );\r | |
1220 | \r | |
1221 | \r | |
92870c98 | 1222 | /**\r |
1223 | Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r | |
1224 | \r | |
a9292c13 | 1225 | @param Xhc The XHCI Instance.\r |
92870c98 | 1226 | @param TrsRing The transfer ring to sync.\r |
1227 | \r | |
1228 | @retval EFI_SUCCESS The transfer ring is synchronized successfully.\r | |
1229 | \r | |
1230 | **/\r | |
1231 | EFI_STATUS\r | |
1232 | EFIAPI\r | |
1233 | XhcSyncTrsRing (\r | |
a9292c13 | 1234 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1235 | TRANSFER_RING *TrsRing\r |
1236 | );\r | |
1237 | \r | |
1238 | /**\r | |
1239 | Synchronize the specified event ring to update the enqueue and dequeue pointer.\r | |
1240 | \r | |
a9292c13 | 1241 | @param Xhc The XHCI Instance.\r |
92870c98 | 1242 | @param EvtRing The event ring to sync.\r |
1243 | \r | |
1244 | @retval EFI_SUCCESS The event ring is synchronized successfully.\r | |
1245 | \r | |
1246 | **/\r | |
1247 | EFI_STATUS\r | |
1248 | EFIAPI\r | |
1249 | XhcSyncEventRing (\r | |
a9292c13 | 1250 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1251 | EVENT_RING *EvtRing\r |
1252 | );\r | |
1253 | \r | |
1254 | /**\r | |
1255 | Check if there is a new generated event.\r | |
1256 | \r | |
a9292c13 | 1257 | @param Xhc The XHCI Instance.\r |
92870c98 | 1258 | @param EvtRing The event ring to check.\r |
1259 | @param NewEvtTrb The new event TRB found.\r | |
1260 | \r | |
1261 | @retval EFI_SUCCESS Found a new event TRB at the event ring.\r | |
1262 | @retval EFI_NOT_READY The event ring has no new event.\r | |
1263 | \r | |
1264 | **/\r | |
1265 | EFI_STATUS\r | |
1266 | EFIAPI\r | |
1267 | XhcCheckNewEvent (\r | |
a9292c13 | 1268 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1269 | IN EVENT_RING *EvtRing,\r |
a9292c13 | 1270 | OUT TRB_TEMPLATE **NewEvtTrb\r |
92870c98 | 1271 | );\r |
1272 | \r | |
1273 | /**\r | |
1274 | Create XHCI transfer ring.\r | |
1275 | \r | |
a9292c13 | 1276 | @param Xhc The XHCI Instance.\r |
92870c98 | 1277 | @param TrbNum The number of TRB in the ring.\r |
1278 | @param TransferRing The created transfer ring.\r | |
1279 | \r | |
1280 | **/\r | |
1281 | VOID\r | |
1282 | CreateTransferRing (\r | |
a9292c13 | 1283 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1284 | IN UINTN TrbNum,\r |
1285 | OUT TRANSFER_RING *TransferRing\r | |
1286 | );\r | |
1287 | \r | |
1288 | /**\r | |
1289 | Create XHCI event ring.\r | |
1290 | \r | |
a9292c13 | 1291 | @param Xhc The XHCI Instance.\r |
92870c98 | 1292 | @param EventRing The created event ring.\r |
1293 | \r | |
1294 | **/\r | |
1295 | VOID\r | |
1296 | CreateEventRing (\r | |
a9292c13 | 1297 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1298 | OUT EVENT_RING *EventRing\r |
1299 | );\r | |
1300 | \r | |
1301 | /**\r | |
1302 | System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted\r | |
1303 | condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint\r | |
1304 | Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is\r | |
1305 | reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the\r | |
1306 | Stopped to the Running state.\r | |
1307 | \r | |
a9292c13 | 1308 | @param Xhc The XHCI Instance.\r |
92870c98 | 1309 | @param Urb The urb which makes the endpoint halted.\r |
1310 | \r | |
1311 | @retval EFI_SUCCESS The recovery is successful.\r | |
1312 | @retval Others Failed to recovery halted endpoint.\r | |
1313 | \r | |
1314 | **/\r | |
1315 | EFI_STATUS\r | |
1316 | EFIAPI\r | |
1317 | XhcRecoverHaltedEndpoint (\r | |
a9292c13 | 1318 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1319 | IN URB *Urb\r |
1320 | );\r | |
1321 | \r | |
12e6c738 FT |
1322 | /**\r |
1323 | System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer\r | |
1324 | Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to\r | |
1325 | the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running\r | |
1326 | state.\r | |
1327 | \r | |
1328 | @param Xhc The XHCI Instance.\r | |
1329 | @param Urb The urb which doesn't get completed in a specified timeout range.\r | |
1330 | \r | |
1331 | @retval EFI_SUCCESS The dequeuing of the TDs is successful.\r | |
1332 | @retval Others Failed to stop the endpoint and dequeue the TDs.\r | |
1333 | \r | |
1334 | **/\r | |
1335 | EFI_STATUS\r | |
1336 | EFIAPI\r | |
1337 | XhcDequeueTrbFromEndpoint (\r | |
1338 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1339 | IN URB *Urb\r | |
1340 | );\r | |
1341 | \r | |
1342 | /**\r | |
1343 | Stop endpoint through XHCI's Stop_Endpoint cmd.\r | |
1344 | \r | |
1345 | @param Xhc The XHCI Instance.\r | |
1346 | @param SlotId The slot id to be configured.\r | |
1347 | @param Dci The device context index of endpoint.\r | |
49be9c3c | 1348 | @param PendingUrb The pending URB to check completion status when stopping the end point.\r |
12e6c738 FT |
1349 | \r |
1350 | @retval EFI_SUCCESS Stop endpoint successfully.\r | |
1351 | @retval Others Failed to stop endpoint.\r | |
1352 | \r | |
1353 | **/\r | |
1354 | EFI_STATUS\r | |
1355 | EFIAPI\r | |
1356 | XhcStopEndpoint (\r | |
1357 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1358 | IN UINT8 SlotId,\r | |
49be9c3c RN |
1359 | IN UINT8 Dci,\r |
1360 | IN URB *PendingUrb OPTIONAL\r | |
12e6c738 FT |
1361 | );\r |
1362 | \r | |
1363 | /**\r | |
1364 | Reset endpoint through XHCI's Reset_Endpoint cmd.\r | |
1365 | \r | |
1366 | @param Xhc The XHCI Instance.\r | |
1367 | @param SlotId The slot id to be configured.\r | |
1368 | @param Dci The device context index of endpoint.\r | |
1369 | \r | |
1370 | @retval EFI_SUCCESS Reset endpoint successfully.\r | |
1371 | @retval Others Failed to reset endpoint.\r | |
1372 | \r | |
1373 | **/\r | |
1374 | EFI_STATUS\r | |
1375 | EFIAPI\r | |
1376 | XhcResetEndpoint (\r | |
1377 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1378 | IN UINT8 SlotId,\r | |
1379 | IN UINT8 Dci\r | |
1380 | );\r | |
1381 | \r | |
1382 | /**\r | |
1383 | Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.\r | |
1384 | \r | |
1385 | @param Xhc The XHCI Instance.\r | |
1386 | @param SlotId The slot id to be configured.\r | |
1387 | @param Dci The device context index of endpoint.\r | |
1388 | @param Urb The dequeue pointer of the transfer ring specified\r | |
1389 | by the urb to be updated.\r | |
1390 | \r | |
1391 | @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.\r | |
1392 | @retval Others Failed to set transfer ring dequeue pointer.\r | |
1393 | \r | |
1394 | **/\r | |
1395 | EFI_STATUS\r | |
1396 | EFIAPI\r | |
1397 | XhcSetTrDequeuePointer (\r | |
1398 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1399 | IN UINT8 SlotId,\r | |
1400 | IN UINT8 Dci,\r | |
1401 | IN URB *Urb\r | |
1402 | );\r | |
1403 | \r | |
92870c98 | 1404 | /**\r |
1405 | Create a new URB for a new transaction.\r | |
1406 | \r | |
a9292c13 | 1407 | @param Xhc The XHCI Instance\r |
92870c98 | 1408 | @param DevAddr The device address\r |
1409 | @param EpAddr Endpoint addrress\r | |
1410 | @param DevSpeed The device speed\r | |
1411 | @param MaxPacket The max packet length of the endpoint\r | |
1412 | @param Type The transaction type\r | |
1413 | @param Request The standard USB request for control transfer\r | |
1414 | @param Data The user data to transfer\r | |
1415 | @param DataLen The length of data buffer\r | |
1416 | @param Callback The function to call when data is transferred\r | |
1417 | @param Context The context to the callback\r | |
1418 | \r | |
1419 | @return Created URB or NULL\r | |
1420 | \r | |
1421 | **/\r | |
1422 | URB*\r | |
1423 | XhcCreateUrb (\r | |
a9292c13 | 1424 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1425 | IN UINT8 DevAddr,\r |
1426 | IN UINT8 EpAddr,\r | |
1427 | IN UINT8 DevSpeed,\r | |
1428 | IN UINTN MaxPacket,\r | |
1429 | IN UINTN Type,\r | |
1430 | IN EFI_USB_DEVICE_REQUEST *Request,\r | |
1431 | IN VOID *Data,\r | |
1432 | IN UINTN DataLen,\r | |
1433 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r | |
1434 | IN VOID *Context\r | |
1435 | );\r | |
1436 | \r | |
1847ed0b EL |
1437 | /**\r |
1438 | Free an allocated URB.\r | |
1439 | \r | |
1440 | @param Xhc The XHCI device.\r | |
1441 | @param Urb The URB to free.\r | |
1442 | \r | |
1443 | **/\r | |
1444 | VOID\r | |
1445 | XhcFreeUrb (\r | |
1446 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1447 | IN URB *Urb\r | |
1448 | );\r | |
1449 | \r | |
92870c98 | 1450 | /**\r |
1451 | Create a transfer TRB.\r | |
1452 | \r | |
a9292c13 | 1453 | @param Xhc The XHCI Instance\r |
92870c98 | 1454 | @param Urb The urb used to construct the transfer TRB.\r |
1455 | \r | |
1456 | @return Created TRB or NULL\r | |
1457 | \r | |
1458 | **/\r | |
1459 | EFI_STATUS\r | |
1460 | XhcCreateTransferTrb (\r | |
a9292c13 | 1461 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1462 | IN URB *Urb\r |
1463 | );\r | |
1464 | \r | |
1465 | #endif\r |