Fix CrytoPkg issue in GCC X64 tip.
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.h
CommitLineData
92870c98 1/** @file\r
2\r
3 This file contains the definition for XHCI host controller schedule routines.\r
4\r
5Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r
6This program and the accompanying materials\r
7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#ifndef _EFI_XHCI_SCHED_H_\r
17#define _EFI_XHCI_SCHED_H_\r
18\r
19#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')\r
20\r
21//\r
22// Transfer types, used in URB to identify the transfer type\r
23//\r
24#define XHC_CTRL_TRANSFER 0x01\r
25#define XHC_BULK_TRANSFER 0x02\r
26#define XHC_INT_TRANSFER_SYNC 0x04\r
27#define XHC_INT_TRANSFER_ASYNC 0x08\r
28#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r
29\r
30//\r
31// 6.4.6 TRB Types\r
32//\r
33#define TRB_TYPE_NORMAL 1\r
34#define TRB_TYPE_SETUP_STAGE 2\r
35#define TRB_TYPE_DATA_STAGE 3\r
36#define TRB_TYPE_STATUS_STAGE 4\r
37#define TRB_TYPE_ISOCH 5\r
38#define TRB_TYPE_LINK 6\r
39#define TRB_TYPE_EVENT_DATA 7\r
40#define TRB_TYPE_NO_OP 8\r
41#define TRB_TYPE_EN_SLOT 9\r
42#define TRB_TYPE_DIS_SLOT 10\r
43#define TRB_TYPE_ADDRESS_DEV 11\r
44#define TRB_TYPE_CON_ENDPOINT 12\r
45#define TRB_TYPE_EVALU_CONTXT 13\r
46#define TRB_TYPE_RESET_ENDPOINT 14\r
47#define TRB_TYPE_STOP_ENDPOINT 15\r
48#define TRB_TYPE_SET_TR_DEQUE 16\r
49#define TRB_TYPE_RESET_DEV 17\r
50#define TRB_TYPE_GET_PORT_BANW 21\r
51#define TRB_TYPE_FORCE_HEADER 22\r
52#define TRB_TYPE_NO_OP_COMMAND 23\r
53#define TRB_TYPE_TRANS_EVENT 32\r
54#define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r
55#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r
56#define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r
57#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r
58#define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r
59\r
60//\r
61// Endpoint Type (EP Type).\r
62//\r
63#define ED_NOT_VALID 0\r
64#define ED_ISOCH_OUT 1\r
65#define ED_BULK_OUT 2\r
66#define ED_INTERRUPT_OUT 3\r
67#define ED_CONTROL_BIDIR 4\r
68#define ED_ISOCH_IN 5\r
69#define ED_BULK_IN 6\r
70#define ED_INTERRUPT_IN 7\r
71\r
72//\r
73// 6.4.5 TRB Completion Codes\r
74//\r
75#define TRB_COMPLETION_INVALID 0\r
76#define TRB_COMPLETION_SUCCESS 1\r
77#define TRB_COMPLETION_DATA_BUFFER_ERROR 2\r
78#define TRB_COMPLETION_BABBLE_ERROR 3\r
79#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4\r
80#define TRB_COMPLETION_TRB_ERROR 5\r
81#define TRB_COMPLETION_STALL_ERROR 6\r
82#define TRB_COMPLETION_SHORT_PACKET 13\r
83\r
84//\r
a9292c13 85// The topology string used to present usb device location\r
92870c98 86//\r
a9292c13 87typedef struct _USB_DEV_TOPOLOGY {\r
88 //\r
89 // The tier concatenation of down stream port.\r
90 //\r
91 UINT32 RouteString:20;\r
92 //\r
93 // The root port number of the chain.\r
94 //\r
95 UINT32 RootPortNum:8;\r
96 //\r
97 // The Tier the device reside.\r
98 //\r
99 UINT32 TierNum:4;\r
100} USB_DEV_TOPOLOGY;\r
101\r
102//\r
103// USB Device's RouteChart\r
104//\r
105typedef union _USB_DEV_ROUTE {\r
106 UINT32 Dword;\r
107 USB_DEV_TOPOLOGY Route;\r
92870c98 108} USB_DEV_ROUTE;\r
109\r
110//\r
111// Endpoint address and its capabilities\r
112//\r
113typedef struct _USB_ENDPOINT {\r
114 UINT8 DevAddr;\r
115 UINT8 EpAddr;\r
116 EFI_USB_DATA_DIRECTION Direction;\r
117 UINT8 DevSpeed;\r
118 UINTN MaxPacket;\r
119 UINTN Type;\r
120} USB_ENDPOINT;\r
121\r
122//\r
a9292c13 123// TRB Template\r
92870c98 124//\r
a9292c13 125typedef struct _TRB_TEMPLATE {\r
126 UINT32 Parameter1;\r
127\r
128 UINT32 Parameter2;\r
129\r
130 UINT32 Status;\r
131\r
92870c98 132 UINT32 CycleBit:1;\r
133 UINT32 RsvdZ1:9;\r
134 UINT32 Type:6;\r
a9292c13 135 UINT32 Control:16;\r
136} TRB_TEMPLATE;\r
92870c98 137\r
138typedef struct _TRANSFER_RING {\r
139 VOID *RingSeg0;\r
140 UINTN TrbNumber;\r
a9292c13 141 TRB_TEMPLATE *RingEnqueue;\r
142 TRB_TEMPLATE *RingDequeue;\r
92870c98 143 UINT32 RingPCS;\r
144} TRANSFER_RING;\r
145\r
146typedef struct _EVENT_RING {\r
147 UINT32 EventInterrupter;\r
148 VOID *ERSTBase;\r
149 VOID *EventRingSeg0;\r
150 UINTN TrbNumber;\r
a9292c13 151 TRB_TEMPLATE *EventRingEnqueue;\r
152 TRB_TEMPLATE *EventRingDequeue;\r
92870c98 153 UINT32 EventRingCCS;\r
154} EVENT_RING;\r
155\r
156//\r
157// URB (Usb Request Block) contains information for all kinds of\r
158// usb requests.\r
159//\r
160typedef struct _URB {\r
161 UINT32 Signature;\r
162 LIST_ENTRY UrbList;\r
163 //\r
164 // Usb Device URB related information\r
165 //\r
166 USB_ENDPOINT Ep;\r
167 EFI_USB_DEVICE_REQUEST *Request;\r
168 VOID *Data;\r
169 UINTN DataLen;\r
170 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r
171 VOID *Context;\r
172 //\r
173 // Execute result\r
174 //\r
175 UINT32 Result;\r
176 //\r
177 // completed data length\r
178 //\r
179 UINTN Completed;\r
180 //\r
181 // Command/Tranfer Ring info\r
182 //\r
183 TRANSFER_RING *Ring;\r
a9292c13 184 TRB_TEMPLATE *TrbStart;\r
185 TRB_TEMPLATE *TrbEnd;\r
92870c98 186 UINTN TrbNum;\r
187 EVENT_RING *EvtRing;\r
a9292c13 188 TRB_TEMPLATE *EvtTrbStart;\r
92870c98 189} URB;\r
190\r
92870c98 191//\r
192// 6.5 Event Ring Segment Table\r
193// The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime\r
194// expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the\r
195// Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table\r
196// is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).\r
197//\r
198typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
199 UINT32 PtrLo;\r
200 UINT32 PtrHi;\r
201 UINT32 RingTrbSize:16;\r
202 UINT32 RsvdZ1:16;\r
203 UINT32 RsvdZ2;\r
204} EVENT_RING_SEG_TABLE_ENTRY;\r
205\r
206//\r
207// 6.4.1.1 Normal TRB\r
208// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r
209// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r
210// Rings, and to define the Data stage information for Control Transfer Rings.\r
211//\r
212typedef struct _TRANSFER_TRB_NORMAL {\r
213 UINT32 TRBPtrLo;\r
a9292c13 214\r
92870c98 215 UINT32 TRBPtrHi;\r
a9292c13 216\r
92870c98 217 UINT32 Lenth:17;\r
218 UINT32 TDSize:5;\r
219 UINT32 IntTarget:10;\r
a9292c13 220\r
92870c98 221 UINT32 CycleBit:1;\r
222 UINT32 ENT:1;\r
223 UINT32 ISP:1;\r
224 UINT32 NS:1;\r
225 UINT32 CH:1;\r
226 UINT32 IOC:1;\r
227 UINT32 IDT:1;\r
228 UINT32 RsvdZ1:2;\r
229 UINT32 BEI:1;\r
230 UINT32 Type:6;\r
231 UINT32 RsvdZ2:16;\r
232} TRANSFER_TRB_NORMAL;\r
233\r
234//\r
235// 6.4.1.2.1 Setup Stage TRB\r
236// A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.\r
237//\r
a9292c13 238typedef struct _TRANSFER_TRB_CONTROL_SETUP {\r
92870c98 239 UINT32 bmRequestType:8;\r
240 UINT32 bRequest:8;\r
241 UINT32 wValue:16;\r
242\r
243 UINT32 wIndex:16;\r
244 UINT32 wLength:16;\r
245\r
246 UINT32 Lenth:17;\r
247 UINT32 RsvdZ1:5;\r
248 UINT32 IntTarget:10;\r
249\r
250 UINT32 CycleBit:1;\r
251 UINT32 RsvdZ2:4;\r
252 UINT32 IOC:1;\r
253 UINT32 IDT:1;\r
254 UINT32 RsvdZ3:3;\r
255 UINT32 Type:6;\r
256 UINT32 TRT:2;\r
257 UINT32 RsvdZ4:14;\r
258} TRANSFER_TRB_CONTROL_SETUP;\r
259\r
260//\r
261// 6.4.1.2.2 Data Stage TRB\r
262// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
263//\r
264typedef struct _TRANSFER_TRB_CONTROL_DATA {\r
265 UINT32 TRBPtrLo;\r
a9292c13 266\r
92870c98 267 UINT32 TRBPtrHi;\r
a9292c13 268\r
92870c98 269 UINT32 Lenth:17;\r
270 UINT32 TDSize:5;\r
271 UINT32 IntTarget:10;\r
a9292c13 272\r
92870c98 273 UINT32 CycleBit:1;\r
274 UINT32 ENT:1;\r
275 UINT32 ISP:1;\r
276 UINT32 NS:1;\r
277 UINT32 CH:1;\r
278 UINT32 IOC:1;\r
279 UINT32 IDT:1;\r
280 UINT32 RsvdZ1:3;\r
281 UINT32 Type:6;\r
282 UINT32 DIR:1;\r
283 UINT32 RsvdZ2:15;\r
284} TRANSFER_TRB_CONTROL_DATA;\r
285\r
286//\r
287// 6.4.1.2.2 Data Stage TRB\r
288// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
289//\r
290typedef struct _TRANSFER_TRB_CONTROL_STATUS {\r
291 UINT32 RsvdZ1;\r
292 UINT32 RsvdZ2;\r
a9292c13 293\r
92870c98 294 UINT32 RsvdZ3:22;\r
295 UINT32 IntTarget:10;\r
a9292c13 296\r
92870c98 297 UINT32 CycleBit:1;\r
298 UINT32 ENT:1;\r
299 UINT32 RsvdZ4:2;\r
300 UINT32 CH:1;\r
301 UINT32 IOC:1;\r
302 UINT32 RsvdZ5:4;\r
303 UINT32 Type:6;\r
304 UINT32 DIR:1;\r
305 UINT32 RsvdZ6:15;\r
306} TRANSFER_TRB_CONTROL_STATUS;\r
307\r
308//\r
309// 6.4.2.1 Transfer Event TRB\r
310// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r
311// for more information on the use and operation of Transfer Events.\r
312//\r
313typedef struct _EVT_TRB_TRANSFER {\r
314 UINT32 TRBPtrLo;\r
a9292c13 315\r
92870c98 316 UINT32 TRBPtrHi;\r
a9292c13 317\r
92870c98 318 UINT32 Lenth:24;\r
a9292c13 319 UINT32 Completecode:8;\r
320\r
92870c98 321 UINT32 CycleBit:1;\r
322 UINT32 RsvdZ1:1;\r
323 UINT32 ED:1;\r
324 UINT32 RsvdZ2:7;\r
325 UINT32 Type:6;\r
a9292c13 326 UINT32 EndpointId:5;\r
92870c98 327 UINT32 RsvdZ3:3;\r
328 UINT32 SlotId:8;\r
329} EVT_TRB_TRANSFER;\r
330\r
331//\r
332// 6.4.2.2 Command Completion Event TRB\r
333// A Command Completion Event TRB shall be generated by the xHC when a command completes on the\r
334// Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.\r
335//\r
a9292c13 336typedef struct _EVT_TRB_COMMAND_COMPLETION {\r
92870c98 337 UINT32 TRBPtrLo;\r
a9292c13 338\r
92870c98 339 UINT32 TRBPtrHi;\r
a9292c13 340\r
92870c98 341 UINT32 RsvdZ2:24;\r
a9292c13 342 UINT32 Completecode:8;\r
343\r
92870c98 344 UINT32 CycleBit:1;\r
345 UINT32 RsvdZ3:9;\r
346 UINT32 Type:6;\r
347 UINT32 VFID:8;\r
348 UINT32 SlotId:8;\r
a9292c13 349} EVT_TRB_COMMAND_COMPLETION;\r
350\r
351typedef union _TRB {\r
352 TRB_TEMPLATE TrbTemplate;\r
353 TRANSFER_TRB_NORMAL TrbNormal;\r
354 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;\r
355 TRANSFER_TRB_CONTROL_DATA TrbCtrData;\r
356 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;\r
357} TRB;\r
92870c98 358\r
359//\r
360// 6.4.3.1 No Op Command TRB\r
361// The No Op Command TRB provides a simple means for verifying the operation of the Command Ring\r
a9292c13 362// mechanisms offered by the xHCI.\r
92870c98 363//\r
364typedef struct _CMD_TRB_NO_OP {\r
365 UINT32 RsvdZ0;\r
366 UINT32 RsvdZ1;\r
367 UINT32 RsvdZ2;\r
a9292c13 368\r
92870c98 369 UINT32 CycleBit:1;\r
370 UINT32 RsvdZ3:9;\r
371 UINT32 Type:6;\r
372 UINT32 RsvdZ4:16;\r
373} CMD_TRB_NO_OP;\r
374\r
375//\r
376// 6.4.3.2 Enable Slot Command TRB\r
377// The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the\r
378// selected slot to the host in a Command Completion Event.\r
379//\r
a9292c13 380typedef struct _CMD_TRB_ENABLE_SLOT {\r
92870c98 381 UINT32 RsvdZ0;\r
382 UINT32 RsvdZ1;\r
383 UINT32 RsvdZ2;\r
a9292c13 384\r
92870c98 385 UINT32 CycleBit:1;\r
386 UINT32 RsvdZ3:9;\r
387 UINT32 Type:6;\r
388 UINT32 RsvdZ4:16;\r
a9292c13 389} CMD_TRB_ENABLE_SLOT;\r
92870c98 390\r
391//\r
392// 6.4.3.3 Disable Slot Command TRB\r
393// The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any\r
394// internal xHC resources assigned to the slot.\r
395//\r
a9292c13 396typedef struct _CMD_TRB_DISABLE_SLOT {\r
92870c98 397 UINT32 RsvdZ0;\r
398 UINT32 RsvdZ1;\r
399 UINT32 RsvdZ2;\r
a9292c13 400\r
92870c98 401 UINT32 CycleBit:1;\r
402 UINT32 RsvdZ3:9;\r
403 UINT32 Type:6;\r
404 UINT32 RsvdZ4:8;\r
405 UINT32 SlotId:8;\r
a9292c13 406} CMD_TRB_DISABLE_SLOT;\r
92870c98 407\r
408//\r
409// 6.4.3.4 Address Device Command TRB\r
410// The Address Device Command TRB transitions the selected Device Context from the Default to the\r
411// Addressed state and causes the xHC to select an address for the USB device in the Default State and\r
412// issue a SET_ADDRESS request to the USB device.\r
413//\r
a9292c13 414typedef struct _CMD_TRB_ADDRESS_DEVICE {\r
92870c98 415 UINT32 PtrLo;\r
a9292c13 416\r
92870c98 417 UINT32 PtrHi;\r
a9292c13 418\r
92870c98 419 UINT32 RsvdZ1;\r
a9292c13 420\r
92870c98 421 UINT32 CycleBit:1;\r
422 UINT32 RsvdZ2:8;\r
423 UINT32 BSR:1;\r
424 UINT32 Type:6;\r
425 UINT32 RsvdZ3:8;\r
426 UINT32 SlotId:8;\r
a9292c13 427} CMD_TRB_ADDRESS_DEVICE;\r
92870c98 428\r
429//\r
430// 6.4.3.5 Configure Endpoint Command TRB\r
431// The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the\r
432// endpoints selected by the command.\r
433//\r
a9292c13 434typedef struct _CMD_TRB_CONFIG_ENDPOINT {\r
92870c98 435 UINT32 PtrLo;\r
a9292c13 436\r
92870c98 437 UINT32 PtrHi;\r
a9292c13 438\r
92870c98 439 UINT32 RsvdZ1;\r
a9292c13 440\r
92870c98 441 UINT32 CycleBit:1;\r
442 UINT32 RsvdZ2:8;\r
443 UINT32 DC:1;\r
444 UINT32 Type:6;\r
445 UINT32 RsvdZ3:8;\r
446 UINT32 SlotId:8;\r
a9292c13 447} CMD_TRB_CONFIG_ENDPOINT;\r
92870c98 448\r
449//\r
450// 6.4.3.6 Evaluate Context Command TRB\r
451// The Evaluate Context Command TRB is used by system software to inform the xHC that the selected\r
452// Context data structures in the Device Context have been modified by system software and that the xHC\r
453// shall evaluate any changes\r
454//\r
a9292c13 455typedef struct _CMD_TRB_EVALUATE_CONTEXT {\r
92870c98 456 UINT32 PtrLo;\r
a9292c13 457\r
92870c98 458 UINT32 PtrHi;\r
a9292c13 459\r
92870c98 460 UINT32 RsvdZ1;\r
a9292c13 461\r
92870c98 462 UINT32 CycleBit:1;\r
463 UINT32 RsvdZ2:9;\r
464 UINT32 Type:6;\r
465 UINT32 RsvdZ3:8;\r
466 UINT32 SlotId:8;\r
a9292c13 467} CMD_TRB_EVALUATE_CONTEXT;\r
92870c98 468\r
469//\r
470// 6.4.3.7 Reset Endpoint Command TRB\r
471// The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring\r
472//\r
a9292c13 473typedef struct _CMD_TRB_RESET_ENDPOINT {\r
92870c98 474 UINT32 RsvdZ0;\r
475 UINT32 RsvdZ1;\r
476 UINT32 RsvdZ2;\r
a9292c13 477\r
92870c98 478 UINT32 CycleBit:1;\r
479 UINT32 RsvdZ3:8;\r
480 UINT32 TSP:1;\r
481 UINT32 Type:6;\r
482 UINT32 EDID:5;\r
483 UINT32 RsvdZ4:3;\r
484 UINT32 SlotId:8;\r
a9292c13 485} CMD_TRB_RESET_ENDPOINT;\r
92870c98 486\r
487//\r
488// 6.4.3.8 Stop Endpoint Command TRB\r
489// The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a\r
490// Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.\r
491//\r
a9292c13 492typedef struct _CMD_TRB_STOP_ENDPOINT {\r
92870c98 493 UINT32 RsvdZ0;\r
494 UINT32 RsvdZ1;\r
495 UINT32 RsvdZ2;\r
a9292c13 496\r
92870c98 497 UINT32 CycleBit:1;\r
498 UINT32 RsvdZ3:9;\r
499 UINT32 Type:6;\r
500 UINT32 EDID:5;\r
501 UINT32 RsvdZ4:2;\r
502 UINT32 SP:1;\r
503 UINT32 SlotId:8;\r
a9292c13 504} CMD_TRB_STOP_ENDPOINT;\r
92870c98 505\r
506//\r
507// 6.4.3.9 Set TR Dequeue Pointer Command TRB\r
508// The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue\r
509// Pointer and DCS fields of an Endpoint or Stream Context.\r
510//\r
a9292c13 511typedef struct _CMD_SET_TR_DEQ_POINTER {\r
92870c98 512 UINT32 PtrLo;\r
a9292c13 513\r
92870c98 514 UINT32 PtrHi;\r
a9292c13 515\r
92870c98 516 UINT32 RsvdZ1:16;\r
517 UINT32 StreamID:16;\r
a9292c13 518\r
92870c98 519 UINT32 CycleBit:1;\r
520 UINT32 RsvdZ2:9;\r
521 UINT32 Type:6;\r
522 UINT32 Endpoint:5;\r
523 UINT32 RsvdZ3:3;\r
524 UINT32 SlotId:8;\r
a9292c13 525} CMD_SET_TR_DEQ_POINTER;\r
92870c98 526\r
527//\r
a9292c13 528// 6.4.4.1 Link TRB\r
92870c98 529// A Link TRB provides support for non-contiguous TRB Rings.\r
530//\r
a9292c13 531typedef struct _LINK_TRB {\r
92870c98 532 UINT32 PtrLo;\r
a9292c13 533\r
92870c98 534 UINT32 PtrHi;\r
a9292c13 535\r
92870c98 536 UINT32 RsvdZ1:22;\r
537 UINT32 InterTarget:10;\r
a9292c13 538\r
92870c98 539 UINT32 CycleBit:1;\r
540 UINT32 TC:1;\r
541 UINT32 RsvdZ2:2;\r
542 UINT32 CH:1;\r
543 UINT32 IOC:1;\r
544 UINT32 RsvdZ3:4;\r
545 UINT32 Type:6;\r
546 UINT32 RsvdZ4:16;\r
a9292c13 547} LINK_TRB;\r
92870c98 548\r
549//\r
550// 6.2.2 Slot Context\r
551//\r
552typedef struct _SLOT_CONTEXT {\r
a9292c13 553 UINT32 RouteString:20;\r
92870c98 554 UINT32 Speed:4;\r
555 UINT32 RsvdZ1:1;\r
556 UINT32 MTT:1;\r
557 UINT32 Hub:1;\r
558 UINT32 ContextEntries:5;\r
559\r
560 UINT32 MaxExitLatency:16;\r
561 UINT32 RootHubPortNum:8;\r
562 UINT32 PortNum:8;\r
563\r
564 UINT32 TTHubSlotId:8;\r
565 UINT32 TTPortNum:8;\r
566 UINT32 TTT:2;\r
567 UINT32 RsvdZ2:4;\r
568 UINT32 InterTarget:10;\r
569\r
570 UINT32 DeviceAddress:8;\r
571 UINT32 RsvdZ3:19;\r
572 UINT32 SlotState:5;\r
573\r
574 UINT32 RsvdZ4;\r
575 UINT32 RsvdZ5;\r
576 UINT32 RsvdZ6;\r
577 UINT32 RsvdZ7;\r
578} SLOT_CONTEXT;\r
579\r
580//\r
581// 6.2.3 Endpoint Context\r
582//\r
583typedef struct _ENDPOINT_CONTEXT {\r
584 UINT32 EPState:3;\r
585 UINT32 RsvdZ1:5;\r
586 UINT32 Mult:2;\r
587 UINT32 MaxPStreams:5;\r
588 UINT32 LSA:1;\r
589 UINT32 Interval:8;\r
590 UINT32 RsvdZ2:8;\r
591\r
592 UINT32 RsvdZ3:1;\r
593 UINT32 CErr:2;\r
594 UINT32 EPType:3;\r
595 UINT32 RsvdZ4:1;\r
596 UINT32 HID:1;\r
597 UINT32 MaxBurstSize:8;\r
598 UINT32 MaxPacketSize:16;\r
599\r
600 UINT32 PtrLo;\r
601\r
602 UINT32 PtrHi;\r
603\r
604 UINT32 AverageTRBLength:16;\r
605 UINT32 MaxESITPayload:16;\r
606\r
607 UINT32 RsvdZ5;\r
608 UINT32 RsvdZ6;\r
609 UINT32 RsvdZ7;\r
610} ENDPOINT_CONTEXT;\r
611\r
612//\r
613// 6.2.5.1 Input Control Context\r
614//\r
615typedef struct _INPUT_CONTRL_CONTEXT {\r
616 UINT32 Dword1;\r
617 UINT32 Dword2;\r
618 UINT32 RsvdZ1;\r
619 UINT32 RsvdZ2;\r
620 UINT32 RsvdZ3;\r
621 UINT32 RsvdZ4;\r
622 UINT32 RsvdZ5;\r
623 UINT32 RsvdZ6;\r
624} INPUT_CONTRL_CONTEXT;\r
625\r
626//\r
627// 6.2.1 Device Context\r
628//\r
629typedef struct _DEVICE_CONTEXT {\r
630 SLOT_CONTEXT Slot;\r
631 ENDPOINT_CONTEXT EP[31];\r
632} DEVICE_CONTEXT;\r
633\r
634//\r
635// 6.2.5 Input Context\r
636//\r
637typedef struct _INPUT_CONTEXT {\r
638 INPUT_CONTRL_CONTEXT InputControlContext;\r
639 SLOT_CONTEXT Slot;\r
640 ENDPOINT_CONTEXT EP[31];\r
641} INPUT_CONTEXT;\r
642\r
643/**\r
644 Initialize the XHCI host controller for schedule.\r
645\r
a9292c13 646 @param Xhc The XHCI Instance to be initialized.\r
92870c98 647\r
648**/\r
649VOID\r
650XhcInitSched (\r
a9292c13 651 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 652 );\r
653\r
654/**\r
655 Free the resouce allocated at initializing schedule.\r
656\r
a9292c13 657 @param Xhc The XHCI Instance.\r
92870c98 658\r
659**/\r
660VOID\r
661XhcFreeSched (\r
a9292c13 662 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 663 );\r
664\r
665/**\r
666 Ring the door bell to notify XHCI there is a transaction to be executed through URB.\r
667\r
a9292c13 668 @param Xhc The XHCI Instance.\r
92870c98 669 @param Urb The URB to be rung.\r
670\r
671 @retval EFI_SUCCESS Successfully ring the door bell.\r
672\r
673**/\r
674EFI_STATUS\r
675RingIntTransferDoorBell (\r
a9292c13 676 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 677 IN URB *Urb\r
678 );\r
679\r
680/**\r
681 Execute the transfer by polling the URB. This is a synchronous operation.\r
682\r
a9292c13 683 @param Xhc The XHCI Instance.\r
92870c98 684 @param CmdTransfer The executed URB is for cmd transfer or not.\r
685 @param Urb The URB to execute.\r
a9292c13 686 @param Timeout The time to wait before abort, in millisecond.\r
92870c98 687\r
688 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r
689 @return EFI_TIMEOUT The transfer failed due to time out.\r
690 @return EFI_SUCCESS The transfer finished OK.\r
691\r
692**/\r
693EFI_STATUS\r
694XhcExecTransfer (\r
a9292c13 695 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 696 IN BOOLEAN CmdTransfer,\r
697 IN URB *Urb,\r
a9292c13 698 IN UINTN Timeout\r
92870c98 699 );\r
700\r
701/**\r
702 Delete a single asynchronous interrupt transfer for\r
703 the device and endpoint.\r
704\r
a9292c13 705 @param Xhc The XHCI Instance.\r
92870c98 706 @param DevAddr The address of the target device.\r
707 @param EpNum The endpoint of the target.\r
708\r
709 @retval EFI_SUCCESS An asynchronous transfer is removed.\r
710 @retval EFI_NOT_FOUND No transfer for the device is found.\r
711\r
712**/\r
713EFI_STATUS\r
714XhciDelAsyncIntTransfer (\r
a9292c13 715 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 716 IN UINT8 DevAddr,\r
717 IN UINT8 EpNum\r
718 );\r
719\r
720/**\r
721 Remove all the asynchronous interrupt transfers.\r
722\r
a9292c13 723 @param Xhc The XHCI Instance.\r
92870c98 724\r
725**/\r
726VOID\r
727XhciDelAllAsyncIntTransfers (\r
a9292c13 728 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 729 );\r
730\r
731/**\r
732 Set Bios Ownership\r
733\r
a9292c13 734 @param Xhc The XHCI Instance.\r
92870c98 735\r
736**/\r
737VOID\r
738XhcSetBiosOwnership (\r
a9292c13 739 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 740 );\r
741\r
742/**\r
743 Clear Bios Ownership\r
744\r
a9292c13 745 @param Xhc The XHCI Instance.\r
92870c98 746\r
747**/\r
748VOID\r
749XhcClearBiosOwnership (\r
a9292c13 750 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 751 );\r
752\r
753/**\r
754 Find out the slot id according to device address assigned by XHCI's Address_Device cmd.\r
755\r
a9292c13 756 @param Xhc The XHCI Instance.\r
92870c98 757 @param DevAddr The device address of the target device.\r
758\r
759 @return The slot id used by the device.\r
760\r
761**/\r
762UINT8\r
763XhcDevAddrToSlotId (\r
a9292c13 764 IN USB_XHCI_INSTANCE *Xhc,\r
765 IN UINT8 DevAddr\r
92870c98 766 );\r
767\r
768/**\r
769 Find out the slot id according to the device's route string.\r
770\r
a9292c13 771 @param Xhc The XHCI Instance.\r
772 @param RouteString The route string described the device location.\r
92870c98 773\r
774 @return The slot id used by the device.\r
775\r
776**/\r
777UINT8\r
778EFIAPI\r
779XhcRouteStringToSlotId (\r
a9292c13 780 IN USB_XHCI_INSTANCE *Xhc,\r
781 IN USB_DEV_ROUTE RouteString\r
92870c98 782 );\r
783\r
784/**\r
785 Calculate the device context index by endpoint address and direction.\r
786\r
787 @param EpAddr The target endpoint number.\r
788 @param Direction The direction of the target endpoint.\r
789\r
790 @return The device context index of endpoint.\r
791\r
792**/\r
793UINT8\r
794XhcEndpointToDci (\r
795 IN UINT8 EpAddr,\r
796 IN UINT8 Direction\r
797 );\r
798\r
799/**\r
800 Ring the door bell to notify XHCI there is a transaction to be executed.\r
801\r
a9292c13 802 @param Xhc The XHCI Instance.\r
92870c98 803 @param SlotId The slot id of the target device.\r
804 @param Dci The device context index of the target slot or endpoint.\r
805\r
806 @retval EFI_SUCCESS Successfully ring the door bell.\r
807\r
808**/\r
809EFI_STATUS\r
810EFIAPI\r
811XhcRingDoorBell (\r
a9292c13 812 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 813 IN UINT8 SlotId,\r
814 IN UINT8 Dci\r
815 );\r
816\r
817/**\r
818 Interrupt transfer periodic check handler.\r
819\r
820 @param Event Interrupt event.\r
a9292c13 821 @param Context Pointer to USB_XHCI_INSTANCE.\r
92870c98 822\r
823**/\r
824VOID\r
825EFIAPI\r
826XhcMonitorAsyncRequests (\r
827 IN EFI_EVENT Event,\r
828 IN VOID *Context\r
829 );\r
830\r
831/**\r
832 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.\r
833\r
a9292c13 834 @param Xhc The XHCI Instance.\r
92870c98 835 @param ParentRouteChart The route string pointed to the parent device if it exists.\r
836 @param Port The port to be polled.\r
837 @param PortState The port state.\r
838\r
839 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.\r
840 @retval Others Should not appear.\r
841\r
842**/\r
843EFI_STATUS\r
844EFIAPI\r
845XhcPollPortStatusChange (\r
a9292c13 846 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 847 IN USB_DEV_ROUTE ParentRouteChart,\r
848 IN UINT8 Port,\r
849 IN EFI_USB_PORT_STATUS *PortState\r
850 );\r
851\r
852/**\r
853 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
854\r
a9292c13 855 @param Xhc The XHCI Instance.\r
92870c98 856 @param SlotId The slot id to be configured.\r
857 @param PortNum The total number of downstream port supported by the hub.\r
858 @param TTT The TT think time of the hub device.\r
859 @param MTT The multi-TT of the hub device.\r
860\r
861 @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r
862\r
863**/\r
864EFI_STATUS\r
865XhcConfigHubContext (\r
a9292c13 866 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 867 IN UINT8 SlotId,\r
868 IN UINT8 PortNum,\r
869 IN UINT8 TTT,\r
870 IN UINT8 MTT\r
871 );\r
872\r
873/**\r
874 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
875\r
a9292c13 876 @param Xhc The XHCI Instance.\r
92870c98 877 @param SlotId The slot id to be configured.\r
878 @param DeviceSpeed The device's speed.\r
879 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
880\r
881 @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
882\r
883**/\r
884EFI_STATUS\r
885EFIAPI\r
886XhcSetConfigCmd (\r
a9292c13 887 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 888 IN UINT8 SlotId,\r
889 IN UINT8 DeviceSpeed,\r
890 IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
891 );\r
892\r
893/**\r
894 Find out the actual device address according to the requested device address from UsbBus.\r
895\r
a9292c13 896 @param Xhc The XHCI Instance.\r
897 @param BusDevAddr The requested device address by UsbBus upper driver.\r
92870c98 898\r
899 @return The actual device address assigned to the device.\r
900\r
901**/\r
902UINT8\r
903EFIAPI\r
904XhcBusDevAddrToSlotId (\r
a9292c13 905 IN USB_XHCI_INSTANCE *Xhc,\r
906 IN UINT8 BusDevAddr\r
92870c98 907 );\r
908\r
909/**\r
910 Assign and initialize the device slot for a new device.\r
911\r
a9292c13 912 @param Xhc The XHCI Instance.\r
92870c98 913 @param ParentRouteChart The route string pointed to the parent device.\r
914 @param ParentPort The port at which the device is located.\r
915 @param RouteChart The route string pointed to the device.\r
916 @param DeviceSpeed The device speed.\r
917\r
918 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r
919\r
920**/\r
921EFI_STATUS\r
922EFIAPI\r
923XhcInitializeDeviceSlot (\r
a9292c13 924 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 925 IN USB_DEV_ROUTE ParentRouteChart,\r
926 IN UINT16 ParentPort,\r
927 IN USB_DEV_ROUTE RouteChart,\r
928 IN UINT8 DeviceSpeed\r
929 );\r
930\r
931/**\r
932 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
933\r
a9292c13 934 @param Xhc The XHCI Instance.\r
92870c98 935 @param SlotId The slot id to be evaluated.\r
936 @param MaxPacketSize The max packet size supported by the device control transfer.\r
937\r
938 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r
939\r
940**/\r
941EFI_STATUS\r
942EFIAPI\r
943XhcEvaluateContext (\r
a9292c13 944 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 945 IN UINT8 SlotId,\r
946 IN UINT32 MaxPacketSize\r
947 );\r
948\r
949/**\r
950 Disable the specified device slot.\r
951\r
a9292c13 952 @param Xhc The XHCI Instance.\r
92870c98 953 @param SlotId The slot id to be disabled.\r
954\r
955 @retval EFI_SUCCESS Successfully disable the device slot.\r
956\r
957**/\r
958EFI_STATUS\r
959EFIAPI\r
960XhcDisableSlotCmd (\r
a9292c13 961 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 962 IN UINT8 SlotId\r
963 );\r
964\r
965/**\r
966 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r
967\r
a9292c13 968 @param Xhc The XHCI Instance.\r
92870c98 969 @param TrsRing The transfer ring to sync.\r
970\r
971 @retval EFI_SUCCESS The transfer ring is synchronized successfully.\r
972\r
973**/\r
974EFI_STATUS\r
975EFIAPI\r
976XhcSyncTrsRing (\r
a9292c13 977 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 978 TRANSFER_RING *TrsRing\r
979 );\r
980\r
981/**\r
982 Synchronize the specified event ring to update the enqueue and dequeue pointer.\r
983\r
a9292c13 984 @param Xhc The XHCI Instance.\r
92870c98 985 @param EvtRing The event ring to sync.\r
986\r
987 @retval EFI_SUCCESS The event ring is synchronized successfully.\r
988\r
989**/\r
990EFI_STATUS\r
991EFIAPI\r
992XhcSyncEventRing (\r
a9292c13 993 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 994 EVENT_RING *EvtRing\r
995 );\r
996\r
997/**\r
998 Check if there is a new generated event.\r
999\r
a9292c13 1000 @param Xhc The XHCI Instance.\r
92870c98 1001 @param EvtRing The event ring to check.\r
1002 @param NewEvtTrb The new event TRB found.\r
1003\r
1004 @retval EFI_SUCCESS Found a new event TRB at the event ring.\r
1005 @retval EFI_NOT_READY The event ring has no new event.\r
1006\r
1007**/\r
1008EFI_STATUS\r
1009EFIAPI\r
1010XhcCheckNewEvent (\r
a9292c13 1011 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1012 IN EVENT_RING *EvtRing,\r
a9292c13 1013 OUT TRB_TEMPLATE **NewEvtTrb\r
92870c98 1014 );\r
1015\r
1016/**\r
1017 Create XHCI transfer ring.\r
1018\r
a9292c13 1019 @param Xhc The XHCI Instance.\r
92870c98 1020 @param TrbNum The number of TRB in the ring.\r
1021 @param TransferRing The created transfer ring.\r
1022\r
1023**/\r
1024VOID\r
1025CreateTransferRing (\r
a9292c13 1026 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1027 IN UINTN TrbNum,\r
1028 OUT TRANSFER_RING *TransferRing\r
1029 );\r
1030\r
1031/**\r
1032 Create XHCI event ring.\r
1033\r
a9292c13 1034 @param Xhc The XHCI Instance.\r
92870c98 1035 @param EventInterrupter The interrupter of event.\r
1036 @param EventRing The created event ring.\r
1037\r
1038**/\r
1039VOID\r
1040CreateEventRing (\r
a9292c13 1041 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1042 IN UINT8 EventInterrupter,\r
1043 OUT EVENT_RING *EventRing\r
1044 );\r
1045\r
1046/**\r
1047 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted\r
1048 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint\r
1049 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is\r
1050 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the\r
1051 Stopped to the Running state.\r
1052\r
a9292c13 1053 @param Xhc The XHCI Instance.\r
92870c98 1054 @param Urb The urb which makes the endpoint halted.\r
1055\r
1056 @retval EFI_SUCCESS The recovery is successful.\r
1057 @retval Others Failed to recovery halted endpoint.\r
1058\r
1059**/\r
1060EFI_STATUS\r
1061EFIAPI\r
1062XhcRecoverHaltedEndpoint (\r
a9292c13 1063 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1064 IN URB *Urb\r
1065 );\r
1066\r
1067/**\r
1068 Create a new URB for a new transaction.\r
1069\r
a9292c13 1070 @param Xhc The XHCI Instance\r
92870c98 1071 @param DevAddr The device address\r
1072 @param EpAddr Endpoint addrress\r
1073 @param DevSpeed The device speed\r
1074 @param MaxPacket The max packet length of the endpoint\r
1075 @param Type The transaction type\r
1076 @param Request The standard USB request for control transfer\r
1077 @param Data The user data to transfer\r
1078 @param DataLen The length of data buffer\r
1079 @param Callback The function to call when data is transferred\r
1080 @param Context The context to the callback\r
1081\r
1082 @return Created URB or NULL\r
1083\r
1084**/\r
1085URB*\r
1086XhcCreateUrb (\r
a9292c13 1087 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1088 IN UINT8 DevAddr,\r
1089 IN UINT8 EpAddr,\r
1090 IN UINT8 DevSpeed,\r
1091 IN UINTN MaxPacket,\r
1092 IN UINTN Type,\r
1093 IN EFI_USB_DEVICE_REQUEST *Request,\r
1094 IN VOID *Data,\r
1095 IN UINTN DataLen,\r
1096 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
1097 IN VOID *Context\r
1098 );\r
1099\r
1100/**\r
1101 Create a transfer TRB.\r
1102\r
a9292c13 1103 @param Xhc The XHCI Instance\r
92870c98 1104 @param Urb The urb used to construct the transfer TRB.\r
1105\r
1106 @return Created TRB or NULL\r
1107\r
1108**/\r
1109EFI_STATUS\r
1110XhcCreateTransferTrb (\r
a9292c13 1111 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1112 IN URB *Urb\r
1113 );\r
1114\r
1115#endif\r