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[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.h
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92870c98 1/** @file\r
2\r
3 This file contains the definition for XHCI host controller schedule routines.\r
4\r
5Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r
6This program and the accompanying materials\r
7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#ifndef _EFI_XHCI_SCHED_H_\r
17#define _EFI_XHCI_SCHED_H_\r
18\r
19#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')\r
20\r
21//\r
22// Transfer types, used in URB to identify the transfer type\r
23//\r
24#define XHC_CTRL_TRANSFER 0x01\r
25#define XHC_BULK_TRANSFER 0x02\r
26#define XHC_INT_TRANSFER_SYNC 0x04\r
27#define XHC_INT_TRANSFER_ASYNC 0x08\r
28#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r
29\r
30//\r
31// 6.4.6 TRB Types\r
32//\r
33#define TRB_TYPE_NORMAL 1\r
34#define TRB_TYPE_SETUP_STAGE 2\r
35#define TRB_TYPE_DATA_STAGE 3\r
36#define TRB_TYPE_STATUS_STAGE 4\r
37#define TRB_TYPE_ISOCH 5\r
38#define TRB_TYPE_LINK 6\r
39#define TRB_TYPE_EVENT_DATA 7\r
40#define TRB_TYPE_NO_OP 8\r
41#define TRB_TYPE_EN_SLOT 9\r
42#define TRB_TYPE_DIS_SLOT 10\r
43#define TRB_TYPE_ADDRESS_DEV 11\r
44#define TRB_TYPE_CON_ENDPOINT 12\r
45#define TRB_TYPE_EVALU_CONTXT 13\r
46#define TRB_TYPE_RESET_ENDPOINT 14\r
47#define TRB_TYPE_STOP_ENDPOINT 15\r
48#define TRB_TYPE_SET_TR_DEQUE 16\r
49#define TRB_TYPE_RESET_DEV 17\r
50#define TRB_TYPE_GET_PORT_BANW 21\r
51#define TRB_TYPE_FORCE_HEADER 22\r
52#define TRB_TYPE_NO_OP_COMMAND 23\r
53#define TRB_TYPE_TRANS_EVENT 32\r
54#define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r
55#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r
56#define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r
57#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r
58#define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r
59\r
60//\r
61// Endpoint Type (EP Type).\r
62//\r
63#define ED_NOT_VALID 0\r
64#define ED_ISOCH_OUT 1\r
65#define ED_BULK_OUT 2\r
66#define ED_INTERRUPT_OUT 3\r
67#define ED_CONTROL_BIDIR 4\r
68#define ED_ISOCH_IN 5\r
69#define ED_BULK_IN 6\r
70#define ED_INTERRUPT_IN 7\r
71\r
72//\r
73// 6.4.5 TRB Completion Codes\r
74//\r
75#define TRB_COMPLETION_INVALID 0\r
76#define TRB_COMPLETION_SUCCESS 1\r
77#define TRB_COMPLETION_DATA_BUFFER_ERROR 2\r
78#define TRB_COMPLETION_BABBLE_ERROR 3\r
79#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4\r
80#define TRB_COMPLETION_TRB_ERROR 5\r
81#define TRB_COMPLETION_STALL_ERROR 6\r
82#define TRB_COMPLETION_SHORT_PACKET 13\r
83\r
84//\r
85// USB device RouteChart record\r
86//\r
87typedef union _USB_DEV_TOPOLOGY {\r
88 UINT32 Dword;\r
89 struct {\r
90 UINT32 RouteString:20; ///< The tier concatenation of down stream port\r
91 UINT32 RootPortNum:8; ///< The root port number of the chain\r
92 UINT32 TierNum:4; ///< The Tier the device reside\r
93 } Field;\r
94} USB_DEV_ROUTE;\r
95\r
96//\r
97// Endpoint address and its capabilities\r
98//\r
99typedef struct _USB_ENDPOINT {\r
100 UINT8 DevAddr;\r
101 UINT8 EpAddr;\r
102 EFI_USB_DATA_DIRECTION Direction;\r
103 UINT8 DevSpeed;\r
104 UINTN MaxPacket;\r
105 UINTN Type;\r
106} USB_ENDPOINT;\r
107\r
108//\r
109// Command TRB\r
110//\r
111typedef struct _TRB {\r
112 UINT32 Dword1;\r
113 UINT32 Dword2;\r
114 UINT32 Dword3;\r
115 UINT32 CycleBit:1;\r
116 UINT32 RsvdZ1:9;\r
117 UINT32 Type:6;\r
118 UINT32 RsvdZ2:16;\r
119} TRB;\r
120\r
121typedef struct _TRANSFER_RING {\r
122 VOID *RingSeg0;\r
123 UINTN TrbNumber;\r
124 TRB *RingEnqueue;\r
125 TRB *RingDequeue;\r
126 UINT32 RingPCS;\r
127} TRANSFER_RING;\r
128\r
129typedef struct _EVENT_RING {\r
130 UINT32 EventInterrupter;\r
131 VOID *ERSTBase;\r
132 VOID *EventRingSeg0;\r
133 UINTN TrbNumber;\r
134 TRB *EventRingEnqueue;\r
135 TRB *EventRingDequeue;\r
136 UINT32 EventRingCCS;\r
137} EVENT_RING;\r
138\r
139//\r
140// URB (Usb Request Block) contains information for all kinds of\r
141// usb requests.\r
142//\r
143typedef struct _URB {\r
144 UINT32 Signature;\r
145 LIST_ENTRY UrbList;\r
146 //\r
147 // Usb Device URB related information\r
148 //\r
149 USB_ENDPOINT Ep;\r
150 EFI_USB_DEVICE_REQUEST *Request;\r
151 VOID *Data;\r
152 UINTN DataLen;\r
153 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r
154 VOID *Context;\r
155 //\r
156 // Execute result\r
157 //\r
158 UINT32 Result;\r
159 //\r
160 // completed data length\r
161 //\r
162 UINTN Completed;\r
163 //\r
164 // Command/Tranfer Ring info\r
165 //\r
166 TRANSFER_RING *Ring;\r
167 TRB *TrbStart;\r
168 TRB *TrbEnd;\r
169 UINTN TrbNum;\r
170 EVENT_RING *EvtRing;\r
171 TRB *EvtTrbStart;\r
172} URB;\r
173\r
174//\r
175// 5.5.2 Interrupter Register Set\r
176//\r
177typedef struct _INTERRUPTER_REGISTER_SET {\r
178 UINT32 InterrupterManagement;\r
179 UINT32 InterrupterModeration;\r
180 UINT32 RingSegTableSize:16;\r
181 UINT32 RsvdZ1:16;\r
182 UINT32 RsvdZ2;\r
183 UINT32 BasePtrLo;\r
184 UINT32 BasePtrHi;\r
185 UINT32 DequeLo;\r
186 UINT32 DequeHi;\r
187} INTERRUPTER_REGISTER_SET;\r
188\r
189//\r
190// Host Controller Runtime Registers\r
191//\r
192typedef struct _HC_RUNTIME_REGS {\r
193 UINT32 MicroframeIndex;\r
194 UINT32 RsvdZ1;\r
195 UINT64 RsvdZ2;\r
196 UINT64 RsvdZ3;\r
197 UINT64 RsvdZ4;\r
198 INTERRUPTER_REGISTER_SET IR[1];\r
199} HC_RUNTIME_REGS;\r
200\r
201//\r
202// 6.5 Event Ring Segment Table\r
203// The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime\r
204// expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the\r
205// Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table\r
206// is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).\r
207//\r
208typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
209 UINT32 PtrLo;\r
210 UINT32 PtrHi;\r
211 UINT32 RingTrbSize:16;\r
212 UINT32 RsvdZ1:16;\r
213 UINT32 RsvdZ2;\r
214} EVENT_RING_SEG_TABLE_ENTRY;\r
215\r
216//\r
217// 6.4.1.1 Normal TRB\r
218// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r
219// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r
220// Rings, and to define the Data stage information for Control Transfer Rings.\r
221//\r
222typedef struct _TRANSFER_TRB_NORMAL {\r
223 UINT32 TRBPtrLo;\r
224 UINT32 TRBPtrHi;\r
225 UINT32 Lenth:17;\r
226 UINT32 TDSize:5;\r
227 UINT32 IntTarget:10;\r
228 UINT32 CycleBit:1;\r
229 UINT32 ENT:1;\r
230 UINT32 ISP:1;\r
231 UINT32 NS:1;\r
232 UINT32 CH:1;\r
233 UINT32 IOC:1;\r
234 UINT32 IDT:1;\r
235 UINT32 RsvdZ1:2;\r
236 UINT32 BEI:1;\r
237 UINT32 Type:6;\r
238 UINT32 RsvdZ2:16;\r
239} TRANSFER_TRB_NORMAL;\r
240\r
241//\r
242// 6.4.1.2.1 Setup Stage TRB\r
243// A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.\r
244//\r
245typedef struct _TRANSFER_TRB_CONTROL_SETUP{\r
246 UINT32 bmRequestType:8;\r
247 UINT32 bRequest:8;\r
248 UINT32 wValue:16;\r
249\r
250 UINT32 wIndex:16;\r
251 UINT32 wLength:16;\r
252\r
253 UINT32 Lenth:17;\r
254 UINT32 RsvdZ1:5;\r
255 UINT32 IntTarget:10;\r
256\r
257 UINT32 CycleBit:1;\r
258 UINT32 RsvdZ2:4;\r
259 UINT32 IOC:1;\r
260 UINT32 IDT:1;\r
261 UINT32 RsvdZ3:3;\r
262 UINT32 Type:6;\r
263 UINT32 TRT:2;\r
264 UINT32 RsvdZ4:14;\r
265} TRANSFER_TRB_CONTROL_SETUP;\r
266\r
267//\r
268// 6.4.1.2.2 Data Stage TRB\r
269// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
270//\r
271typedef struct _TRANSFER_TRB_CONTROL_DATA {\r
272 UINT32 TRBPtrLo;\r
273 UINT32 TRBPtrHi;\r
274 UINT32 Lenth:17;\r
275 UINT32 TDSize:5;\r
276 UINT32 IntTarget:10;\r
277 UINT32 CycleBit:1;\r
278 UINT32 ENT:1;\r
279 UINT32 ISP:1;\r
280 UINT32 NS:1;\r
281 UINT32 CH:1;\r
282 UINT32 IOC:1;\r
283 UINT32 IDT:1;\r
284 UINT32 RsvdZ1:3;\r
285 UINT32 Type:6;\r
286 UINT32 DIR:1;\r
287 UINT32 RsvdZ2:15;\r
288} TRANSFER_TRB_CONTROL_DATA;\r
289\r
290//\r
291// 6.4.1.2.2 Data Stage TRB\r
292// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
293//\r
294typedef struct _TRANSFER_TRB_CONTROL_STATUS {\r
295 UINT32 RsvdZ1;\r
296 UINT32 RsvdZ2;\r
297 UINT32 RsvdZ3:22;\r
298 UINT32 IntTarget:10;\r
299 UINT32 CycleBit:1;\r
300 UINT32 ENT:1;\r
301 UINT32 RsvdZ4:2;\r
302 UINT32 CH:1;\r
303 UINT32 IOC:1;\r
304 UINT32 RsvdZ5:4;\r
305 UINT32 Type:6;\r
306 UINT32 DIR:1;\r
307 UINT32 RsvdZ6:15;\r
308} TRANSFER_TRB_CONTROL_STATUS;\r
309\r
310//\r
311// 6.4.2.1 Transfer Event TRB\r
312// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r
313// for more information on the use and operation of Transfer Events.\r
314//\r
315typedef struct _EVT_TRB_TRANSFER {\r
316 UINT32 TRBPtrLo;\r
317 UINT32 TRBPtrHi;\r
318 UINT32 Lenth:24;\r
319 UINT32 Completcode:8;\r
320 UINT32 CycleBit:1;\r
321 UINT32 RsvdZ1:1;\r
322 UINT32 ED:1;\r
323 UINT32 RsvdZ2:7;\r
324 UINT32 Type:6;\r
325 UINT32 EndpointID:5;\r
326 UINT32 RsvdZ3:3;\r
327 UINT32 SlotId:8;\r
328} EVT_TRB_TRANSFER;\r
329\r
330//\r
331// 6.4.2.2 Command Completion Event TRB\r
332// A Command Completion Event TRB shall be generated by the xHC when a command completes on the\r
333// Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.\r
334//\r
335typedef struct _EVT_TRB_COMMAND {\r
336 UINT32 TRBPtrLo;\r
337 UINT32 TRBPtrHi;\r
338 UINT32 RsvdZ2:24;\r
339 UINT32 Completcode:8;\r
340 UINT32 CycleBit:1;\r
341 UINT32 RsvdZ3:9;\r
342 UINT32 Type:6;\r
343 UINT32 VFID:8;\r
344 UINT32 SlotId:8;\r
345} EVT_TRB_COMMAND;\r
346\r
347//\r
348// 6.4.2.3 Port Status Change Event TRB\r
349//\r
350typedef struct _EVT_TRB_PORT {\r
351 UINT32 RsvdZ1:24;\r
352 UINT32 PortID:8;\r
353 UINT32 RsvdZ2;\r
354 UINT32 RsvdZ3:24;\r
355 UINT32 Completcode:8;\r
356 UINT32 CycleBit:1;\r
357 UINT32 RsvdZ4:9;\r
358 UINT32 Type:6;\r
359 UINT32 RsvdZ5:16;\r
360} EVT_TRB_PORT;\r
361\r
362//\r
363// 6.4.3.1 No Op Command TRB\r
364// The No Op Command TRB provides a simple means for verifying the operation of the Command Ring\r
365// mechanisms offered by the xHCI.\r
366//\r
367typedef struct _CMD_TRB_NO_OP {\r
368 UINT32 RsvdZ0;\r
369 UINT32 RsvdZ1;\r
370 UINT32 RsvdZ2;\r
371 UINT32 CycleBit:1;\r
372 UINT32 RsvdZ3:9;\r
373 UINT32 Type:6;\r
374 UINT32 RsvdZ4:16;\r
375} CMD_TRB_NO_OP;\r
376\r
377//\r
378// 6.4.3.2 Enable Slot Command TRB\r
379// The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the\r
380// selected slot to the host in a Command Completion Event.\r
381//\r
382typedef struct _CMD_TRB_EN_SLOT {\r
383 UINT32 RsvdZ0;\r
384 UINT32 RsvdZ1;\r
385 UINT32 RsvdZ2;\r
386 UINT32 CycleBit:1;\r
387 UINT32 RsvdZ3:9;\r
388 UINT32 Type:6;\r
389 UINT32 RsvdZ4:16;\r
390} CMD_TRB_EN_SLOT;\r
391\r
392//\r
393// 6.4.3.3 Disable Slot Command TRB\r
394// The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any\r
395// internal xHC resources assigned to the slot.\r
396//\r
397typedef struct _CMD_TRB_DIS_SLOT {\r
398 UINT32 RsvdZ0;\r
399 UINT32 RsvdZ1;\r
400 UINT32 RsvdZ2;\r
401 UINT32 CycleBit:1;\r
402 UINT32 RsvdZ3:9;\r
403 UINT32 Type:6;\r
404 UINT32 RsvdZ4:8;\r
405 UINT32 SlotId:8;\r
406} CMD_TRB_DIS_SLOT;\r
407\r
408typedef struct _CMD_TRB_RESET_PORT {\r
409 UINT32 RsvdZ0;\r
410 UINT32 RsvdZ1;\r
411 UINT32 RsvdZ2;\r
412 UINT32 CycleBit:1;\r
413 UINT32 RsvdZ3:8;\r
414 UINT32 Tsp:1;\r
415 UINT32 Type:6;\r
416 UINT32 Endpoint:5;\r
417 UINT32 RsvdZ4:3;\r
418 UINT32 SlotId:8;\r
419} CMD_TRB_RESET_PORT;\r
420\r
421//\r
422// 6.4.3.4 Address Device Command TRB\r
423// The Address Device Command TRB transitions the selected Device Context from the Default to the\r
424// Addressed state and causes the xHC to select an address for the USB device in the Default State and\r
425// issue a SET_ADDRESS request to the USB device.\r
426//\r
427typedef struct _CMD_TRB_ADDR_DEV {\r
428 UINT32 PtrLo;\r
429 UINT32 PtrHi;\r
430 UINT32 RsvdZ1;\r
431 UINT32 CycleBit:1;\r
432 UINT32 RsvdZ2:8;\r
433 UINT32 BSR:1;\r
434 UINT32 Type:6;\r
435 UINT32 RsvdZ3:8;\r
436 UINT32 SlotId:8;\r
437} CMD_TRB_ADDR_DEV;\r
438\r
439//\r
440// 6.4.3.5 Configure Endpoint Command TRB\r
441// The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the\r
442// endpoints selected by the command.\r
443//\r
444typedef struct _CMD_CFG_ED {\r
445 UINT32 PtrLo;\r
446 UINT32 PtrHi;\r
447 UINT32 RsvdZ1;\r
448 UINT32 CycleBit:1;\r
449 UINT32 RsvdZ2:8;\r
450 UINT32 DC:1;\r
451 UINT32 Type:6;\r
452 UINT32 RsvdZ3:8;\r
453 UINT32 SlotId:8;\r
454} CMD_CFG_ED;\r
455\r
456//\r
457// 6.4.3.6 Evaluate Context Command TRB\r
458// The Evaluate Context Command TRB is used by system software to inform the xHC that the selected\r
459// Context data structures in the Device Context have been modified by system software and that the xHC\r
460// shall evaluate any changes\r
461//\r
462typedef struct _CMD_TRB_EVALU_CONTX {\r
463 UINT32 PtrLo;\r
464 UINT32 PtrHi;\r
465 UINT32 RsvdZ1;\r
466 UINT32 CycleBit:1;\r
467 UINT32 RsvdZ2:9;\r
468 UINT32 Type:6;\r
469 UINT32 RsvdZ3:8;\r
470 UINT32 SlotId:8;\r
471} CMD_TRB_EVALU_CONTX;\r
472\r
473//\r
474// 6.4.3.7 Reset Endpoint Command TRB\r
475// The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring\r
476//\r
477typedef struct _CMD_TRB_RESET_ED {\r
478 UINT32 RsvdZ0;\r
479 UINT32 RsvdZ1;\r
480 UINT32 RsvdZ2;\r
481 UINT32 CycleBit:1;\r
482 UINT32 RsvdZ3:8;\r
483 UINT32 TSP:1;\r
484 UINT32 Type:6;\r
485 UINT32 EDID:5;\r
486 UINT32 RsvdZ4:3;\r
487 UINT32 SlotId:8;\r
488} CMD_TRB_RESET_ED;\r
489\r
490//\r
491// 6.4.3.8 Stop Endpoint Command TRB\r
492// The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a\r
493// Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.\r
494//\r
495typedef struct _CMD_TRB_STOP_ED {\r
496 UINT32 RsvdZ0;\r
497 UINT32 RsvdZ1;\r
498 UINT32 RsvdZ2;\r
499 UINT32 CycleBit:1;\r
500 UINT32 RsvdZ3:9;\r
501 UINT32 Type:6;\r
502 UINT32 EDID:5;\r
503 UINT32 RsvdZ4:2;\r
504 UINT32 SP:1;\r
505 UINT32 SlotId:8;\r
506} CMD_TRB_STOP_ED;\r
507\r
508//\r
509// 6.4.3.9 Set TR Dequeue Pointer Command TRB\r
510// The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue\r
511// Pointer and DCS fields of an Endpoint or Stream Context.\r
512//\r
513typedef struct _CMD_SET_TR_DEQ {\r
514 UINT32 PtrLo;\r
515 UINT32 PtrHi;\r
516 UINT32 RsvdZ1:16;\r
517 UINT32 StreamID:16;\r
518 UINT32 CycleBit:1;\r
519 UINT32 RsvdZ2:9;\r
520 UINT32 Type:6;\r
521 UINT32 Endpoint:5;\r
522 UINT32 RsvdZ3:3;\r
523 UINT32 SlotId:8;\r
524} CMD_SET_TR_DEQ;\r
525\r
526//\r
527// A Link TRB provides support for non-contiguous TRB Rings.\r
528//\r
529typedef struct _LNK_TRB {\r
530 UINT32 PtrLo;\r
531 UINT32 PtrHi;\r
532 UINT32 RsvdZ1:22;\r
533 UINT32 InterTarget:10;\r
534 UINT32 CycleBit:1;\r
535 UINT32 TC:1;\r
536 UINT32 RsvdZ2:2;\r
537 UINT32 CH:1;\r
538 UINT32 IOC:1;\r
539 UINT32 RsvdZ3:4;\r
540 UINT32 Type:6;\r
541 UINT32 RsvdZ4:16;\r
542} LNK_TRB;\r
543\r
544//\r
545// A Link TRB provides support for non-contiguous TRB Rings.\r
546//\r
547typedef struct _NO_OP_TRB {\r
548 UINT32 RsvdZ0;\r
549 UINT32 RsvdZ1;\r
550 UINT32 RsvdZ2;\r
551 UINT32 CycleBit:1;\r
552 UINT32 RsvdZ3:9;\r
553 UINT32 Type:6;\r
554 UINT32 RsvdZ4:16;\r
555} CMD_NO_OP_TRB;\r
556\r
557//\r
558// 6.2.2 Slot Context\r
559//\r
560typedef struct _SLOT_CONTEXT {\r
561 UINT32 RouteStr:20;\r
562 UINT32 Speed:4;\r
563 UINT32 RsvdZ1:1;\r
564 UINT32 MTT:1;\r
565 UINT32 Hub:1;\r
566 UINT32 ContextEntries:5;\r
567\r
568 UINT32 MaxExitLatency:16;\r
569 UINT32 RootHubPortNum:8;\r
570 UINT32 PortNum:8;\r
571\r
572 UINT32 TTHubSlotId:8;\r
573 UINT32 TTPortNum:8;\r
574 UINT32 TTT:2;\r
575 UINT32 RsvdZ2:4;\r
576 UINT32 InterTarget:10;\r
577\r
578 UINT32 DeviceAddress:8;\r
579 UINT32 RsvdZ3:19;\r
580 UINT32 SlotState:5;\r
581\r
582 UINT32 RsvdZ4;\r
583 UINT32 RsvdZ5;\r
584 UINT32 RsvdZ6;\r
585 UINT32 RsvdZ7;\r
586} SLOT_CONTEXT;\r
587\r
588//\r
589// 6.2.3 Endpoint Context\r
590//\r
591typedef struct _ENDPOINT_CONTEXT {\r
592 UINT32 EPState:3;\r
593 UINT32 RsvdZ1:5;\r
594 UINT32 Mult:2;\r
595 UINT32 MaxPStreams:5;\r
596 UINT32 LSA:1;\r
597 UINT32 Interval:8;\r
598 UINT32 RsvdZ2:8;\r
599\r
600 UINT32 RsvdZ3:1;\r
601 UINT32 CErr:2;\r
602 UINT32 EPType:3;\r
603 UINT32 RsvdZ4:1;\r
604 UINT32 HID:1;\r
605 UINT32 MaxBurstSize:8;\r
606 UINT32 MaxPacketSize:16;\r
607\r
608 UINT32 PtrLo;\r
609\r
610 UINT32 PtrHi;\r
611\r
612 UINT32 AverageTRBLength:16;\r
613 UINT32 MaxESITPayload:16;\r
614\r
615 UINT32 RsvdZ5;\r
616 UINT32 RsvdZ6;\r
617 UINT32 RsvdZ7;\r
618} ENDPOINT_CONTEXT;\r
619\r
620//\r
621// 6.2.5.1 Input Control Context\r
622//\r
623typedef struct _INPUT_CONTRL_CONTEXT {\r
624 UINT32 Dword1;\r
625 UINT32 Dword2;\r
626 UINT32 RsvdZ1;\r
627 UINT32 RsvdZ2;\r
628 UINT32 RsvdZ3;\r
629 UINT32 RsvdZ4;\r
630 UINT32 RsvdZ5;\r
631 UINT32 RsvdZ6;\r
632} INPUT_CONTRL_CONTEXT;\r
633\r
634//\r
635// 6.2.1 Device Context\r
636//\r
637typedef struct _DEVICE_CONTEXT {\r
638 SLOT_CONTEXT Slot;\r
639 ENDPOINT_CONTEXT EP[31];\r
640} DEVICE_CONTEXT;\r
641\r
642//\r
643// 6.2.5 Input Context\r
644//\r
645typedef struct _INPUT_CONTEXT {\r
646 INPUT_CONTRL_CONTEXT InputControlContext;\r
647 SLOT_CONTEXT Slot;\r
648 ENDPOINT_CONTEXT EP[31];\r
649} INPUT_CONTEXT;\r
650\r
651/**\r
652 Initialize the XHCI host controller for schedule.\r
653\r
654 @param Xhc The XHCI device to be initialized.\r
655\r
656**/\r
657VOID\r
658XhcInitSched (\r
659 IN USB_XHCI_DEV *Xhc\r
660 );\r
661\r
662/**\r
663 Free the resouce allocated at initializing schedule.\r
664\r
665 @param Xhc The XHCI device.\r
666\r
667**/\r
668VOID\r
669XhcFreeSched (\r
670 IN USB_XHCI_DEV *Xhc\r
671 );\r
672\r
673/**\r
674 Ring the door bell to notify XHCI there is a transaction to be executed through URB.\r
675\r
676 @param Xhc The XHCI device.\r
677 @param Urb The URB to be rung.\r
678\r
679 @retval EFI_SUCCESS Successfully ring the door bell.\r
680\r
681**/\r
682EFI_STATUS\r
683RingIntTransferDoorBell (\r
684 IN USB_XHCI_DEV *Xhc,\r
685 IN URB *Urb\r
686 );\r
687\r
688/**\r
689 Execute the transfer by polling the URB. This is a synchronous operation.\r
690\r
691 @param Xhc The XHCI device.\r
692 @param CmdTransfer The executed URB is for cmd transfer or not.\r
693 @param Urb The URB to execute.\r
694 @param TimeOut The time to wait before abort, in millisecond.\r
695\r
696 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r
697 @return EFI_TIMEOUT The transfer failed due to time out.\r
698 @return EFI_SUCCESS The transfer finished OK.\r
699\r
700**/\r
701EFI_STATUS\r
702XhcExecTransfer (\r
703 IN USB_XHCI_DEV *Xhc,\r
704 IN BOOLEAN CmdTransfer,\r
705 IN URB *Urb,\r
706 IN UINTN TimeOut\r
707 );\r
708\r
709/**\r
710 Delete a single asynchronous interrupt transfer for\r
711 the device and endpoint.\r
712\r
713 @param Xhc The XHCI device.\r
714 @param DevAddr The address of the target device.\r
715 @param EpNum The endpoint of the target.\r
716\r
717 @retval EFI_SUCCESS An asynchronous transfer is removed.\r
718 @retval EFI_NOT_FOUND No transfer for the device is found.\r
719\r
720**/\r
721EFI_STATUS\r
722XhciDelAsyncIntTransfer (\r
723 IN USB_XHCI_DEV *Xhc,\r
724 IN UINT8 DevAddr,\r
725 IN UINT8 EpNum\r
726 );\r
727\r
728/**\r
729 Remove all the asynchronous interrupt transfers.\r
730\r
731 @param Xhc The XHCI device.\r
732\r
733**/\r
734VOID\r
735XhciDelAllAsyncIntTransfers (\r
736 IN USB_XHCI_DEV *Xhc\r
737 );\r
738\r
739/**\r
740 Set Bios Ownership\r
741\r
742 @param Xhc The XHCI device.\r
743\r
744**/\r
745VOID\r
746XhcSetBiosOwnership (\r
747 IN USB_XHCI_DEV *Xhc\r
748 );\r
749\r
750/**\r
751 Clear Bios Ownership\r
752\r
753 @param Xhc The XHCI device.\r
754\r
755**/\r
756VOID\r
757XhcClearBiosOwnership (\r
758 IN USB_XHCI_DEV *Xhc\r
759 );\r
760\r
761/**\r
762 Find out the slot id according to device address assigned by XHCI's Address_Device cmd.\r
763\r
764 @param DevAddr The device address of the target device.\r
765\r
766 @return The slot id used by the device.\r
767\r
768**/\r
769UINT8\r
770XhcDevAddrToSlotId (\r
771 IN UINT8 DevAddr\r
772 );\r
773\r
774/**\r
775 Find out the slot id according to the device's route string.\r
776\r
777 @param RouteString The route string described the device location.\r
778\r
779 @return The slot id used by the device.\r
780\r
781**/\r
782UINT8\r
783EFIAPI\r
784XhcRouteStringToSlotId (\r
785 IN USB_DEV_ROUTE RouteString\r
786 );\r
787\r
788/**\r
789 Calculate the device context index by endpoint address and direction.\r
790\r
791 @param EpAddr The target endpoint number.\r
792 @param Direction The direction of the target endpoint.\r
793\r
794 @return The device context index of endpoint.\r
795\r
796**/\r
797UINT8\r
798XhcEndpointToDci (\r
799 IN UINT8 EpAddr,\r
800 IN UINT8 Direction\r
801 );\r
802\r
803/**\r
804 Ring the door bell to notify XHCI there is a transaction to be executed.\r
805\r
806 @param Xhc The XHCI device.\r
807 @param SlotId The slot id of the target device.\r
808 @param Dci The device context index of the target slot or endpoint.\r
809\r
810 @retval EFI_SUCCESS Successfully ring the door bell.\r
811\r
812**/\r
813EFI_STATUS\r
814EFIAPI\r
815XhcRingDoorBell (\r
816 IN USB_XHCI_DEV *Xhc,\r
817 IN UINT8 SlotId,\r
818 IN UINT8 Dci\r
819 );\r
820\r
821/**\r
822 Interrupt transfer periodic check handler.\r
823\r
824 @param Event Interrupt event.\r
825 @param Context Pointer to USB_XHCI_DEV.\r
826\r
827**/\r
828VOID\r
829EFIAPI\r
830XhcMonitorAsyncRequests (\r
831 IN EFI_EVENT Event,\r
832 IN VOID *Context\r
833 );\r
834\r
835/**\r
836 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.\r
837\r
838 @param Xhc The XHCI device.\r
839 @param ParentRouteChart The route string pointed to the parent device if it exists.\r
840 @param Port The port to be polled.\r
841 @param PortState The port state.\r
842\r
843 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.\r
844 @retval Others Should not appear.\r
845\r
846**/\r
847EFI_STATUS\r
848EFIAPI\r
849XhcPollPortStatusChange (\r
850 IN USB_XHCI_DEV* Xhc,\r
851 IN USB_DEV_ROUTE ParentRouteChart,\r
852 IN UINT8 Port,\r
853 IN EFI_USB_PORT_STATUS *PortState\r
854 );\r
855\r
856/**\r
857 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
858\r
859 @param Xhc The XHCI device.\r
860 @param SlotId The slot id to be configured.\r
861 @param PortNum The total number of downstream port supported by the hub.\r
862 @param TTT The TT think time of the hub device.\r
863 @param MTT The multi-TT of the hub device.\r
864\r
865 @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r
866\r
867**/\r
868EFI_STATUS\r
869XhcConfigHubContext (\r
870 IN USB_XHCI_DEV *Xhc,\r
871 IN UINT8 SlotId,\r
872 IN UINT8 PortNum,\r
873 IN UINT8 TTT,\r
874 IN UINT8 MTT\r
875 );\r
876\r
877/**\r
878 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
879\r
880 @param Xhc The XHCI device.\r
881 @param SlotId The slot id to be configured.\r
882 @param DeviceSpeed The device's speed.\r
883 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
884\r
885 @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
886\r
887**/\r
888EFI_STATUS\r
889EFIAPI\r
890XhcSetConfigCmd (\r
891 IN USB_XHCI_DEV *Xhc,\r
892 IN UINT8 SlotId,\r
893 IN UINT8 DeviceSpeed,\r
894 IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
895 );\r
896\r
897/**\r
898 Find out the actual device address according to the requested device address from UsbBus.\r
899\r
900 @param BusDevAddr The requested device address by UsbBus upper driver.\r
901\r
902 @return The actual device address assigned to the device.\r
903\r
904**/\r
905UINT8\r
906EFIAPI\r
907XhcBusDevAddrToSlotId (\r
908 IN UINT8 BusDevAddr\r
909 );\r
910\r
911/**\r
912 Assign and initialize the device slot for a new device.\r
913\r
914 @param Xhc The XHCI device.\r
915 @param ParentRouteChart The route string pointed to the parent device.\r
916 @param ParentPort The port at which the device is located.\r
917 @param RouteChart The route string pointed to the device.\r
918 @param DeviceSpeed The device speed.\r
919\r
920 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r
921\r
922**/\r
923EFI_STATUS\r
924EFIAPI\r
925XhcInitializeDeviceSlot (\r
926 IN USB_XHCI_DEV *Xhc,\r
927 IN USB_DEV_ROUTE ParentRouteChart,\r
928 IN UINT16 ParentPort,\r
929 IN USB_DEV_ROUTE RouteChart,\r
930 IN UINT8 DeviceSpeed\r
931 );\r
932\r
933/**\r
934 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
935\r
936 @param Xhc The XHCI device.\r
937 @param SlotId The slot id to be evaluated.\r
938 @param MaxPacketSize The max packet size supported by the device control transfer.\r
939\r
940 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r
941\r
942**/\r
943EFI_STATUS\r
944EFIAPI\r
945XhcEvaluateContext (\r
946 IN USB_XHCI_DEV *Xhc,\r
947 IN UINT8 SlotId,\r
948 IN UINT32 MaxPacketSize\r
949 );\r
950\r
951/**\r
952 Disable the specified device slot.\r
953\r
954 @param Xhc The XHCI device.\r
955 @param SlotId The slot id to be disabled.\r
956\r
957 @retval EFI_SUCCESS Successfully disable the device slot.\r
958\r
959**/\r
960EFI_STATUS\r
961EFIAPI\r
962XhcDisableSlotCmd (\r
963 IN USB_XHCI_DEV *Xhc,\r
964 IN UINT8 SlotId\r
965 );\r
966\r
967/**\r
968 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r
969\r
970 @param Xhc The XHCI device.\r
971 @param TrsRing The transfer ring to sync.\r
972\r
973 @retval EFI_SUCCESS The transfer ring is synchronized successfully.\r
974\r
975**/\r
976EFI_STATUS\r
977EFIAPI\r
978XhcSyncTrsRing (\r
979 IN USB_XHCI_DEV *Xhc,\r
980 TRANSFER_RING *TrsRing\r
981 );\r
982\r
983/**\r
984 Synchronize the specified event ring to update the enqueue and dequeue pointer.\r
985\r
986 @param Xhc The XHCI device.\r
987 @param EvtRing The event ring to sync.\r
988\r
989 @retval EFI_SUCCESS The event ring is synchronized successfully.\r
990\r
991**/\r
992EFI_STATUS\r
993EFIAPI\r
994XhcSyncEventRing (\r
995 IN USB_XHCI_DEV *Xhc,\r
996 EVENT_RING *EvtRing\r
997 );\r
998\r
999/**\r
1000 Check if there is a new generated event.\r
1001\r
1002 @param Xhc The XHCI device.\r
1003 @param EvtRing The event ring to check.\r
1004 @param NewEvtTrb The new event TRB found.\r
1005\r
1006 @retval EFI_SUCCESS Found a new event TRB at the event ring.\r
1007 @retval EFI_NOT_READY The event ring has no new event.\r
1008\r
1009**/\r
1010EFI_STATUS\r
1011EFIAPI\r
1012XhcCheckNewEvent (\r
1013 IN USB_XHCI_DEV *Xhc,\r
1014 IN EVENT_RING *EvtRing,\r
1015 OUT TRB **NewEvtTrb\r
1016 );\r
1017\r
1018/**\r
1019 Create XHCI transfer ring.\r
1020\r
1021 @param Xhc The XHCI device.\r
1022 @param TrbNum The number of TRB in the ring.\r
1023 @param TransferRing The created transfer ring.\r
1024\r
1025**/\r
1026VOID\r
1027CreateTransferRing (\r
1028 IN USB_XHCI_DEV *Xhc,\r
1029 IN UINTN TrbNum,\r
1030 OUT TRANSFER_RING *TransferRing\r
1031 );\r
1032\r
1033/**\r
1034 Create XHCI event ring.\r
1035\r
1036 @param Xhc The XHCI device.\r
1037 @param EventInterrupter The interrupter of event.\r
1038 @param EventRing The created event ring.\r
1039\r
1040**/\r
1041VOID\r
1042CreateEventRing (\r
1043 IN USB_XHCI_DEV *Xhc,\r
1044 IN UINT8 EventInterrupter,\r
1045 OUT EVENT_RING *EventRing\r
1046 );\r
1047\r
1048/**\r
1049 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted\r
1050 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint\r
1051 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is\r
1052 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the\r
1053 Stopped to the Running state.\r
1054\r
1055 @param Xhc The XHCI device.\r
1056 @param Urb The urb which makes the endpoint halted.\r
1057\r
1058 @retval EFI_SUCCESS The recovery is successful.\r
1059 @retval Others Failed to recovery halted endpoint.\r
1060\r
1061**/\r
1062EFI_STATUS\r
1063EFIAPI\r
1064XhcRecoverHaltedEndpoint (\r
1065 IN USB_XHCI_DEV *Xhc,\r
1066 IN URB *Urb\r
1067 );\r
1068\r
1069/**\r
1070 Create a new URB for a new transaction.\r
1071\r
1072 @param Xhc The XHCI device\r
1073 @param DevAddr The device address\r
1074 @param EpAddr Endpoint addrress\r
1075 @param DevSpeed The device speed\r
1076 @param MaxPacket The max packet length of the endpoint\r
1077 @param Type The transaction type\r
1078 @param Request The standard USB request for control transfer\r
1079 @param Data The user data to transfer\r
1080 @param DataLen The length of data buffer\r
1081 @param Callback The function to call when data is transferred\r
1082 @param Context The context to the callback\r
1083\r
1084 @return Created URB or NULL\r
1085\r
1086**/\r
1087URB*\r
1088XhcCreateUrb (\r
1089 IN USB_XHCI_DEV *Xhc,\r
1090 IN UINT8 DevAddr,\r
1091 IN UINT8 EpAddr,\r
1092 IN UINT8 DevSpeed,\r
1093 IN UINTN MaxPacket,\r
1094 IN UINTN Type,\r
1095 IN EFI_USB_DEVICE_REQUEST *Request,\r
1096 IN VOID *Data,\r
1097 IN UINTN DataLen,\r
1098 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
1099 IN VOID *Context\r
1100 );\r
1101\r
1102/**\r
1103 Create a transfer TRB.\r
1104\r
1105 @param Xhc The XHCI device\r
1106 @param Urb The urb used to construct the transfer TRB.\r
1107\r
1108 @return Created TRB or NULL\r
1109\r
1110**/\r
1111EFI_STATUS\r
1112XhcCreateTransferTrb (\r
1113 IN USB_XHCI_DEV *Xhc,\r
1114 IN URB *Urb\r
1115 );\r
1116\r
1117#endif\r
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