[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhcPeim.h

/** @file\r
Private Header file for Usb Host Controller PEIM\r
\r
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
of the BSD License which accompanies this distribution.  The\r
full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _RECOVERY_XHC_H_\r
#define _RECOVERY_XHC_H_\r
\r
#include <PiPei.h>\r
\r
#include <Ppi/UsbController.h>\r
#include <Ppi/Usb2HostController.h>\r
#include <Ppi/IoMmu.h>\r
#include <Ppi/EndOfPeiPhase.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/TimerLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
\r
typedef struct _PEI_XHC_DEV PEI_XHC_DEV;\r
typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;\r
\r
#include "UsbHcMem.h"\r
#include "XhciReg.h"\r
#include "XhciSched.h"\r
\r
#define CMD_RING_TRB_NUMBER         0x100\r
#define TR_RING_TRB_NUMBER          0x100\r
#define ERST_NUMBER                 0x01\r
#define EVENT_RING_TRB_NUMBER       0x200\r
\r
#define XHC_1_MICROSECOND           1\r
#define XHC_1_MILLISECOND           (1000 * XHC_1_MICROSECOND)\r
#define XHC_1_SECOND                (1000 * XHC_1_MILLISECOND)\r
\r
//\r
// XHC reset timeout experience values.\r
// The unit is millisecond, setting it as 1s.\r
//\r
#define XHC_RESET_TIMEOUT           (1000)\r
\r
//\r
// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.\r
// The unit is microsecond, setting it as 10ms.\r
//\r
#define XHC_RESET_RECOVERY_DELAY     (10 * 1000)\r
\r
//\r
// Wait for root port state stable.\r
//\r
#define XHC_ROOT_PORT_STATE_STABLE  (200 * XHC_1_MILLISECOND)\r
\r
//\r
// XHC generic timeout experience values.\r
// The unit is millisecond, setting it as 10s.\r
//\r
#define XHC_GENERIC_TIMEOUT         (10 * 1000)\r
\r
#define XHC_LOW_32BIT(Addr64)       ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r
#define XHC_HIGH_32BIT(Addr64)      ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r
#define XHC_BIT_IS_SET(Data, Bit)   ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
\r
#define XHC_REG_BIT_IS_SET(XHC, Offset, Bit) \\r
          (XHC_BIT_IS_SET(XhcPeiReadOpReg ((XHC), (Offset)), (Bit)))\r
\r
#define USB_DESC_TYPE_HUB              0x29\r
#define USB_DESC_TYPE_HUB_SUPER_SPEED  0x2a\r
\r
//\r
// The RequestType in EFI_USB_DEVICE_REQUEST is composed of\r
// three fields: One bit direction, 2 bit type, and 5 bit\r
// target.\r
//\r
#define USB_REQUEST_TYPE(Dir, Type, Target) \\r
          ((UINT8)((((Dir) == EfiUsbDataIn ? 0x01 : 0) << 7) | (Type) | (Target)))\r
\r
struct _USB_DEV_CONTEXT {\r
  //\r
  // Whether this entry in UsbDevContext array is used or not.\r
  //\r
  BOOLEAN                           Enabled;\r
  //\r
  // The slot id assigned to the new device through XHCI's Enable_Slot cmd.\r
  //\r
  UINT8                             SlotId;\r
  //\r
  // The route string presented an attached usb device.\r
  //\r
  USB_DEV_ROUTE                     RouteString;\r
  //\r
  // The route string of parent device if it exists. Otherwise it's zero.\r
  //\r
  USB_DEV_ROUTE                     ParentRouteString;\r
  //\r
  // The actual device address assigned by XHCI through Address_Device command.\r
  //\r
  UINT8                             XhciDevAddr;\r
  //\r
  // The requested device address from UsbBus driver through Set_Address standard usb request.\r
  // As XHCI spec replaces this request with Address_Device command, we have to record the\r
  // requested device address and establish a mapping relationship with the actual device address.\r
  // Then UsbBus driver just need to be aware of the requested device address to access usb device\r
  // through EFI_USB2_HC_PROTOCOL. Xhci driver would be responsible for translating it to actual\r
  // device address and access the actual device.\r
  //\r
  UINT8                             BusDevAddr;\r
  //\r
  // The pointer to the input device context.\r
  //\r
  VOID                              *InputContext;\r
  //\r
  // The pointer to the output device context.\r
  //\r
  VOID                              *OutputContext;\r
  //\r
  // The transfer queue for every endpoint.\r
  //\r
  VOID                              *EndpointTransferRing[31];\r
  //\r
  // The device descriptor which is stored to support XHCI's Evaluate_Context cmd.\r
  //\r
  EFI_USB_DEVICE_DESCRIPTOR         DevDesc;\r
  //\r
  // As a usb device may include multiple configuration descriptors, we dynamically allocate an array\r
  // to store them.\r
  // Note that every configuration descriptor stored here includes those lower level descriptors,\r
  // such as Interface descriptor, Endpoint descriptor, and so on.\r
  // These information is used to support XHCI's Config_Endpoint cmd.\r
  //\r
  EFI_USB_CONFIG_DESCRIPTOR         **ConfDesc;\r
};\r
\r
#define USB_XHC_DEV_SIGNATURE       SIGNATURE_32 ('x', 'h', 'c', 'i')\r
\r
struct _PEI_XHC_DEV {\r
  UINTN                             Signature;\r
  PEI_USB2_HOST_CONTROLLER_PPI      Usb2HostControllerPpi;\r
  EFI_PEI_PPI_DESCRIPTOR            PpiDescriptor;\r
  UINT32                            UsbHostControllerBaseAddress;\r
  USBHC_MEM_POOL                    *MemPool;\r
\r
  //\r
  // EndOfPei callback is used to stop the XHC DMA operation\r
  // after exit PEI phase.\r
  //\r
  EFI_PEI_NOTIFY_DESCRIPTOR         EndOfPeiNotifyList;\r
\r
  //\r
  // XHCI configuration data\r
  //\r
  UINT8                             CapLength;    ///< Capability Register Length\r
  XHC_HCSPARAMS1                    HcSParams1;   ///< Structural Parameters 1\r
  XHC_HCSPARAMS2                    HcSParams2;   ///< Structural Parameters 2\r
  XHC_HCCPARAMS                     HcCParams;    ///< Capability Parameters\r
  UINT32                            DBOff;        ///< Doorbell Offset\r
  UINT32                            RTSOff;       ///< Runtime Register Space Offset\r
  UINT32                            PageSize;\r
  UINT32                            MaxScratchpadBufs;\r
  UINT64                            *ScratchBuf;\r
  VOID                              *ScratchMap;\r
  UINT64                            *ScratchEntry;\r
  UINTN                             *ScratchEntryMap;\r
  UINT64                            *DCBAA;\r
  UINT32                            MaxSlotsEn;\r
  //\r
  // Cmd Transfer Ring\r
  //\r
  TRANSFER_RING                     CmdRing;\r
  //\r
  // EventRing\r
  //\r
  EVENT_RING                        EventRing;\r
\r
  //\r
  // Store device contexts managed by XHCI device\r
  // The array supports up to 255 devices, entry 0 is reserved and should not be used.\r
  //\r
  USB_DEV_CONTEXT                   UsbDevContext[256];\r
};\r
\r
#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a) CR (a, PEI_XHC_DEV, Usb2HostControllerPpi, USB_XHC_DEV_SIGNATURE)\r
#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_XHC_DEV, EndOfPeiNotifyList, USB_XHC_DEV_SIGNATURE)\r
\r
/**\r
  Initialize the memory management pool for the host controller.\r
\r
  @return Pointer to the allocated memory pool or NULL if failed.\r
\r
**/\r
USBHC_MEM_POOL *\r
UsbHcInitMemPool (\r
  VOID\r
  )\r
;\r
\r
/**\r
  Release the memory management pool.\r
\r
  @param  Pool          The USB memory pool to free.\r
\r
**/\r
VOID\r
UsbHcFreeMemPool (\r
  IN USBHC_MEM_POOL     *Pool\r
  )\r
;\r
\r
/**\r
  Allocate some memory from the host controller's memory pool\r
  which can be used to communicate with host controller.\r
\r
  @param  Pool          The host controller's memory pool.\r
  @param  Size          Size of the memory to allocate.\r
\r
  @return The allocated memory or NULL.\r
\r
**/\r
VOID *\r
UsbHcAllocateMem (\r
  IN USBHC_MEM_POOL     *Pool,\r
  IN UINTN              Size\r
  )\r
;\r
\r
/**\r
  Free the allocated memory back to the memory pool.\r
\r
  @param  Pool          The memory pool of the host controller.\r
  @param  Mem           The memory to free.\r
  @param  Size          The size of the memory to free.\r
\r
**/\r
VOID\r
UsbHcFreeMem (\r
  IN USBHC_MEM_POOL     *Pool,\r
  IN VOID               *Mem,\r
  IN UINTN              Size\r
  )\r
;\r
\r
\r
/**\r
  Initialize IOMMU.\r
**/\r
VOID\r
IoMmuInit (\r
  VOID\r
  );\r
\r
/**\r
  Provides the controller-specific addresses required to access system memory from a\r
  DMA bus master.\r
\r
  @param  Operation             Indicates if the bus master is going to read or write to system memory.\r
  @param  HostAddress           The system memory address to map to the PCI controller.\r
  @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes\r
                                that were mapped.\r
  @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to\r
                                access the hosts HostAddress.\r
  @param  Mapping               A resulting value to pass to Unmap().\r
\r
  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.\r
  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.\r
\r
**/\r
EFI_STATUS\r
IoMmuMap (\r
  IN  EDKII_IOMMU_OPERATION Operation,\r
  IN  VOID                  *HostAddress,\r
  IN  OUT UINTN             *NumberOfBytes,\r
  OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,\r
  OUT VOID                  **Mapping\r
  );\r
\r
/**\r
  Completes the Map() operation and releases any corresponding resources.\r
\r
  @param  Mapping               The mapping value returned from Map().\r
\r
  @retval EFI_SUCCESS           The range was unmapped.\r
  @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
  @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.\r
**/\r
EFI_STATUS\r
IoMmuUnmap (\r
  IN VOID                  *Mapping\r
  );\r
\r
/**\r
  Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r
  OperationBusMasterCommonBuffer64 mapping.\r
\r
  @param  Pages                 The number of pages to allocate.\r
  @param  HostAddress           A pointer to store the base system memory address of the\r
                                allocated range.\r
  @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to\r
                                access the hosts HostAddress.\r
  @param  Mapping               A resulting value to pass to Unmap().\r
\r
  @retval EFI_SUCCESS           The requested memory pages were allocated.\r
  @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are\r
                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.\r
\r
**/\r
EFI_STATUS\r
IoMmuAllocateBuffer (\r
  IN UINTN                  Pages,\r
  OUT VOID                  **HostAddress,\r
  OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,\r
  OUT VOID                  **Mapping\r
  );\r
\r
/**\r
  Frees memory that was allocated with AllocateBuffer().\r
\r
  @param  Pages                 The number of pages to free.\r
  @param  HostAddress           The base system memory address of the allocated range.\r
  @param  Mapping               The mapping value returned from Map().\r
\r
  @retval EFI_SUCCESS           The requested memory pages were freed.\r
  @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
                                was not allocated with AllocateBuffer().\r
\r
**/\r
EFI_STATUS\r
IoMmuFreeBuffer (\r
  IN UINTN                  Pages,\r
  IN VOID                   *HostAddress,\r
  IN VOID                   *Mapping\r
  );\r
\r
#endif\r
Commit	Line	Data
d987459f SZ	1	/** @file\r
	2	Private Header file for Usb Host Controller PEIM\r
	3	\r
26b85012	4	Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r
d987459f SZ	5	\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions\r
	8	of the BSD License which accompanies this distribution. The\r
	9	full text of the license may be found at\r
	10	http://opensource.org/licenses/bsd-license.php\r
	11	\r
	12	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	\r
	15	**/\r
	16	\r
	17	#ifndef _RECOVERY_XHC_H_\r
	18	#define _RECOVERY_XHC_H_\r
	19	\r
	20	#include <PiPei.h>\r
	21	\r
	22	#include <Ppi/UsbController.h>\r
	23	#include <Ppi/Usb2HostController.h>\r
b575ca32 JY	24	#include <Ppi/IoMmu.h>\r
b575ca32 JY	25	#include <Ppi/EndOfPeiPhase.h>\r
d987459f SZ	26	\r
	27	#include <Library/DebugLib.h>\r
	28	#include <Library/PeimEntryPoint.h>\r
	29	#include <Library/PeiServicesLib.h>\r
	30	#include <Library/BaseMemoryLib.h>\r
	31	#include <Library/TimerLib.h>\r
	32	#include <Library/IoLib.h>\r
	33	#include <Library/MemoryAllocationLib.h>\r
	34	\r
	35	typedef struct _PEI_XHC_DEV PEI_XHC_DEV;\r
	36	typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;\r
	37	\r
	38	#include "UsbHcMem.h"\r
	39	#include "XhciReg.h"\r
	40	#include "XhciSched.h"\r
	41	\r
	42	#define CMD_RING_TRB_NUMBER 0x100\r
	43	#define TR_RING_TRB_NUMBER 0x100\r
	44	#define ERST_NUMBER 0x01\r
	45	#define EVENT_RING_TRB_NUMBER 0x200\r
	46	\r
	47	#define XHC_1_MICROSECOND 1\r
	48	#define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND)\r
	49	#define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)\r
	50	\r
	51	//\r
	52	// XHC reset timeout experience values.\r
26cd2d6d	53	// The unit is millisecond, setting it as 1s.\r
d987459f	54	//\r
26cd2d6d	55	#define XHC_RESET_TIMEOUT (1000)\r
d987459f	56	\r
26b85012 FT	57	//\r
	58	// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.\r
	59	// The unit is microsecond, setting it as 10ms.\r
	60	//\r
	61	#define XHC_RESET_RECOVERY_DELAY (10 * 1000)\r
	62	\r
d987459f SZ	63	//\r
	64	// Wait for root port state stable.\r
	65	//\r
	66	#define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)\r
	67	\r
26cd2d6d FT	68	//\r
	69	// XHC generic timeout experience values.\r
	70	// The unit is millisecond, setting it as 10s.\r
	71	//\r
	72	#define XHC_GENERIC_TIMEOUT (10 * 1000)\r
d987459f SZ	73	\r
	74	#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r
	75	#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r
	76	#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
	77	\r
	78	#define XHC_REG_BIT_IS_SET(XHC, Offset, Bit) \\r
	79	(XHC_BIT_IS_SET(XhcPeiReadOpReg ((XHC), (Offset)), (Bit)))\r
	80	\r
	81	#define USB_DESC_TYPE_HUB 0x29\r
	82	#define USB_DESC_TYPE_HUB_SUPER_SPEED 0x2a\r
	83	\r
	84	//\r
	85	// The RequestType in EFI_USB_DEVICE_REQUEST is composed of\r
	86	// three fields: One bit direction, 2 bit type, and 5 bit\r
	87	// target.\r
	88	//\r
	89	#define USB_REQUEST_TYPE(Dir, Type, Target) \\r
	90	((UINT8)((((Dir) == EfiUsbDataIn ? 0x01 : 0) << 7) \| (Type) \| (Target)))\r
	91	\r
	92	struct _USB_DEV_CONTEXT {\r
	93	//\r
	94	// Whether this entry in UsbDevContext array is used or not.\r
	95	//\r
	96	BOOLEAN Enabled;\r
	97	//\r
	98	// The slot id assigned to the new device through XHCI's Enable_Slot cmd.\r
	99	//\r
	100	UINT8 SlotId;\r
	101	//\r
	102	// The route string presented an attached usb device.\r
	103	//\r
	104	USB_DEV_ROUTE RouteString;\r
	105	//\r
	106	// The route string of parent device if it exists. Otherwise it's zero.\r
	107	//\r
	108	USB_DEV_ROUTE ParentRouteString;\r
	109	//\r
	110	// The actual device address assigned by XHCI through Address_Device command.\r
	111	//\r
	112	UINT8 XhciDevAddr;\r
	113	//\r
	114	// The requested device address from UsbBus driver through Set_Address standard usb request.\r
	115	// As XHCI spec replaces this request with Address_Device command, we have to record the\r
	116	// requested device address and establish a mapping relationship with the actual device address.\r
	117	// Then UsbBus driver just need to be aware of the requested device address to access usb device\r
	118	// through EFI_USB2_HC_PROTOCOL. Xhci driver would be responsible for translating it to actual\r
	119	// device address and access the actual device.\r
	120	//\r
	121	UINT8 BusDevAddr;\r
	122	//\r
	123	// The pointer to the input device context.\r
	124	//\r
	125	VOID *InputContext;\r
	126	//\r
	127	// The pointer to the output device context.\r
	128	//\r
	129	VOID *OutputContext;\r
	130	//\r
	131	// The transfer queue for every endpoint.\r
	132	//\r
	133	VOID *EndpointTransferRing[31];\r
	134	//\r
	135	// The device descriptor which is stored to support XHCI's Evaluate_Context cmd.\r
	136	//\r
137	EFI_USB_DEVICE_DESCRIPTOR DevDesc;\r
138	//\r
139	// As a usb device may include multiple configuration descriptors, we dynamically allocate an array\r
140	// to store them.\r
141	// Note that every configuration descriptor stored here includes those lower level descriptors,\r
142	// such as Interface descriptor, Endpoint descriptor, and so on.\r
143	// These information is used to support XHCI's Config_Endpoint cmd.\r
144	//\r
145	EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;\r
146	};\r
147	\r
148	#define USB_XHC_DEV_SIGNATURE SIGNATURE_32 ('x', 'h', 'c', 'i')\r
149	\r
150	struct _PEI_XHC_DEV {\r
151	UINTN Signature;\r
152	PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;\r
153	EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;\r
154	UINT32 UsbHostControllerBaseAddress;\r
155	USBHC_MEM_POOL *MemPool;\r
156	\r
b575ca32 JY	157	//\r
	158	// EndOfPei callback is used to stop the XHC DMA operation\r
	159	// after exit PEI phase.\r
	160	//\r
	161	EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;\r
	162	\r
d987459f SZ	163	//\r
	164	// XHCI configuration data\r
	165	//\r
	166	UINT8 CapLength; ///< Capability Register Length\r
	167	XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1\r
	168	XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2\r
	169	XHC_HCCPARAMS HcCParams; ///< Capability Parameters\r
	170	UINT32 DBOff; ///< Doorbell Offset\r
	171	UINT32 RTSOff; ///< Runtime Register Space Offset\r
	172	UINT32 PageSize;\r
	173	UINT32 MaxScratchpadBufs;\r
	174	UINT64 *ScratchBuf;\r
b575ca32	175	VOID *ScratchMap;\r
d987459f	176	UINT64 *ScratchEntry;\r
b575ca32	177	UINTN *ScratchEntryMap;\r
d987459f SZ	178	UINT64 *DCBAA;\r
	179	UINT32 MaxSlotsEn;\r
	180	//\r
	181	// Cmd Transfer Ring\r
	182	//\r
	183	TRANSFER_RING CmdRing;\r
	184	//\r
	185	// EventRing\r
	186	//\r
	187	EVENT_RING EventRing;\r
	188	\r
	189	//\r
	190	// Store device contexts managed by XHCI device\r
	191	// The array supports up to 255 devices, entry 0 is reserved and should not be used.\r
	192	//\r
	193	USB_DEV_CONTEXT UsbDevContext[256];\r
	194	};\r
	195	\r
	196	#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a) CR (a, PEI_XHC_DEV, Usb2HostControllerPpi, USB_XHC_DEV_SIGNATURE)\r
b575ca32	197	#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_XHC_DEV, EndOfPeiNotifyList, USB_XHC_DEV_SIGNATURE)\r
d987459f SZ	198	\r
	199	/**\r
	200	Initialize the memory management pool for the host controller.\r
	201	\r
	202	@return Pointer to the allocated memory pool or NULL if failed.\r
	203	\r
	204	**/\r
	205	USBHC_MEM_POOL *\r
	206	UsbHcInitMemPool (\r
	207	VOID\r
	208	)\r
	209	;\r
	210	\r
	211	/**\r
	212	Release the memory management pool.\r
	213	\r
	214	@param Pool The USB memory pool to free.\r
	215	\r
	216	**/\r
	217	VOID\r
	218	UsbHcFreeMemPool (\r
	219	IN USBHC_MEM_POOL *Pool\r
	220	)\r
	221	;\r
	222	\r
	223	/**\r
	224	Allocate some memory from the host controller's memory pool\r
	225	which can be used to communicate with host controller.\r
	226	\r
	227	@param Pool The host controller's memory pool.\r
	228	@param Size Size of the memory to allocate.\r
	229	\r
	230	@return The allocated memory or NULL.\r
	231	\r
	232	**/\r
	233	VOID *\r
	234	UsbHcAllocateMem (\r
	235	IN USBHC_MEM_POOL *Pool,\r
	236	IN UINTN Size\r
	237	)\r
	238	;\r
	239	\r
	240	/**\r
	241	Free the allocated memory back to the memory pool.\r
	242	\r
	243	@param Pool The memory pool of the host controller.\r
	244	@param Mem The memory to free.\r
	245	@param Size The size of the memory to free.\r
	246	\r
	247	**/\r
	248	VOID\r
	249	UsbHcFreeMem (\r
	250	IN USBHC_MEM_POOL *Pool,\r
	251	IN VOID *Mem,\r
	252	IN UINTN Size\r
	253	)\r
	254	;\r
	255	\r
b575ca32 JY	256	\r
	257	/**\r
	258	Initialize IOMMU.\r
	259	**/\r
	260	VOID\r
	261	IoMmuInit (\r
	262	VOID\r
	263	);\r
	264	\r
	265	/**\r
	266	Provides the controller-specific addresses required to access system memory from a\r
	267	DMA bus master.\r
	268	\r
	269	@param Operation Indicates if the bus master is going to read or write to system memory.\r
	270	@param HostAddress The system memory address to map to the PCI controller.\r
	271	@param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
	272	that were mapped.\r
	273	@param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
	274	access the hosts HostAddress.\r
	275	@param Mapping A resulting value to pass to Unmap().\r
	276	\r
	277	@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
	278	@retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
	279	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	280	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
	281	@retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
	282	\r
	283	**/\r
	284	EFI_STATUS\r
	285	IoMmuMap (\r
	286	IN EDKII_IOMMU_OPERATION Operation,\r
	287	IN VOID *HostAddress,\r
	288	IN OUT UINTN *NumberOfBytes,\r
	289	OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
	290	OUT VOID **Mapping\r
	291	);\r
	292	\r
	293	/**\r
	294	Completes the Map() operation and releases any corresponding resources.\r
	295	\r
	296	@param Mapping The mapping value returned from Map().\r
	297	\r
	298	@retval EFI_SUCCESS The range was unmapped.\r
	299	@retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
	300	@retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
	301	**/\r
	302	EFI_STATUS\r
	303	IoMmuUnmap (\r
	304	IN VOID *Mapping\r
	305	);\r
	306	\r
	307	/**\r
	308	Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r
	309	OperationBusMasterCommonBuffer64 mapping.\r
	310	\r
	311	@param Pages The number of pages to allocate.\r
	312	@param HostAddress A pointer to store the base system memory address of the\r
	313	allocated range.\r
	314	@param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
	315	access the hosts HostAddress.\r
	316	@param Mapping A resulting value to pass to Unmap().\r
	317	\r
	318	@retval EFI_SUCCESS The requested memory pages were allocated.\r
	319	@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
320	MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
321	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
322	@retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
323	\r
324	**/\r
325	EFI_STATUS\r
326	IoMmuAllocateBuffer (\r
327	IN UINTN Pages,\r
328	OUT VOID **HostAddress,\r
329	OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
330	OUT VOID **Mapping\r
331	);\r
332	\r
333	/**\r
334	Frees memory that was allocated with AllocateBuffer().\r
335	\r
336	@param Pages The number of pages to free.\r
337	@param HostAddress The base system memory address of the allocated range.\r
338	@param Mapping The mapping value returned from Map().\r
339	\r
340	@retval EFI_SUCCESS The requested memory pages were freed.\r
341	@retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
342	was not allocated with AllocateBuffer().\r
343	\r
344	**/\r
345	EFI_STATUS\r
346	IoMmuFreeBuffer (\r
347	IN UINTN Pages,\r
348	IN VOID *HostAddress,\r
349	IN VOID *Mapping\r
350	);\r
351	\r
d987459f	352	#endif\r