[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhciSched.c

/** @file\r
PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid\r
which is used to enable recovery function from USB Drivers.\r
\r
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
of the BSD License which accompanies this distribution.  The\r
full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "XhcPeim.h"\r
\r
/**\r
  Create a command transfer TRB to support XHCI command interfaces.\r
\r
  @param  Xhc       The XHCI device.\r
  @param  CmdTrb    The cmd TRB to be executed.\r
\r
  @return Created URB or NULL.\r
\r
**/\r
URB*\r
XhcPeiCreateCmdTrb (\r
  IN PEI_XHC_DEV    *Xhc,\r
  IN TRB_TEMPLATE   *CmdTrb\r
  )\r
{\r
  URB   *Urb;\r
\r
  Urb = AllocateZeroPool (sizeof (URB));\r
  if (Urb == NULL) {\r
    return NULL;\r
  }\r
\r
  Urb->Signature  = XHC_URB_SIG;\r
\r
  Urb->Ring       = &Xhc->CmdRing;\r
  XhcPeiSyncTrsRing (Xhc, Urb->Ring);\r
  Urb->TrbNum     = 1;\r
  Urb->TrbStart   = Urb->Ring->RingEnqueue;\r
  CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));\r
  Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;\r
  Urb->TrbEnd             = Urb->TrbStart;\r
\r
  return Urb;\r
}\r
\r
/**\r
  Execute a XHCI cmd TRB pointed by CmdTrb.\r
\r
  @param  Xhc                   The XHCI device.\r
  @param  CmdTrb                The cmd TRB to be executed.\r
  @param  Timeout               Indicates the maximum time, in millisecond, which the\r
                                transfer is allowed to complete.\r
  @param  EvtTrb                The event TRB corresponding to the cmd TRB.\r
\r
  @retval EFI_SUCCESS           The transfer was completed successfully.\r
  @retval EFI_INVALID_PARAMETER Some parameters are invalid.\r
  @retval EFI_TIMEOUT           The transfer failed due to timeout.\r
  @retval EFI_DEVICE_ERROR      The transfer failed due to host controller error.\r
\r
**/\r
EFI_STATUS\r
XhcPeiCmdTransfer (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN TRB_TEMPLATE               *CmdTrb,\r
  IN UINTN                      Timeout,\r
  OUT TRB_TEMPLATE              **EvtTrb\r
  )\r
{\r
  EFI_STATUS    Status;\r
  URB           *Urb;\r
\r
  //\r
  // Validate the parameters\r
  //\r
  if ((Xhc == NULL) || (CmdTrb == NULL)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Status = EFI_DEVICE_ERROR;\r
\r
  if (XhcPeiIsHalt (Xhc) || XhcPeiIsSysError (Xhc)) {\r
    DEBUG ((EFI_D_ERROR, "XhcPeiCmdTransfer: HC is halted or has system error\n"));\r
    goto ON_EXIT;\r
  }\r
\r
  //\r
  // Create a new URB, then poll the execution status.\r
  //\r
  Urb = XhcPeiCreateCmdTrb (Xhc, CmdTrb);\r
  if (Urb == NULL) {\r
    DEBUG ((EFI_D_ERROR, "XhcPeiCmdTransfer: failed to create URB\n"));\r
    Status = EFI_OUT_OF_RESOURCES;\r
    goto ON_EXIT;\r
  }\r
\r
  Status  = XhcPeiExecTransfer (Xhc, TRUE, Urb, Timeout);\r
  *EvtTrb = Urb->EvtTrb;\r
\r
  if (Urb->Result == EFI_USB_NOERROR) {\r
    Status = EFI_SUCCESS;\r
  }\r
\r
  XhcPeiFreeUrb (Xhc, Urb);\r
\r
ON_EXIT:\r
  return Status;\r
}\r
\r
/**\r
  Create a new URB for a new transaction.\r
\r
  @param  Xhc       The XHCI device\r
  @param  BusAddr   The logical device address assigned by UsbBus driver\r
  @param  EpAddr    Endpoint addrress\r
  @param  DevSpeed  The device speed\r
  @param  MaxPacket The max packet length of the endpoint\r
  @param  Type      The transaction type\r
  @param  Request   The standard USB request for control transfer\r
  @param  Data      The user data to transfer\r
  @param  DataLen   The length of data buffer\r
  @param  Callback  The function to call when data is transferred\r
  @param  Context   The context to the callback\r
\r
  @return Created URB or NULL\r
\r
**/\r
URB*\r
XhcPeiCreateUrb (\r
  IN PEI_XHC_DEV                        *Xhc,\r
  IN UINT8                              BusAddr,\r
  IN UINT8                              EpAddr,\r
  IN UINT8                              DevSpeed,\r
  IN UINTN                              MaxPacket,\r
  IN UINTN                              Type,\r
  IN EFI_USB_DEVICE_REQUEST             *Request,\r
  IN VOID                               *Data,\r
  IN UINTN                              DataLen,\r
  IN EFI_ASYNC_USB_TRANSFER_CALLBACK    Callback,\r
  IN VOID                               *Context\r
  )\r
{\r
  USB_ENDPOINT      *Ep;\r
  EFI_STATUS        Status;\r
  URB               *Urb;\r
\r
  Urb = AllocateZeroPool (sizeof (URB));\r
  if (Urb == NULL) {\r
    return NULL;\r
  }\r
\r
  Urb->Signature = XHC_URB_SIG;\r
\r
  Ep            = &Urb->Ep;\r
  Ep->BusAddr   = BusAddr;\r
  Ep->EpAddr    = (UINT8) (EpAddr & 0x0F);\r
  Ep->Direction = ((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;\r
  Ep->DevSpeed  = DevSpeed;\r
  Ep->MaxPacket = MaxPacket;\r
  Ep->Type      = Type;\r
\r
  Urb->Request  = Request;\r
  Urb->Data     = Data;\r
  Urb->DataLen  = DataLen;\r
  Urb->Callback = Callback;\r
  Urb->Context  = Context;\r
\r
  Status = XhcPeiCreateTransferTrb (Xhc, Urb);\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcPeiCreateUrb: XhcPeiCreateTransferTrb Failed, Status = %r\n", Status));\r
    FreePool (Urb);\r
    Urb = NULL;\r
  }\r
\r
  return Urb;\r
}\r
\r
/**\r
  Free an allocated URB.\r
\r
  @param  Xhc       The XHCI device.\r
  @param  Urb       The URB to free.\r
\r
**/\r
VOID\r
XhcPeiFreeUrb (\r
  IN PEI_XHC_DEV    *Xhc,\r
  IN URB            *Urb\r
  )\r
{\r
  if ((Xhc == NULL) || (Urb == NULL)) {\r
    return;\r
  }\r
\r
  FreePool (Urb);\r
}\r
\r
/**\r
  Create a transfer TRB.\r
\r
  @param  Xhc       The XHCI device\r
  @param  Urb       The urb used to construct the transfer TRB.\r
\r
  @return Created TRB or NULL\r
\r
**/\r
EFI_STATUS\r
XhcPeiCreateTransferTrb (\r
  IN PEI_XHC_DEV    *Xhc,\r
  IN URB            *Urb\r
  )\r
{\r
  VOID                          *OutputContext;\r
  TRANSFER_RING                 *EPRing;\r
  UINT8                         EPType;\r
  UINT8                         SlotId;\r
  UINT8                         Dci;\r
  TRB                           *TrbStart;\r
  UINTN                         TotalLen;\r
  UINTN                         Len;\r
  UINTN                         TrbNum;\r
\r
  SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r
  if (SlotId == 0) {\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  Urb->Finished  = FALSE;\r
  Urb->StartDone = FALSE;\r
  Urb->EndDone   = FALSE;\r
  Urb->Completed = 0;\r
  Urb->Result    = EFI_USB_NOERROR;\r
\r
  Dci       = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
  EPRing    = (TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];\r
  Urb->Ring = EPRing;\r
  OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
  if (Xhc->HcCParams.Data.Csz == 0) {\r
    EPType  = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;\r
  } else {\r
    EPType  = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;\r
  }\r
\r
  Urb->DataPhy = Urb->Data;\r
\r
  //\r
  // Construct the TRB\r
  //\r
  XhcPeiSyncTrsRing (Xhc, EPRing);\r
  Urb->TrbStart = EPRing->RingEnqueue;\r
  switch (EPType) {\r
    case ED_CONTROL_BIDIR:\r
      //\r
      // For control transfer, create SETUP_STAGE_TRB first.\r
      //\r
      TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;\r
      TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;\r
      TrbStart->TrbCtrSetup.bRequest      = Urb->Request->Request;\r
      TrbStart->TrbCtrSetup.wValue        = Urb->Request->Value;\r
      TrbStart->TrbCtrSetup.wIndex        = Urb->Request->Index;\r
      TrbStart->TrbCtrSetup.wLength       = Urb->Request->Length;\r
      TrbStart->TrbCtrSetup.Length        = 8;\r
      TrbStart->TrbCtrSetup.IntTarget     = 0;\r
      TrbStart->TrbCtrSetup.IOC           = 1;\r
      TrbStart->TrbCtrSetup.IDT           = 1;\r
      TrbStart->TrbCtrSetup.Type          = TRB_TYPE_SETUP_STAGE;\r
      if (Urb->Ep.Direction == EfiUsbDataIn) {\r
        TrbStart->TrbCtrSetup.TRT = 3;\r
      } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r
        TrbStart->TrbCtrSetup.TRT = 2;\r
      } else {\r
        TrbStart->TrbCtrSetup.TRT = 0;\r
      }\r
      //\r
      // Update the cycle bit\r
      //\r
      TrbStart->TrbCtrSetup.CycleBit = EPRing->RingPCS & BIT0;\r
      Urb->TrbNum++;\r
\r
      //\r
      // For control transfer, create DATA_STAGE_TRB.\r
      //\r
      if (Urb->DataLen > 0) {\r
        XhcPeiSyncTrsRing (Xhc, EPRing);\r
        TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;\r
        TrbStart->TrbCtrData.TRBPtrLo  = XHC_LOW_32BIT (Urb->DataPhy);\r
        TrbStart->TrbCtrData.TRBPtrHi  = XHC_HIGH_32BIT (Urb->DataPhy);\r
        TrbStart->TrbCtrData.Length    = (UINT32) Urb->DataLen;\r
        TrbStart->TrbCtrData.TDSize    = 0;\r
        TrbStart->TrbCtrData.IntTarget = 0;\r
        TrbStart->TrbCtrData.ISP       = 1;\r
        TrbStart->TrbCtrData.IOC       = 1;\r
        TrbStart->TrbCtrData.IDT       = 0;\r
        TrbStart->TrbCtrData.CH        = 0;\r
        TrbStart->TrbCtrData.Type      = TRB_TYPE_DATA_STAGE;\r
        if (Urb->Ep.Direction == EfiUsbDataIn) {\r
          TrbStart->TrbCtrData.DIR = 1;\r
        } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r
          TrbStart->TrbCtrData.DIR = 0;\r
        } else {\r
          TrbStart->TrbCtrData.DIR = 0;\r
        }\r
        //\r
        // Update the cycle bit\r
        //\r
        TrbStart->TrbCtrData.CycleBit = EPRing->RingPCS & BIT0;\r
        Urb->TrbNum++;\r
      }\r
      //\r
      // For control transfer, create STATUS_STAGE_TRB.\r
      // Get the pointer to next TRB for status stage use\r
      //\r
      XhcPeiSyncTrsRing (Xhc, EPRing);\r
      TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;\r
      TrbStart->TrbCtrStatus.IntTarget = 0;\r
      TrbStart->TrbCtrStatus.IOC       = 1;\r
      TrbStart->TrbCtrStatus.CH        = 0;\r
      TrbStart->TrbCtrStatus.Type      = TRB_TYPE_STATUS_STAGE;\r
      if (Urb->Ep.Direction == EfiUsbDataIn) {\r
        TrbStart->TrbCtrStatus.DIR = 0;\r
      } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r
        TrbStart->TrbCtrStatus.DIR = 1;\r
      } else {\r
        TrbStart->TrbCtrStatus.DIR = 0;\r
      }\r
      //\r
      // Update the cycle bit\r
      //\r
      TrbStart->TrbCtrStatus.CycleBit = EPRing->RingPCS & BIT0;\r
      //\r
      // Update the enqueue pointer\r
      //\r
      XhcPeiSyncTrsRing (Xhc, EPRing);\r
      Urb->TrbNum++;\r
      Urb->TrbEnd = (TRB_TEMPLATE *) (UINTN) TrbStart;\r
\r
      break;\r
\r
    case ED_BULK_OUT:\r
    case ED_BULK_IN:\r
      TotalLen = 0;\r
      Len      = 0;\r
      TrbNum   = 0;\r
      TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;\r
      while (TotalLen < Urb->DataLen) {\r
        if ((TotalLen + 0x10000) >= Urb->DataLen) {\r
          Len = Urb->DataLen - TotalLen;\r
        } else {\r
          Len = 0x10000;\r
        }\r
        TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
        TrbStart->TrbNormal.TRBPtrLo  = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
        TrbStart->TrbNormal.TRBPtrHi  = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
        TrbStart->TrbNormal.Length    = (UINT32) Len;\r
        TrbStart->TrbNormal.TDSize    = 0;\r
        TrbStart->TrbNormal.IntTarget = 0;\r
        TrbStart->TrbNormal.ISP       = 1;\r
        TrbStart->TrbNormal.IOC       = 1;\r
        TrbStart->TrbNormal.Type      = TRB_TYPE_NORMAL;\r
        //\r
        // Update the cycle bit\r
        //\r
        TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;\r
\r
        XhcPeiSyncTrsRing (Xhc, EPRing);\r
        TrbNum++;\r
        TotalLen += Len;\r
      }\r
\r
      Urb->TrbNum = TrbNum;\r
      Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;\r
      break;\r
\r
    case ED_INTERRUPT_OUT:\r
    case ED_INTERRUPT_IN:\r
      TotalLen = 0;\r
      Len      = 0;\r
      TrbNum   = 0;\r
      TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;\r
      while (TotalLen < Urb->DataLen) {\r
        if ((TotalLen + 0x10000) >= Urb->DataLen) {\r
          Len = Urb->DataLen - TotalLen;\r
        } else {\r
          Len = 0x10000;\r
        }\r
        TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
        TrbStart->TrbNormal.TRBPtrLo  = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
        TrbStart->TrbNormal.TRBPtrHi  = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
        TrbStart->TrbNormal.Length    = (UINT32) Len;\r
        TrbStart->TrbNormal.TDSize    = 0;\r
        TrbStart->TrbNormal.IntTarget = 0;\r
        TrbStart->TrbNormal.ISP       = 1;\r
        TrbStart->TrbNormal.IOC       = 1;\r
        TrbStart->TrbNormal.Type      = TRB_TYPE_NORMAL;\r
        //\r
        // Update the cycle bit\r
        //\r
        TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;\r
\r
        XhcPeiSyncTrsRing (Xhc, EPRing);\r
        TrbNum++;\r
        TotalLen += Len;\r
      }\r
\r
      Urb->TrbNum = TrbNum;\r
      Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;\r
      break;\r
\r
    default:\r
      DEBUG ((EFI_D_INFO, "Not supported EPType 0x%x!\n",EPType));\r
      ASSERT (FALSE);\r
      break;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted\r
  condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint\r
  Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is\r
  reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the\r
  Stopped to the Running state.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Urb           The urb which makes the endpoint halted.\r
\r
  @retval EFI_SUCCESS   The recovery is successful.\r
  @retval Others        Failed to recovery halted endpoint.\r
\r
**/\r
EFI_STATUS\r
XhcPeiRecoverHaltedEndpoint (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN URB                *Urb\r
  )\r
{\r
  EFI_STATUS                  Status;\r
  EVT_TRB_COMMAND_COMPLETION  *EvtTrb;\r
  CMD_TRB_RESET_ENDPOINT      CmdTrbResetED;\r
  CMD_SET_TR_DEQ_POINTER      CmdSetTRDeq;\r
  UINT8                       Dci;\r
  UINT8                       SlotId;\r
  EFI_PHYSICAL_ADDRESS        PhyAddr;\r
\r
  Status = EFI_SUCCESS;\r
  SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r
  if (SlotId == 0) {\r
    return EFI_DEVICE_ERROR;\r
  }\r
  Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8) (Urb->Ep.Direction));\r
\r
  DEBUG ((EFI_D_INFO, "XhcPeiRecoverHaltedEndpoint: Recovery Halted Slot = %x, Dci = %x\n", SlotId, Dci));\r
\r
  //\r
  // 1) Send Reset endpoint command to transit from halt to stop state\r
  //\r
  ZeroMem (&CmdTrbResetED, sizeof (CmdTrbResetED));\r
  CmdTrbResetED.CycleBit = 1;\r
  CmdTrbResetED.Type     = TRB_TYPE_RESET_ENDPOINT;\r
  CmdTrbResetED.EDID     = Dci;\r
  CmdTrbResetED.SlotId   = SlotId;\r
  Status = XhcPeiCmdTransfer (\r
             Xhc,\r
             (TRB_TEMPLATE *) (UINTN) &CmdTrbResetED,\r
             XHC_GENERIC_TIMEOUT,\r
             (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
             );\r
  if (EFI_ERROR(Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcPeiRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));\r
    goto Done;\r
  }\r
\r
  //\r
  // 2) Set dequeue pointer\r
  //\r
  ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));\r
  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));\r
  CmdSetTRDeq.PtrLo    = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;\r
  CmdSetTRDeq.PtrHi    = XHC_HIGH_32BIT (PhyAddr);\r
  CmdSetTRDeq.CycleBit = 1;\r
  CmdSetTRDeq.Type     = TRB_TYPE_SET_TR_DEQUE;\r
  CmdSetTRDeq.Endpoint = Dci;\r
  CmdSetTRDeq.SlotId   = SlotId;\r
  Status = XhcPeiCmdTransfer (\r
             Xhc,\r
             (TRB_TEMPLATE *) (UINTN) &CmdSetTRDeq,\r
             XHC_GENERIC_TIMEOUT,\r
             (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
             );\r
  if (EFI_ERROR(Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcPeiRecoverHaltedEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status));\r
    goto Done;\r
  }\r
\r
  //\r
  // 3) Ring the doorbell to transit from stop to active\r
  //\r
  XhcPeiRingDoorBell (Xhc, SlotId, Dci);\r
\r
Done:\r
  return Status;\r
}\r
\r
/**\r
  Check if the Trb is a transaction of the URB.\r
\r
  @param Trb        The TRB to be checked\r
  @param Urb        The transfer ring to be checked.\r
\r
  @retval TRUE      It is a transaction of the URB.\r
  @retval FALSE     It is not any transaction of the URB.\r
\r
**/\r
BOOLEAN\r
XhcPeiIsTransferRingTrb (\r
  IN TRB_TEMPLATE   *Trb,\r
  IN URB            *Urb\r
  )\r
{\r
  TRB_TEMPLATE  *CheckedTrb;\r
  UINTN         Index;\r
\r
  CheckedTrb = Urb->Ring->RingSeg0;\r
\r
  ASSERT (Urb->Ring->TrbNumber == CMD_RING_TRB_NUMBER || Urb->Ring->TrbNumber == TR_RING_TRB_NUMBER);\r
\r
  for (Index = 0; Index < Urb->Ring->TrbNumber; Index++) {\r
    if (Trb == CheckedTrb) {\r
      return TRUE;\r
    }\r
    CheckedTrb++;\r
  }\r
\r
  return FALSE;\r
}\r
\r
/**\r
  Check the URB's execution result and update the URB's\r
  result accordingly.\r
\r
  @param  Xhc               The XHCI device.\r
  @param  Urb               The URB to check result.\r
\r
  @return Whether the result of URB transfer is finialized.\r
\r
**/\r
BOOLEAN\r
XhcPeiCheckUrbResult (\r
  IN PEI_XHC_DEV            *Xhc,\r
  IN URB                    *Urb\r
  )\r
{\r
  EVT_TRB_TRANSFER          *EvtTrb;\r
  TRB_TEMPLATE              *TRBPtr;\r
  UINTN                     Index;\r
  UINT8                     TRBType;\r
  EFI_STATUS                Status;\r
  URB                       *CheckedUrb;\r
  UINT64                    XhcDequeue;\r
  UINT32                    High;\r
  UINT32                    Low;\r
  EFI_PHYSICAL_ADDRESS      PhyAddr;\r
\r
  ASSERT ((Xhc != NULL) && (Urb != NULL));\r
\r
  Status = EFI_SUCCESS;\r
\r
  if (Urb->Finished) {\r
    goto EXIT;\r
  }\r
\r
  EvtTrb = NULL;\r
\r
  if (XhcPeiIsHalt (Xhc) || XhcPeiIsSysError (Xhc)) {\r
    Urb->Result |= EFI_USB_ERR_SYSTEM;\r
    goto EXIT;\r
  }\r
\r
  //\r
  // Traverse the event ring to find out all new events from the previous check.\r
  //\r
  XhcPeiSyncEventRing (Xhc, &Xhc->EventRing);\r
  for (Index = 0; Index < Xhc->EventRing.TrbNumber; Index++) {\r
    Status = XhcPeiCheckNewEvent (Xhc, &Xhc->EventRing, ((TRB_TEMPLATE **) &EvtTrb));\r
    if (Status == EFI_NOT_READY) {\r
      //\r
      // All new events are handled, return directly.\r
      //\r
      goto EXIT;\r
    }\r
\r
    //\r
    // Only handle COMMAND_COMPLETETION_EVENT and TRANSFER_EVENT.\r
    //\r
    if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {\r
      continue;\r
    }\r
\r
    //\r
    // Need convert pci device address to host address\r
    //\r
    PhyAddr = (EFI_PHYSICAL_ADDRESS) (EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));\r
    TRBPtr = (TRB_TEMPLATE *) (UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *) (UINTN) PhyAddr, sizeof (TRB_TEMPLATE));\r
\r
    //\r
    // Update the status of Urb according to the finished event regardless of whether\r
    // the urb is current checked one or in the XHCI's async transfer list.\r
    // This way is used to avoid that those completed async transfer events don't get\r
    // handled in time and are flushed by newer coming events.\r
    //\r
    if (XhcPeiIsTransferRingTrb (TRBPtr, Urb)) {\r
      CheckedUrb = Urb;\r
    } else {\r
      continue;\r
    }\r
\r
    switch (EvtTrb->Completecode) {\r
      case TRB_COMPLETION_STALL_ERROR:\r
        CheckedUrb->Result  |= EFI_USB_ERR_STALL;\r
        CheckedUrb->Finished = TRUE;\r
        DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: STALL_ERROR! Completecode = %x\n", EvtTrb->Completecode));\r
        goto EXIT;\r
\r
      case TRB_COMPLETION_BABBLE_ERROR:\r
        CheckedUrb->Result  |= EFI_USB_ERR_BABBLE;\r
        CheckedUrb->Finished = TRUE;\r
        DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: BABBLE_ERROR! Completecode = %x\n", EvtTrb->Completecode));\r
        goto EXIT;\r
\r
      case TRB_COMPLETION_DATA_BUFFER_ERROR:\r
        CheckedUrb->Result  |= EFI_USB_ERR_BUFFER;\r
        CheckedUrb->Finished = TRUE;\r
        DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: ERR_BUFFER! Completecode = %x\n", EvtTrb->Completecode));\r
        goto EXIT;\r
\r
      case TRB_COMPLETION_USB_TRANSACTION_ERROR:\r
        CheckedUrb->Result  |= EFI_USB_ERR_TIMEOUT;\r
        CheckedUrb->Finished = TRUE;\r
        DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n", EvtTrb->Completecode));\r
        goto EXIT;\r
\r
      case TRB_COMPLETION_SHORT_PACKET:\r
      case TRB_COMPLETION_SUCCESS:\r
        if (EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) {\r
          DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: short packet happens!\n"));\r
        }\r
\r
        TRBType = (UINT8) (TRBPtr->Type);\r
        if ((TRBType == TRB_TYPE_DATA_STAGE) ||\r
            (TRBType == TRB_TYPE_NORMAL) ||\r
            (TRBType == TRB_TYPE_ISOCH)) {\r
          CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);\r
        }\r
\r
        break;\r
\r
      default:\r
        DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: Transfer Default Error Occur! Completecode = 0x%x!\n", EvtTrb->Completecode));\r
        CheckedUrb->Result  |= EFI_USB_ERR_TIMEOUT;\r
        CheckedUrb->Finished = TRUE;\r
        goto EXIT;\r
    }\r
\r
    //\r
    // Only check first and end Trb event address\r
    //\r
    if (TRBPtr == CheckedUrb->TrbStart) {\r
      CheckedUrb->StartDone = TRUE;\r
    }\r
\r
    if (TRBPtr == CheckedUrb->TrbEnd) {\r
      CheckedUrb->EndDone = TRUE;\r
    }\r
\r
    if (CheckedUrb->StartDone && CheckedUrb->EndDone) {\r
      CheckedUrb->Finished = TRUE;\r
      CheckedUrb->EvtTrb   = (TRB_TEMPLATE *) EvtTrb;\r
    }\r
  }\r
\r
EXIT:\r
\r
  //\r
  // Advance event ring to last available entry\r
  //\r
  // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
  // So divide it to two 32-bytes width register access.\r
  //\r
  Low  = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);\r
  High = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);\r
  XhcDequeue = (UINT64) (LShiftU64((UINT64) High, 32) | Low);\r
\r
  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));\r
\r
  if ((XhcDequeue & (~0x0F)) != (PhyAddr & (~0x0F))) {\r
    //\r
    // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
    // So divide it to two 32-bytes width register access.\r
    //\r
    XhcPeiWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, XHC_LOW_32BIT (PhyAddr) | BIT3);\r
    XhcPeiWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, XHC_HIGH_32BIT (PhyAddr));\r
  }\r
\r
  return Urb->Finished;\r
}\r
\r
/**\r
  Execute the transfer by polling the URB. This is a synchronous operation.\r
\r
  @param  Xhc               The XHCI device.\r
  @param  CmdTransfer       The executed URB is for cmd transfer or not.\r
  @param  Urb               The URB to execute.\r
  @param  Timeout           The time to wait before abort, in millisecond.\r
\r
  @return EFI_DEVICE_ERROR  The transfer failed due to transfer error.\r
  @return EFI_TIMEOUT       The transfer failed due to time out.\r
  @return EFI_SUCCESS       The transfer finished OK.\r
\r
**/\r
EFI_STATUS\r
XhcPeiExecTransfer (\r
  IN PEI_XHC_DEV            *Xhc,\r
  IN BOOLEAN                CmdTransfer,\r
  IN URB                    *Urb,\r
  IN UINTN                  Timeout\r
  )\r
{\r
  EFI_STATUS    Status;\r
  UINTN         Index;\r
  UINT64        Loop;\r
  UINT8         SlotId;\r
  UINT8         Dci;\r
  BOOLEAN       Finished;\r
\r
  if (CmdTransfer) {\r
    SlotId = 0;\r
    Dci    = 0;\r
  } else {\r
    SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r
    if (SlotId == 0) {\r
      return EFI_DEVICE_ERROR;\r
    }\r
    Dci  = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
  }\r
\r
  Status = EFI_SUCCESS;\r
  Loop   = Timeout * XHC_1_MILLISECOND;\r
  if (Timeout == 0) {\r
    Loop = 0xFFFFFFFF;\r
  }\r
\r
  XhcPeiRingDoorBell (Xhc, SlotId, Dci);\r
\r
  for (Index = 0; Index < Loop; Index++) {\r
    Finished = XhcPeiCheckUrbResult (Xhc, Urb);\r
    if (Finished) {\r
      break;\r
    }\r
    MicroSecondDelay (XHC_1_MICROSECOND);\r
  }\r
\r
  if (Index == Loop) {\r
    Urb->Result = EFI_USB_ERR_TIMEOUT;\r
    Status      = EFI_TIMEOUT;\r
  } else if (Urb->Result != EFI_USB_NOERROR) {\r
    Status      = EFI_DEVICE_ERROR;\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.\r
\r
  @param  Xhc               The XHCI device.\r
  @param  ParentRouteChart  The route string pointed to the parent device if it exists.\r
  @param  Port              The port to be polled.\r
  @param  PortState         The port state.\r
\r
  @retval EFI_SUCCESS       Successfully enable/disable device slot according to port state.\r
  @retval Others            Should not appear.\r
\r
**/\r
EFI_STATUS\r
XhcPeiPollPortStatusChange (\r
  IN PEI_XHC_DEV            *Xhc,\r
  IN USB_DEV_ROUTE          ParentRouteChart,\r
  IN UINT8                  Port,\r
  IN EFI_USB_PORT_STATUS    *PortState\r
  )\r
{\r
  EFI_STATUS        Status;\r
  UINT8             Speed;\r
  UINT8             SlotId;\r
  USB_DEV_ROUTE     RouteChart;\r
\r
  DEBUG ((EFI_D_INFO, "XhcPeiPollPortStatusChange: PortChangeStatus: %x PortStatus: %x\n", PortState->PortChangeStatus, PortState->PortStatus));\r
\r
  Status = EFI_SUCCESS;\r
\r
  if ((PortState->PortChangeStatus & (USB_PORT_STAT_C_CONNECTION | USB_PORT_STAT_C_ENABLE | USB_PORT_STAT_C_OVERCURRENT | USB_PORT_STAT_C_RESET)) == 0) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  if (ParentRouteChart.Dword == 0) {\r
    RouteChart.Route.RouteString = 0;\r
    RouteChart.Route.RootPortNum = Port + 1;\r
    RouteChart.Route.TierNum     = 1;\r
  } else {\r
    if(Port < 14) {\r
      RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (Port << (4 * (ParentRouteChart.Route.TierNum - 1)));\r
    } else {\r
      RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (15 << (4 * (ParentRouteChart.Route.TierNum - 1)));\r
    }\r
    RouteChart.Route.RootPortNum   = ParentRouteChart.Route.RootPortNum;\r
    RouteChart.Route.TierNum       = ParentRouteChart.Route.TierNum + 1;\r
  }\r
\r
  SlotId = XhcPeiRouteStringToSlotId (Xhc, RouteChart);\r
  if (SlotId != 0) {\r
    if (Xhc->HcCParams.Data.Csz == 0) {\r
      Status = XhcPeiDisableSlotCmd (Xhc, SlotId);\r
    } else {\r
      Status = XhcPeiDisableSlotCmd64 (Xhc, SlotId);\r
    }\r
  }\r
\r
  if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&\r
      ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {\r
    //\r
    // Has a device attached, Identify device speed after port is enabled.\r
    //\r
    Speed = EFI_USB_SPEED_FULL;\r
    if ((PortState->PortStatus & USB_PORT_STAT_LOW_SPEED) != 0) {\r
      Speed = EFI_USB_SPEED_LOW;\r
    } else if ((PortState->PortStatus & USB_PORT_STAT_HIGH_SPEED) != 0) {\r
      Speed = EFI_USB_SPEED_HIGH;\r
    } else if ((PortState->PortStatus & USB_PORT_STAT_SUPER_SPEED) != 0) {\r
      Speed = EFI_USB_SPEED_SUPER;\r
    }\r
    //\r
    // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.\r
    //\r
    SlotId = XhcPeiRouteStringToSlotId (Xhc, RouteChart);\r
    if ((SlotId == 0) && ((PortState->PortChangeStatus & USB_PORT_STAT_C_RESET) != 0)) {\r
      if (Xhc->HcCParams.Data.Csz == 0) {\r
        Status = XhcPeiInitializeDeviceSlot (Xhc, ParentRouteChart, Port, RouteChart, Speed);\r
      } else {\r
        Status = XhcPeiInitializeDeviceSlot64 (Xhc, ParentRouteChart, Port, RouteChart, Speed);\r
      }\r
    }\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Calculate the device context index by endpoint address and direction.\r
\r
  @param  EpAddr        The target endpoint number.\r
  @param  Direction     The direction of the target endpoint.\r
\r
  @return The device context index of endpoint.\r
\r
**/\r
UINT8\r
XhcPeiEndpointToDci (\r
  IN UINT8                      EpAddr,\r
  IN EFI_USB_DATA_DIRECTION     Direction\r
  )\r
{\r
  UINT8 Index;\r
\r
  ASSERT (EpAddr <= 15);\r
\r
  if (EpAddr == 0) {\r
    return 1;\r
  } else {\r
    Index = (UINT8) (2 * EpAddr);\r
    if (Direction == EfiUsbDataIn) {\r
      Index += 1;\r
    }\r
    return Index;\r
  }\r
}\r
\r
/**\r
  Find out the actual device address according to the requested device address from UsbBus.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  BusDevAddr    The requested device address by UsbBus upper driver.\r
\r
  @return The actual device address assigned to the device.\r
\r
**/\r
UINT8\r
XhcPeiBusDevAddrToSlotId (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT8              BusDevAddr\r
  )\r
{\r
  UINT8   Index;\r
\r
  for (Index = 0; Index < 255; Index++) {\r
    if (Xhc->UsbDevContext[Index + 1].Enabled &&\r
        (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&\r
        (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {\r
      break;\r
    }\r
  }\r
\r
  if (Index == 255) {\r
    return 0;\r
  }\r
\r
  return Xhc->UsbDevContext[Index + 1].SlotId;\r
}\r
\r
/**\r
  Find out the slot id according to the device's route string.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  RouteString   The route string described the device location.\r
\r
  @return The slot id used by the device.\r
\r
**/\r
UINT8\r
XhcPeiRouteStringToSlotId (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN USB_DEV_ROUTE      RouteString\r
  )\r
{\r
  UINT8   Index;\r
\r
  for (Index = 0; Index < 255; Index++) {\r
    if (Xhc->UsbDevContext[Index + 1].Enabled &&\r
        (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&\r
        (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {\r
      break;\r
    }\r
  }\r
\r
  if (Index == 255) {\r
    return 0;\r
  }\r
\r
  return Xhc->UsbDevContext[Index + 1].SlotId;\r
}\r
\r
/**\r
  Ring the door bell to notify XHCI there is a transaction to be executed.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id of the target device.\r
  @param  Dci           The device context index of the target slot or endpoint.\r
\r
**/\r
VOID\r
XhcPeiRingDoorBell (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT8              SlotId,\r
  IN UINT8              Dci\r
  )\r
{\r
  if (SlotId == 0) {\r
    XhcPeiWriteDoorBellReg (Xhc, 0, 0);\r
  } else {\r
    XhcPeiWriteDoorBellReg (Xhc, SlotId * sizeof (UINT32), Dci);\r
  }\r
}\r
\r
/**\r
  Assign and initialize the device slot for a new device.\r
\r
  @param  Xhc                   The XHCI device.\r
  @param  ParentRouteChart      The route string pointed to the parent device.\r
  @param  ParentPort            The port at which the device is located.\r
  @param  RouteChart            The route string pointed to the device.\r
  @param  DeviceSpeed           The device speed.\r
\r
  @retval EFI_SUCCESS           Successfully assign a slot to the device and assign an address to it.\r
  @retval Others                Fail to initialize device slot.\r
\r
**/\r
EFI_STATUS\r
XhcPeiInitializeDeviceSlot (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN USB_DEV_ROUTE              ParentRouteChart,\r
  IN UINT16                     ParentPort,\r
  IN USB_DEV_ROUTE              RouteChart,\r
  IN UINT8                      DeviceSpeed\r
  )\r
{\r
  EFI_STATUS                    Status;\r
  EVT_TRB_COMMAND_COMPLETION    *EvtTrb;\r
  INPUT_CONTEXT                 *InputContext;\r
  DEVICE_CONTEXT                *OutputContext;\r
  TRANSFER_RING                 *EndpointTransferRing;\r
  CMD_TRB_ADDRESS_DEVICE        CmdTrbAddr;\r
  UINT8                         DeviceAddress;\r
  CMD_TRB_ENABLE_SLOT           CmdTrb;\r
  UINT8                         SlotId;\r
  UINT8                         ParentSlotId;\r
  DEVICE_CONTEXT                *ParentDeviceContext;\r
  EFI_PHYSICAL_ADDRESS          PhyAddr;\r
\r
  ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));\r
  CmdTrb.CycleBit = 1;\r
  CmdTrb.Type     = TRB_TYPE_EN_SLOT;\r
\r
  Status = XhcPeiCmdTransfer (\r
             Xhc,\r
             (TRB_TEMPLATE *) (UINTN) &CmdTrb,\r
             XHC_GENERIC_TIMEOUT,\r
             (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcPeiInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));\r
    return Status;\r
  }\r
  ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);\r
  DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));\r
  SlotId = (UINT8) EvtTrb->SlotId;\r
  ASSERT (SlotId != 0);\r
\r
  ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));\r
  Xhc->UsbDevContext[SlotId].Enabled                 = TRUE;\r
  Xhc->UsbDevContext[SlotId].SlotId                  = SlotId;\r
  Xhc->UsbDevContext[SlotId].RouteString.Dword       = RouteChart.Dword;\r
  Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;\r
\r
  //\r
  // 4.3.3 Device Slot Initialization\r
  // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.\r
  //\r
  InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT));\r
  ASSERT (InputContext != NULL);\r
  ASSERT (((UINTN) InputContext & 0x3F) == 0);\r
  ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r
\r
  Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;\r
\r
  //\r
  // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1\r
  //    flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input\r
  //    Context are affected by the command.\r
  //\r
  InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);\r
\r
  //\r
  // 3) Initialize the Input Slot Context data structure\r
  //\r
  InputContext->Slot.RouteString    = RouteChart.Route.RouteString;\r
  InputContext->Slot.Speed          = DeviceSpeed + 1;\r
  InputContext->Slot.ContextEntries = 1;\r
  InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;\r
\r
  if (RouteChart.Route.RouteString != 0) {\r
    //\r
    // The device is behind of hub device.\r
    //\r
    ParentSlotId = XhcPeiRouteStringToSlotId (Xhc, ParentRouteChart);\r
    ASSERT (ParentSlotId != 0);\r
    //\r
    // If the Full/Low device attached to a High Speed Hub, init the TTPortNum and TTHubSlotId field of slot context\r
    //\r
    ParentDeviceContext = (DEVICE_CONTEXT *) Xhc->UsbDevContext[ParentSlotId].OutputContext;\r
    if ((ParentDeviceContext->Slot.TTPortNum == 0) &&\r
        (ParentDeviceContext->Slot.TTHubSlotId == 0)) {\r
      if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {\r
        //\r
        // Full/Low device attached to High speed hub port that isolates the high speed signaling\r
        // environment from Full/Low speed signaling environment for a device\r
        //\r
        InputContext->Slot.TTPortNum   = ParentPort;\r
        InputContext->Slot.TTHubSlotId = ParentSlotId;\r
      }\r
    } else {\r
      //\r
      // Inherit the TT parameters from parent device.\r
      //\r
      InputContext->Slot.TTPortNum   = ParentDeviceContext->Slot.TTPortNum;\r
      InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;\r
      //\r
      // If the device is a High speed device then down the speed to be the same as its parent Hub\r
      //\r
      if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r
        InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;\r
      }\r
    }\r
  }\r
\r
  //\r
  // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.\r
  //\r
  EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
  Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;\r
  XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r
  //\r
  // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).\r
  //\r
  InputContext->EP[0].EPType = ED_CONTROL_BIDIR;\r
\r
  if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r
    InputContext->EP[0].MaxPacketSize = 512;\r
  } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r
    InputContext->EP[0].MaxPacketSize = 64;\r
  } else {\r
    InputContext->EP[0].MaxPacketSize = 8;\r
  }\r
  //\r
  // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints\r
  // 1KB, and Bulk and Isoch endpoints 3KB.\r
  //\r
  InputContext->EP[0].AverageTRBLength = 8;\r
  InputContext->EP[0].MaxBurstSize     = 0;\r
  InputContext->EP[0].Interval         = 0;\r
  InputContext->EP[0].MaxPStreams      = 0;\r
  InputContext->EP[0].Mult             = 0;\r
  InputContext->EP[0].CErr             = 3;\r
\r
  //\r
  // Init the DCS(dequeue cycle state) as the transfer ring's CCS\r
  //\r
  PhyAddr = UsbHcGetPciAddrForHostAddr (\r
              Xhc->MemPool,\r
              ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,\r
              sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r
              );\r
  InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;\r
  InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
\r
  //\r
  // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.\r
  //\r
  OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT));\r
  ASSERT (OutputContext != NULL);\r
  ASSERT (((UINTN) OutputContext & 0x3F) == 0);\r
  ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));\r
\r
  Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;\r
  //\r
  // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with\r
  //    a pointer to the Output Device Context data structure (6.2.1).\r
  //\r
  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT));\r
  //\r
  // Fill DCBAA with PCI device address\r
  //\r
  Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;\r
\r
  //\r
  // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input\r
  //    Context data structure described above.\r
  //\r
  ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));\r
  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));\r
  CmdTrbAddr.PtrLo    = XHC_LOW_32BIT (PhyAddr);\r
  CmdTrbAddr.PtrHi    = XHC_HIGH_32BIT (PhyAddr);\r
  CmdTrbAddr.CycleBit = 1;\r
  CmdTrbAddr.Type     = TRB_TYPE_ADDRESS_DEV;\r
  CmdTrbAddr.SlotId   = Xhc->UsbDevContext[SlotId].SlotId;\r
  Status = XhcPeiCmdTransfer (\r
             Xhc,\r
             (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,\r
             XHC_GENERIC_TIMEOUT,\r
             (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
             );\r
  if (!EFI_ERROR (Status)) {\r
    DeviceAddress = (UINT8) OutputContext->Slot.DeviceAddress;\r
    DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot: Address %d assigned successfully\n", DeviceAddress));\r
    Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;\r
  }\r
\r
  DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot: Enable Slot, Status = %r\n", Status));\r
  return Status;\r
}\r
\r
/**\r
  Assign and initialize the device slot for a new device.\r
\r
  @param  Xhc                   The XHCI device.\r
  @param  ParentRouteChart      The route string pointed to the parent device.\r
  @param  ParentPort            The port at which the device is located.\r
  @param  RouteChart            The route string pointed to the device.\r
  @param  DeviceSpeed           The device speed.\r
\r
  @retval EFI_SUCCESS           Successfully assign a slot to the device and assign an address to it.\r
  @retval Others                Fail to initialize device slot.\r
\r
**/\r
EFI_STATUS\r
XhcPeiInitializeDeviceSlot64 (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN USB_DEV_ROUTE              ParentRouteChart,\r
  IN UINT16                     ParentPort,\r
  IN USB_DEV_ROUTE              RouteChart,\r
  IN UINT8                      DeviceSpeed\r
  )\r
{\r
  EFI_STATUS                    Status;\r
  EVT_TRB_COMMAND_COMPLETION    *EvtTrb;\r
  INPUT_CONTEXT_64              *InputContext;\r
  DEVICE_CONTEXT_64             *OutputContext;\r
  TRANSFER_RING                 *EndpointTransferRing;\r
  CMD_TRB_ADDRESS_DEVICE        CmdTrbAddr;\r
  UINT8                         DeviceAddress;\r
  CMD_TRB_ENABLE_SLOT           CmdTrb;\r
  UINT8                         SlotId;\r
  UINT8                         ParentSlotId;\r
  DEVICE_CONTEXT_64             *ParentDeviceContext;\r
  EFI_PHYSICAL_ADDRESS          PhyAddr;\r
\r
  ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));\r
  CmdTrb.CycleBit = 1;\r
  CmdTrb.Type     = TRB_TYPE_EN_SLOT;\r
\r
  Status = XhcPeiCmdTransfer (\r
             Xhc,\r
             (TRB_TEMPLATE *) (UINTN) &CmdTrb,\r
             XHC_GENERIC_TIMEOUT,\r
             (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcPeiInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));\r
    return Status;\r
  }\r
  ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);\r
  DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot64: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));\r
  SlotId = (UINT8)EvtTrb->SlotId;\r
  ASSERT (SlotId != 0);\r
\r
  ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));\r
  Xhc->UsbDevContext[SlotId].Enabled                 = TRUE;\r
  Xhc->UsbDevContext[SlotId].SlotId                  = SlotId;\r
  Xhc->UsbDevContext[SlotId].RouteString.Dword       = RouteChart.Dword;\r
  Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;\r
\r
  //\r
  // 4.3.3 Device Slot Initialization\r
  // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.\r
  //\r
  InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT_64));\r
  ASSERT (InputContext != NULL);\r
  ASSERT (((UINTN) InputContext & 0x3F) == 0);\r
  ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r
\r
  Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;\r
\r
  //\r
  // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1\r
  //    flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input\r
  //    Context are affected by the command.\r
  //\r
  InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);\r
\r
  //\r
  // 3) Initialize the Input Slot Context data structure\r
  //\r
  InputContext->Slot.RouteString    = RouteChart.Route.RouteString;\r
  InputContext->Slot.Speed          = DeviceSpeed + 1;\r
  InputContext->Slot.ContextEntries = 1;\r
  InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;\r
\r
  if (RouteChart.Route.RouteString != 0) {\r
    //\r
    // The device is behind of hub device.\r
    //\r
    ParentSlotId = XhcPeiRouteStringToSlotId (Xhc, ParentRouteChart);\r
    ASSERT (ParentSlotId != 0);\r
    //\r
    //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context\r
    //\r
    ParentDeviceContext = (DEVICE_CONTEXT_64 *) Xhc->UsbDevContext[ParentSlotId].OutputContext;\r
    if ((ParentDeviceContext->Slot.TTPortNum == 0) &&\r
        (ParentDeviceContext->Slot.TTHubSlotId == 0)) {\r
      if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {\r
        //\r
        // Full/Low device attached to High speed hub port that isolates the high speed signaling\r
        // environment from Full/Low speed signaling environment for a device\r
        //\r
        InputContext->Slot.TTPortNum   = ParentPort;\r
        InputContext->Slot.TTHubSlotId = ParentSlotId;\r
      }\r
    } else {\r
      //\r
      // Inherit the TT parameters from parent device.\r
      //\r
      InputContext->Slot.TTPortNum   = ParentDeviceContext->Slot.TTPortNum;\r
      InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;\r
      //\r
      // If the device is a High speed device then down the speed to be the same as its parent Hub\r
      //\r
      if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r
        InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;\r
      }\r
    }\r
  }\r
\r
  //\r
  // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.\r
  //\r
  EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
  Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;\r
  XhcPeiCreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r
  //\r
  // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).\r
  //\r
  InputContext->EP[0].EPType = ED_CONTROL_BIDIR;\r
\r
  if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r
    InputContext->EP[0].MaxPacketSize = 512;\r
  } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r
    InputContext->EP[0].MaxPacketSize = 64;\r
  } else {\r
    InputContext->EP[0].MaxPacketSize = 8;\r
  }\r
  //\r
  // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints\r
  // 1KB, and Bulk and Isoch endpoints 3KB.\r
  //\r
  InputContext->EP[0].AverageTRBLength = 8;\r
  InputContext->EP[0].MaxBurstSize     = 0;\r
  InputContext->EP[0].Interval         = 0;\r
  InputContext->EP[0].MaxPStreams      = 0;\r
  InputContext->EP[0].Mult             = 0;\r
  InputContext->EP[0].CErr             = 3;\r
\r
  //\r
  // Init the DCS(dequeue cycle state) as the transfer ring's CCS\r
  //\r
  PhyAddr = UsbHcGetPciAddrForHostAddr (\r
              Xhc->MemPool,\r
              ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,\r
              sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r
              );\r
  InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;\r
  InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
\r
  //\r
  // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.\r
  //\r
  OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT_64));\r
  ASSERT (OutputContext != NULL);\r
  ASSERT (((UINTN) OutputContext & 0x3F) == 0);\r
  ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));\r
\r
  Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;\r
  //\r
  // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with\r
  //    a pointer to the Output Device Context data structure (6.2.1).\r
  //\r
  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT_64));\r
  //\r
  // Fill DCBAA with PCI device address\r
  //\r
  Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;\r
\r
  //\r
  // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input\r
  //    Context data structure described above.\r
  //\r
  ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));\r
  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));\r
  CmdTrbAddr.PtrLo    = XHC_LOW_32BIT (PhyAddr);\r
  CmdTrbAddr.PtrHi    = XHC_HIGH_32BIT (PhyAddr);\r
  CmdTrbAddr.CycleBit = 1;\r
  CmdTrbAddr.Type     = TRB_TYPE_ADDRESS_DEV;\r
  CmdTrbAddr.SlotId   = Xhc->UsbDevContext[SlotId].SlotId;\r
  Status = XhcPeiCmdTransfer (\r
             Xhc,\r
             (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,\r
             XHC_GENERIC_TIMEOUT,\r
             (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
             );\r
  if (!EFI_ERROR (Status)) {\r
    DeviceAddress = (UINT8) OutputContext->Slot.DeviceAddress;\r
    DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot64: Address %d assigned successfully\n", DeviceAddress));\r
    Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;\r
  }\r
\r
  DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot64: Enable Slot, Status = %r\n", Status));\r
  return Status;\r
}\r
\r
\r
/**\r
  Disable the specified device slot.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be disabled.\r
\r
  @retval EFI_SUCCESS   Successfully disable the device slot.\r
\r
**/\r
EFI_STATUS\r
XhcPeiDisableSlotCmd (\r
  IN PEI_XHC_DEV               *Xhc,\r
  IN UINT8                     SlotId\r
  )\r
{\r
  EFI_STATUS            Status;\r
  TRB_TEMPLATE          *EvtTrb;\r
  CMD_TRB_DISABLE_SLOT  CmdTrbDisSlot;\r
  UINT8                 Index;\r
  VOID                  *RingSeg;\r
\r
  //\r
  // Disable the device slots occupied by these devices on its downstream ports.\r
  // Entry 0 is reserved.\r
  //\r
  for (Index = 0; Index < 255; Index++) {\r
    if (!Xhc->UsbDevContext[Index + 1].Enabled ||\r
        (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||\r
        (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {\r
      continue;\r
    }\r
\r
    Status = XhcPeiDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);\r
\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((EFI_D_ERROR, "XhcPeiDisableSlotCmd: failed to disable child, ignore error\n"));\r
      Xhc->UsbDevContext[Index + 1].SlotId = 0;\r
    }\r
  }\r
\r
  //\r
  // Construct the disable slot command\r
  //\r
  DEBUG ((EFI_D_INFO, "XhcPeiDisableSlotCmd: Disable device slot %d!\n", SlotId));\r
\r
  ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));\r
  CmdTrbDisSlot.CycleBit = 1;\r
  CmdTrbDisSlot.Type     = TRB_TYPE_DIS_SLOT;\r
  CmdTrbDisSlot.SlotId   = SlotId;\r
  Status = XhcPeiCmdTransfer (\r
             Xhc,\r
             (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,\r
             XHC_GENERIC_TIMEOUT,\r
             (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcPeiDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));\r
    return Status;\r
  }\r
  //\r
  // Free the slot's device context entry\r
  //\r
  Xhc->DCBAA[SlotId] = 0;\r
\r
  //\r
  // Free the slot related data structure\r
  //\r
  for (Index = 0; Index < 31; Index++) {\r
    if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {\r
      RingSeg = ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;\r
      if (RingSeg != NULL) {\r
        UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);\r
      }\r
      FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);\r
      Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;\r
    }\r
  }\r
\r
  for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {\r
    if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {\r
      FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);\r
    }\r
  }\r
\r
  if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {\r
    UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));\r
  }\r
\r
  if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {\r
    UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT));\r
  }\r
  //\r
  // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established\r
  // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to\r
  // remove urb from XHCI's asynchronous transfer list.\r
  //\r
  Xhc->UsbDevContext[SlotId].Enabled = FALSE;\r
  Xhc->UsbDevContext[SlotId].SlotId  = 0;\r
\r
  DEBUG ((EFI_D_INFO, "XhcPeiDisableSlotCmd: Disable Slot Command, Status = %r\n", Status));\r
  return Status;\r
}\r
\r
/**\r
  Disable the specified device slot.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be disabled.\r
\r
  @retval EFI_SUCCESS   Successfully disable the device slot.\r
\r
**/\r
EFI_STATUS\r
XhcPeiDisableSlotCmd64 (\r
  IN PEI_XHC_DEV               *Xhc,\r
  IN UINT8                     SlotId\r
  )\r
{\r
  EFI_STATUS            Status;\r
  TRB_TEMPLATE          *EvtTrb;\r
  CMD_TRB_DISABLE_SLOT  CmdTrbDisSlot;\r
  UINT8                 Index;\r
  VOID                  *RingSeg;\r
\r
  //\r
  // Disable the device slots occupied by these devices on its downstream ports.\r
  // Entry 0 is reserved.\r
  //\r
  for (Index = 0; Index < 255; Index++) {\r
    if (!Xhc->UsbDevContext[Index + 1].Enabled ||\r
        (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||\r
        (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {\r
      continue;\r
    }\r
\r
    Status = XhcPeiDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);\r
\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((EFI_D_ERROR, "XhcPeiDisableSlotCmd64: failed to disable child, ignore error\n"));\r
      Xhc->UsbDevContext[Index + 1].SlotId = 0;\r
    }\r
  }\r
\r
  //\r
  // Construct the disable slot command\r
  //\r
  DEBUG ((EFI_D_INFO, "XhcPeiDisableSlotCmd64: Disable device slot %d!\n", SlotId));\r
\r
  ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));\r
  CmdTrbDisSlot.CycleBit = 1;\r
  CmdTrbDisSlot.Type     = TRB_TYPE_DIS_SLOT;\r
  CmdTrbDisSlot.SlotId   = SlotId;\r
  Status = XhcPeiCmdTransfer (\r
             Xhc,\r
             (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,\r
             XHC_GENERIC_TIMEOUT,\r
             (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcPeiDisableSlotCmd64: Disable Slot Command Failed, Status = %r\n", Status));\r
    return Status;\r
  }\r
  //\r
  // Free the slot's device context entry\r
  //\r
  Xhc->DCBAA[SlotId] = 0;\r
\r
  //\r
  // Free the slot related data structure\r
  //\r
  for (Index = 0; Index < 31; Index++) {\r
    if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {\r
      RingSeg = ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;\r
      if (RingSeg != NULL) {\r
        UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);\r
      }\r
      FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);\r
      Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;\r
    }\r
  }\r
\r
  for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {\r
    if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {\r
      FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);\r
    }\r
  }\r
\r
  if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {\r
    UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));\r
  }\r
\r
  if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {\r
     UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));\r
  }\r
  //\r
  // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established\r
  // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to\r
  // remove urb from XHCI's asynchronous transfer list.\r
  //\r
  Xhc->UsbDevContext[SlotId].Enabled = FALSE;\r
  Xhc->UsbDevContext[SlotId].SlotId  = 0;\r
\r
  DEBUG ((EFI_D_INFO, "XhcPeiDisableSlotCmd64: Disable Slot Command, Status = %r\n", Status));\r
  return Status;\r
}\r
\r
/**\r
  Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be configured.\r
  @param  DeviceSpeed   The device's speed.\r
  @param  ConfigDesc    The pointer to the usb device configuration descriptor.\r
\r
  @retval EFI_SUCCESS   Successfully configure all the device endpoints.\r
\r
**/\r
EFI_STATUS\r
XhcPeiSetConfigCmd (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN UINT8                      SlotId,\r
  IN UINT8                      DeviceSpeed,\r
  IN USB_CONFIG_DESCRIPTOR      *ConfigDesc\r
  )\r
{\r
  EFI_STATUS                    Status;\r
  USB_INTERFACE_DESCRIPTOR      *IfDesc;\r
  USB_ENDPOINT_DESCRIPTOR       *EpDesc;\r
  UINT8                         Index;\r
  UINTN                         NumEp;\r
  UINTN                         EpIndex;\r
  UINT8                         EpAddr;\r
  EFI_USB_DATA_DIRECTION        Direction;\r
  UINT8                         Dci;\r
  UINT8                         MaxDci;\r
  EFI_PHYSICAL_ADDRESS          PhyAddr;\r
  UINT8                         Interval;\r
\r
  TRANSFER_RING                 *EndpointTransferRing;\r
  CMD_TRB_CONFIG_ENDPOINT       CmdTrbCfgEP;\r
  INPUT_CONTEXT                 *InputContext;\r
  DEVICE_CONTEXT                *OutputContext;\r
  EVT_TRB_COMMAND_COMPLETION    *EvtTrb;\r
  //\r
  // 4.6.6 Configure Endpoint\r
  //\r
  InputContext  = Xhc->UsbDevContext[SlotId].InputContext;\r
  OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
  ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r
  CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));\r
\r
  ASSERT (ConfigDesc != NULL);\r
\r
  MaxDci = 0;\r
\r
  IfDesc = (USB_INTERFACE_DESCRIPTOR *) (ConfigDesc + 1);\r
  for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {\r
    while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {\r
      IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN) IfDesc + IfDesc->Length);\r
    }\r
\r
    NumEp = IfDesc->NumEndpoints;\r
\r
    EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDesc + 1);\r
    for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r
      while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r
        EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN) EpDesc + EpDesc->Length);\r
      }\r
\r
      EpAddr    = (UINT8) (EpDesc->EndpointAddress & 0x0F);\r
      Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r
\r
      Dci = XhcPeiEndpointToDci (EpAddr, Direction);\r
      if (Dci > MaxDci) {\r
        MaxDci = Dci;\r
      }\r
\r
      InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);\r
      InputContext->EP[Dci-1].MaxPacketSize     = EpDesc->MaxPacketSize;\r
\r
      if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r
        //\r
        // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.\r
        //\r
        InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
      } else {\r
        InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
      }\r
\r
      switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {\r
        case USB_ENDPOINT_BULK:\r
          if (Direction == EfiUsbDataIn) {\r
            InputContext->EP[Dci-1].CErr   = 3;\r
            InputContext->EP[Dci-1].EPType = ED_BULK_IN;\r
          } else {\r
            InputContext->EP[Dci-1].CErr   = 3;\r
            InputContext->EP[Dci-1].EPType = ED_BULK_OUT;\r
          }\r
\r
          InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
          if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
            EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
            Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
            XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
          }\r
\r
          break;\r
        case USB_ENDPOINT_ISO:\r
          if (Direction == EfiUsbDataIn) {\r
            InputContext->EP[Dci-1].CErr   = 0;\r
            InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;\r
          } else {\r
            InputContext->EP[Dci-1].CErr   = 0;\r
            InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
          }\r
          //\r
          // Do not support isochronous transfer now.\r
          //\r
          DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd: Unsupport ISO EP found, Transfer ring is not allocated.\n"));\r
          EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
          continue;\r
        case USB_ENDPOINT_INTERRUPT:\r
          if (Direction == EfiUsbDataIn) {\r
            InputContext->EP[Dci-1].CErr   = 3;\r
            InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;\r
          } else {\r
            InputContext->EP[Dci-1].CErr   = 3;\r
            InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;\r
          }\r
          InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
          InputContext->EP[Dci-1].MaxESITPayload   = EpDesc->MaxPacketSize;\r
          //\r
          // Get the bInterval from descriptor and init the interval field of endpoint context\r
          //\r
          if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {\r
            Interval = EpDesc->Interval;\r
            //\r
            // Calculate through the bInterval field of Endpoint descriptor.\r
            //\r
            ASSERT (Interval != 0);\r
            InputContext->EP[Dci-1].Interval = (UINT32) HighBitSet32 ((UINT32) Interval) + 3;\r
          } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r
            Interval = EpDesc->Interval;\r
            ASSERT (Interval >= 1 && Interval <= 16);\r
            //\r
            // Refer to XHCI 1.0 spec section 6.2.3.6, table 61\r
            //\r
            InputContext->EP[Dci-1].Interval = Interval - 1;\r
          }\r
\r
          if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
            EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
            Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
            XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
          }\r
          break;\r
\r
        case USB_ENDPOINT_CONTROL:\r
          //\r
          // Do not support control transfer now.\r
          //\r
          DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd: Unsupport Control EP found, Transfer ring is not allocated.\n"));\r
        default:\r
          DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd: Unknown EP found, Transfer ring is not allocated.\n"));\r
          EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
          continue;\r
      }\r
\r
      PhyAddr = UsbHcGetPciAddrForHostAddr (\r
                  Xhc->MemPool,\r
                  ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,\r
                  sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r
                  );\r
      PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);\r
      PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
      InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);\r
      InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
\r
      EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN) EpDesc + EpDesc->Length);\r
    }\r
    IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN) IfDesc + IfDesc->Length);\r
  }\r
\r
  InputContext->InputControlContext.Dword2 |= BIT0;\r
  InputContext->Slot.ContextEntries         = MaxDci;\r
  //\r
  // configure endpoint\r
  //\r
  ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r
  CmdTrbCfgEP.PtrLo    = XHC_LOW_32BIT (PhyAddr);\r
  CmdTrbCfgEP.PtrHi    = XHC_HIGH_32BIT (PhyAddr);\r
  CmdTrbCfgEP.CycleBit = 1;\r
  CmdTrbCfgEP.Type     = TRB_TYPE_CON_ENDPOINT;\r
  CmdTrbCfgEP.SlotId   = Xhc->UsbDevContext[SlotId].SlotId;\r
  DEBUG ((EFI_D_INFO, "XhcSetConfigCmd: Configure Endpoint\n"));\r
  Status = XhcPeiCmdTransfer (\r
             Xhc,\r
             (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
             XHC_GENERIC_TIMEOUT,\r
             (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));\r
  }\r
  return Status;\r
}\r
\r
/**\r
  Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be configured.\r
  @param  DeviceSpeed   The device's speed.\r
  @param  ConfigDesc    The pointer to the usb device configuration descriptor.\r
\r
  @retval EFI_SUCCESS   Successfully configure all the device endpoints.\r
\r
**/\r
EFI_STATUS\r
XhcPeiSetConfigCmd64 (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN UINT8                      SlotId,\r
  IN UINT8                      DeviceSpeed,\r
  IN USB_CONFIG_DESCRIPTOR      *ConfigDesc\r
  )\r
{\r
  EFI_STATUS                    Status;\r
  USB_INTERFACE_DESCRIPTOR      *IfDesc;\r
  USB_ENDPOINT_DESCRIPTOR       *EpDesc;\r
  UINT8                         Index;\r
  UINTN                         NumEp;\r
  UINTN                         EpIndex;\r
  UINT8                         EpAddr;\r
  EFI_USB_DATA_DIRECTION        Direction;\r
  UINT8                         Dci;\r
  UINT8                         MaxDci;\r
  EFI_PHYSICAL_ADDRESS          PhyAddr;\r
  UINT8                         Interval;\r
\r
  TRANSFER_RING                 *EndpointTransferRing;\r
  CMD_TRB_CONFIG_ENDPOINT       CmdTrbCfgEP;\r
  INPUT_CONTEXT_64              *InputContext;\r
  DEVICE_CONTEXT_64             *OutputContext;\r
  EVT_TRB_COMMAND_COMPLETION    *EvtTrb;\r
  //\r
  // 4.6.6 Configure Endpoint\r
  //\r
  InputContext  = Xhc->UsbDevContext[SlotId].InputContext;\r
  OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
  ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r
  CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));\r
\r
  ASSERT (ConfigDesc != NULL);\r
\r
  MaxDci = 0;\r
\r
  IfDesc = (USB_INTERFACE_DESCRIPTOR *) (ConfigDesc + 1);\r
  for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {\r
    while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {\r
      IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN) IfDesc + IfDesc->Length);\r
    }\r
\r
    NumEp = IfDesc->NumEndpoints;\r
\r
    EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDesc + 1);\r
    for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r
      while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r
        EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN) EpDesc + EpDesc->Length);\r
      }\r
\r
      EpAddr    = (UINT8) (EpDesc->EndpointAddress & 0x0F);\r
      Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r
\r
      Dci = XhcPeiEndpointToDci (EpAddr, Direction);\r
      ASSERT (Dci < 32);\r
      if (Dci > MaxDci) {\r
        MaxDci = Dci;\r
      }\r
\r
      InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);\r
      InputContext->EP[Dci-1].MaxPacketSize     = EpDesc->MaxPacketSize;\r
\r
      if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r
        //\r
        // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.\r
        //\r
        InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
      } else {\r
        InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
      }\r
\r
      switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {\r
        case USB_ENDPOINT_BULK:\r
          if (Direction == EfiUsbDataIn) {\r
            InputContext->EP[Dci-1].CErr   = 3;\r
            InputContext->EP[Dci-1].EPType = ED_BULK_IN;\r
          } else {\r
            InputContext->EP[Dci-1].CErr   = 3;\r
            InputContext->EP[Dci-1].EPType = ED_BULK_OUT;\r
          }\r
\r
          InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
          if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
            EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
            Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
            XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
          }\r
\r
          break;\r
        case USB_ENDPOINT_ISO:\r
          if (Direction == EfiUsbDataIn) {\r
            InputContext->EP[Dci-1].CErr   = 0;\r
            InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;\r
          } else {\r
            InputContext->EP[Dci-1].CErr   = 0;\r
            InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
          }\r
          //\r
          // Do not support isochronous transfer now.\r
          //\r
          DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));\r
          EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
          continue;\r
        case USB_ENDPOINT_INTERRUPT:\r
          if (Direction == EfiUsbDataIn) {\r
            InputContext->EP[Dci-1].CErr   = 3;\r
            InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;\r
          } else {\r
            InputContext->EP[Dci-1].CErr   = 3;\r
            InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;\r
          }\r
          InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
          InputContext->EP[Dci-1].MaxESITPayload   = EpDesc->MaxPacketSize;\r
          //\r
          // Get the bInterval from descriptor and init the the interval field of endpoint context\r
          //\r
          if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {\r
            Interval = EpDesc->Interval;\r
            //\r
            // Calculate through the bInterval field of Endpoint descriptor.\r
            //\r
            ASSERT (Interval != 0);\r
            InputContext->EP[Dci-1].Interval = (UINT32) HighBitSet32( (UINT32) Interval) + 3;\r
          } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r
            Interval = EpDesc->Interval;\r
            ASSERT (Interval >= 1 && Interval <= 16);\r
            //\r
            // Refer to XHCI 1.0 spec section 6.2.3.6, table 61\r
            //\r
            InputContext->EP[Dci-1].Interval = Interval - 1;\r
          }\r
\r
          if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
            EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
            Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
            XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
          }\r
          break;\r
\r
        case USB_ENDPOINT_CONTROL:\r
          //\r
          // Do not support control transfer now.\r
          //\r
          DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd64: Unsupport Control EP found, Transfer ring is not allocated.\n"));\r
        default:\r
          DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd64: Unknown EP found, Transfer ring is not allocated.\n"));\r
          EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
          continue;\r
      }\r
\r
      PhyAddr = UsbHcGetPciAddrForHostAddr (\r
                  Xhc->MemPool,\r
                  ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,\r
                  sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r
                  );\r
\r
      PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);\r
      PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
\r
      InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);\r
      InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
\r
      EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN)EpDesc + EpDesc->Length);\r
    }\r
    IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN)IfDesc + IfDesc->Length);\r
  }\r
\r
  InputContext->InputControlContext.Dword2 |= BIT0;\r
  InputContext->Slot.ContextEntries         = MaxDci;\r
  //\r
  // configure endpoint\r
  //\r
  ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
  PhyAddr  = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r
  CmdTrbCfgEP.PtrLo    = XHC_LOW_32BIT (PhyAddr);\r
  CmdTrbCfgEP.PtrHi    = XHC_HIGH_32BIT (PhyAddr);\r
  CmdTrbCfgEP.CycleBit = 1;\r
  CmdTrbCfgEP.Type     = TRB_TYPE_CON_ENDPOINT;\r
  CmdTrbCfgEP.SlotId   = Xhc->UsbDevContext[SlotId].SlotId;\r
  DEBUG ((EFI_D_INFO, "XhcSetConfigCmd64: Configure Endpoint\n"));\r
  Status = XhcPeiCmdTransfer (\r
             Xhc,\r
             (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
             XHC_GENERIC_TIMEOUT,\r
             (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));\r
  }\r
\r
  return Status;\r
}\r
\r
\r
/**\r
  Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be evaluated.\r
  @param  MaxPacketSize The max packet size supported by the device control transfer.\r
\r
  @retval EFI_SUCCESS   Successfully evaluate the device endpoint 0.\r
\r
**/\r
EFI_STATUS\r
XhcPeiEvaluateContext (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN UINT8                      SlotId,\r
  IN UINT32                     MaxPacketSize\r
  )\r
{\r
  EFI_STATUS                    Status;\r
  CMD_TRB_EVALUATE_CONTEXT      CmdTrbEvalu;\r
  EVT_TRB_COMMAND_COMPLETION    *EvtTrb;\r
  INPUT_CONTEXT                 *InputContext;\r
  EFI_PHYSICAL_ADDRESS          PhyAddr;\r
\r
  ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
\r
  //\r
  // 4.6.7 Evaluate Context\r
  //\r
  InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
  ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r
\r
  InputContext->InputControlContext.Dword2 |= BIT1;\r
  InputContext->EP[0].MaxPacketSize         = MaxPacketSize;\r
\r
  ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));\r
  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r
  CmdTrbEvalu.PtrLo    = XHC_LOW_32BIT (PhyAddr);\r
  CmdTrbEvalu.PtrHi    = XHC_HIGH_32BIT (PhyAddr);\r
  CmdTrbEvalu.CycleBit = 1;\r
  CmdTrbEvalu.Type     = TRB_TYPE_EVALU_CONTXT;\r
  CmdTrbEvalu.SlotId   = Xhc->UsbDevContext[SlotId].SlotId;\r
  DEBUG ((EFI_D_INFO, "XhcEvaluateContext: Evaluate context\n"));\r
  Status = XhcPeiCmdTransfer (\r
             Xhc,\r
             (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,\r
             XHC_GENERIC_TIMEOUT,\r
             (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));\r
  }\r
  return Status;\r
}\r
\r
/**\r
  Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be evaluated.\r
  @param  MaxPacketSize The max packet size supported by the device control transfer.\r
\r
  @retval EFI_SUCCESS   Successfully evaluate the device endpoint 0.\r
\r
**/\r
EFI_STATUS\r
XhcPeiEvaluateContext64 (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN UINT8                      SlotId,\r
  IN UINT32                     MaxPacketSize\r
  )\r
{\r
  EFI_STATUS                    Status;\r
  CMD_TRB_EVALUATE_CONTEXT      CmdTrbEvalu;\r
  EVT_TRB_COMMAND_COMPLETION    *EvtTrb;\r
  INPUT_CONTEXT_64              *InputContext;\r
  EFI_PHYSICAL_ADDRESS          PhyAddr;\r
\r
  ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
\r
  //\r
  // 4.6.7 Evaluate Context\r
  //\r
  InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
  ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r
\r
  InputContext->InputControlContext.Dword2 |= BIT1;\r
  InputContext->EP[0].MaxPacketSize         = MaxPacketSize;\r
\r
  ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));\r
  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r
  CmdTrbEvalu.PtrLo    = XHC_LOW_32BIT (PhyAddr);\r
  CmdTrbEvalu.PtrHi    = XHC_HIGH_32BIT (PhyAddr);\r
  CmdTrbEvalu.CycleBit = 1;\r
  CmdTrbEvalu.Type     = TRB_TYPE_EVALU_CONTXT;\r
  CmdTrbEvalu.SlotId   = Xhc->UsbDevContext[SlotId].SlotId;\r
  DEBUG ((EFI_D_INFO, "XhcEvaluateContext64: Evaluate context 64\n"));\r
  Status = XhcPeiCmdTransfer (\r
             Xhc,\r
             (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,\r
             XHC_GENERIC_TIMEOUT,\r
             (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));\r
  }\r
  return Status;\r
}\r
\r
/**\r
  Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be configured.\r
  @param  PortNum       The total number of downstream port supported by the hub.\r
  @param  TTT           The TT think time of the hub device.\r
  @param  MTT           The multi-TT of the hub device.\r
\r
  @retval EFI_SUCCESS   Successfully configure the hub device's slot context.\r
\r
**/\r
EFI_STATUS\r
XhcPeiConfigHubContext (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN UINT8                      SlotId,\r
  IN UINT8                      PortNum,\r
  IN UINT8                      TTT,\r
  IN UINT8                      MTT\r
  )\r
{\r
  EFI_STATUS                    Status;\r
  EVT_TRB_COMMAND_COMPLETION    *EvtTrb;\r
  INPUT_CONTEXT                 *InputContext;\r
  DEVICE_CONTEXT                *OutputContext;\r
  CMD_TRB_CONFIG_ENDPOINT       CmdTrbCfgEP;\r
  EFI_PHYSICAL_ADDRESS          PhyAddr;\r
\r
  ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
  InputContext  = Xhc->UsbDevContext[SlotId].InputContext;\r
  OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
\r
  //\r
  // 4.6.7 Evaluate Context\r
  //\r
  ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r
\r
  InputContext->InputControlContext.Dword2 |= BIT0;\r
\r
  //\r
  // Copy the slot context from OutputContext to Input context\r
  //\r
  CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));\r
  InputContext->Slot.Hub     = 1;\r
  InputContext->Slot.PortNum = PortNum;\r
  InputContext->Slot.TTT     = TTT;\r
  InputContext->Slot.MTT     = MTT;\r
\r
  ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r
  CmdTrbCfgEP.PtrLo    = XHC_LOW_32BIT (PhyAddr);\r
  CmdTrbCfgEP.PtrHi    = XHC_HIGH_32BIT (PhyAddr);\r
  CmdTrbCfgEP.CycleBit = 1;\r
  CmdTrbCfgEP.Type     = TRB_TYPE_CON_ENDPOINT;\r
  CmdTrbCfgEP.SlotId   = Xhc->UsbDevContext[SlotId].SlotId;\r
  DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));\r
  Status = XhcPeiCmdTransfer (\r
             Xhc,\r
             (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
             XHC_GENERIC_TIMEOUT,\r
             (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));\r
  }\r
  return Status;\r
}\r
\r
/**\r
  Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be configured.\r
  @param  PortNum       The total number of downstream port supported by the hub.\r
  @param  TTT           The TT think time of the hub device.\r
  @param  MTT           The multi-TT of the hub device.\r
\r
  @retval EFI_SUCCESS   Successfully configure the hub device's slot context.\r
\r
**/\r
EFI_STATUS\r
XhcPeiConfigHubContext64 (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN UINT8                      SlotId,\r
  IN UINT8                      PortNum,\r
  IN UINT8                      TTT,\r
  IN UINT8                      MTT\r
  )\r
{\r
  EFI_STATUS                    Status;\r
  EVT_TRB_COMMAND_COMPLETION    *EvtTrb;\r
  INPUT_CONTEXT_64              *InputContext;\r
  DEVICE_CONTEXT_64             *OutputContext;\r
  CMD_TRB_CONFIG_ENDPOINT       CmdTrbCfgEP;\r
  EFI_PHYSICAL_ADDRESS          PhyAddr;\r
\r
  ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
  InputContext  = Xhc->UsbDevContext[SlotId].InputContext;\r
  OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
\r
  //\r
  // 4.6.7 Evaluate Context\r
  //\r
  ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r
\r
  InputContext->InputControlContext.Dword2 |= BIT0;\r
\r
  //\r
  // Copy the slot context from OutputContext to Input context\r
  //\r
  CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));\r
  InputContext->Slot.Hub     = 1;\r
  InputContext->Slot.PortNum = PortNum;\r
  InputContext->Slot.TTT     = TTT;\r
  InputContext->Slot.MTT     = MTT;\r
\r
  ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r
  CmdTrbCfgEP.PtrLo    = XHC_LOW_32BIT (PhyAddr);\r
  CmdTrbCfgEP.PtrHi    = XHC_HIGH_32BIT (PhyAddr);\r
  CmdTrbCfgEP.CycleBit = 1;\r
  CmdTrbCfgEP.Type     = TRB_TYPE_CON_ENDPOINT;\r
  CmdTrbCfgEP.SlotId   = Xhc->UsbDevContext[SlotId].SlotId;\r
  DEBUG ((EFI_D_INFO, "Configure Hub Slot Context 64\n"));\r
  Status = XhcPeiCmdTransfer (\r
             Xhc,\r
             (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
             XHC_GENERIC_TIMEOUT,\r
             (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));\r
  }\r
  return Status;\r
}\r
\r
/**\r
  Check if there is a new generated event.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  EvtRing       The event ring to check.\r
  @param  NewEvtTrb     The new event TRB found.\r
\r
  @retval EFI_SUCCESS   Found a new event TRB at the event ring.\r
  @retval EFI_NOT_READY The event ring has no new event.\r
\r
**/\r
EFI_STATUS\r
XhcPeiCheckNewEvent (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN EVENT_RING         *EvtRing,\r
  OUT TRB_TEMPLATE      **NewEvtTrb\r
  )\r
{\r
  ASSERT (EvtRing != NULL);\r
\r
  *NewEvtTrb = EvtRing->EventRingDequeue;\r
\r
  if (EvtRing->EventRingDequeue == EvtRing->EventRingEnqueue) {\r
    return EFI_NOT_READY;\r
  }\r
\r
  EvtRing->EventRingDequeue++;\r
  //\r
  // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.\r
  //\r
  if ((UINTN) EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {\r
    EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Synchronize the specified event ring to update the enqueue and dequeue pointer.\r
\r
  @param  Xhc       The XHCI device.\r
  @param  EvtRing   The event ring to sync.\r
\r
  @retval EFI_SUCCESS The event ring is synchronized successfully.\r
\r
**/\r
EFI_STATUS\r
XhcPeiSyncEventRing (\r
  IN PEI_XHC_DEV    *Xhc,\r
  IN EVENT_RING     *EvtRing\r
  )\r
{\r
  UINTN             Index;\r
  TRB_TEMPLATE      *EvtTrb;\r
\r
  ASSERT (EvtRing != NULL);\r
\r
  //\r
  // Calculate the EventRingEnqueue and EventRingCCS.\r
  // Note: only support single Segment\r
  //\r
  EvtTrb = EvtRing->EventRingDequeue;\r
\r
  for (Index = 0; Index < EvtRing->TrbNumber; Index++) {\r
    if (EvtTrb->CycleBit != EvtRing->EventRingCCS) {\r
      break;\r
    }\r
\r
    EvtTrb++;\r
\r
    if ((UINTN) EvtTrb >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {\r
      EvtTrb = EvtRing->EventRingSeg0;\r
      EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;\r
    }\r
  }\r
\r
  if (Index < EvtRing->TrbNumber) {\r
    EvtRing->EventRingEnqueue = EvtTrb;\r
  } else {\r
    ASSERT (FALSE);\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Free XHCI event ring.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  EventRing     The event ring to be freed.\r
\r
**/\r
VOID\r
XhcPeiFreeEventRing (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN EVENT_RING         *EventRing\r
  )\r
{\r
  if(EventRing->EventRingSeg0 == NULL) {\r
    return;\r
  }\r
\r
  //\r
  // Free EventRing Segment 0\r
  //\r
  UsbHcFreeMem (Xhc->MemPool, EventRing->EventRingSeg0, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);\r
\r
  //\r
  // Free ERST table\r
  //\r
  UsbHcFreeMem (Xhc->MemPool, EventRing->ERSTBase, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);\r
}\r
\r
/**\r
  Create XHCI event ring.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  EventRing     The created event ring.\r
\r
**/\r
VOID\r
XhcPeiCreateEventRing (\r
  IN PEI_XHC_DEV        *Xhc,\r
  OUT EVENT_RING        *EventRing\r
  )\r
{\r
  VOID                          *Buf;\r
  EVENT_RING_SEG_TABLE_ENTRY    *ERSTBase;\r
  UINTN                         Size;\r
  EFI_PHYSICAL_ADDRESS          ERSTPhy;\r
  EFI_PHYSICAL_ADDRESS          DequeuePhy;\r
\r
  ASSERT (EventRing != NULL);\r
\r
  Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;\r
  Buf = UsbHcAllocateMem (Xhc->MemPool, Size);\r
  ASSERT (Buf != NULL);\r
  ASSERT (((UINTN) Buf & 0x3F) == 0);\r
  ZeroMem (Buf, Size);\r
\r
  DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);\r
\r
  EventRing->EventRingSeg0      = Buf;\r
  EventRing->TrbNumber          = EVENT_RING_TRB_NUMBER;\r
  EventRing->EventRingDequeue   = (TRB_TEMPLATE *) EventRing->EventRingSeg0;\r
  EventRing->EventRingEnqueue   = (TRB_TEMPLATE *) EventRing->EventRingSeg0;\r
\r
  //\r
  // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'\r
  // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.\r
  //\r
  EventRing->EventRingCCS = 1;\r
\r
  Size = sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER;\r
  Buf = UsbHcAllocateMem (Xhc->MemPool, Size);\r
  ASSERT (Buf != NULL);\r
  ASSERT (((UINTN) Buf & 0x3F) == 0);\r
  ZeroMem (Buf, Size);\r
\r
  ERSTBase              = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;\r
  EventRing->ERSTBase   = ERSTBase;\r
  ERSTBase->PtrLo       = XHC_LOW_32BIT (DequeuePhy);\r
  ERSTBase->PtrHi       = XHC_HIGH_32BIT (DequeuePhy);\r
  ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;\r
\r
  ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);\r
\r
  //\r
  // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)\r
  //\r
  XhcPeiWriteRuntimeReg (\r
    Xhc,\r
    XHC_ERSTSZ_OFFSET,\r
    ERST_NUMBER\r
    );\r
  //\r
  // Program the Interrupter Event Ring Dequeue Pointer (ERDP) register (5.5.2.3.3)\r
  //\r
  // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
  // So divide it to two 32-bytes width register access.\r
  //\r
  XhcPeiWriteRuntimeReg (\r
    Xhc,\r
    XHC_ERDP_OFFSET,\r
    XHC_LOW_32BIT ((UINT64) (UINTN) DequeuePhy)\r
    );\r
  XhcPeiWriteRuntimeReg (\r
    Xhc,\r
    XHC_ERDP_OFFSET + 4,\r
    XHC_HIGH_32BIT ((UINT64) (UINTN) DequeuePhy)\r
    );\r
  //\r
  // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register (5.5.2.3.2)\r
  //\r
  // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
  // So divide it to two 32-bytes width register access.\r
  //\r
  XhcPeiWriteRuntimeReg (\r
    Xhc,\r
    XHC_ERSTBA_OFFSET,\r
    XHC_LOW_32BIT ((UINT64) (UINTN) ERSTPhy)\r
    );\r
  XhcPeiWriteRuntimeReg (\r
    Xhc,\r
    XHC_ERSTBA_OFFSET + 4,\r
    XHC_HIGH_32BIT ((UINT64) (UINTN) ERSTPhy)\r
    );\r
  //\r
  // Need set IMAN IE bit to enable the ring interrupt\r
  //\r
  XhcPeiSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET, XHC_IMAN_IE);\r
}\r
\r
/**\r
  Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r
\r
  @param  Xhc       The XHCI device.\r
  @param  TrsRing   The transfer ring to sync.\r
\r
  @retval EFI_SUCCESS The transfer ring is synchronized successfully.\r
\r
**/\r
EFI_STATUS\r
XhcPeiSyncTrsRing (\r
  IN PEI_XHC_DEV    *Xhc,\r
  IN TRANSFER_RING  *TrsRing\r
  )\r
{\r
  UINTN             Index;\r
  TRB_TEMPLATE      *TrsTrb;\r
\r
  ASSERT (TrsRing != NULL);\r
  //\r
  // Calculate the latest RingEnqueue and RingPCS\r
  //\r
  TrsTrb = TrsRing->RingEnqueue;\r
  ASSERT (TrsTrb != NULL);\r
\r
  for (Index = 0; Index < TrsRing->TrbNumber; Index++) {\r
    if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {\r
      break;\r
    }\r
    TrsTrb++;\r
    if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {\r
      ASSERT (((LINK_TRB *) TrsTrb)->TC != 0);\r
      //\r
      // set cycle bit in Link TRB as normal\r
      //\r
      ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;\r
      //\r
      // Toggle PCS maintained by software\r
      //\r
      TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;\r
      TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0;  // Use host address\r
    }\r
  }\r
\r
  ASSERT (Index != TrsRing->TrbNumber);\r
\r
  if (TrsTrb != TrsRing->RingEnqueue) {\r
    TrsRing->RingEnqueue = TrsTrb;\r
  }\r
\r
  //\r
  // Clear the Trb context for enqueue, but reserve the PCS bit\r
  //\r
  TrsTrb->Parameter1 = 0;\r
  TrsTrb->Parameter2 = 0;\r
  TrsTrb->Status     = 0;\r
  TrsTrb->RsvdZ1     = 0;\r
  TrsTrb->Type       = 0;\r
  TrsTrb->Control    = 0;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Create XHCI transfer ring.\r
\r
  @param  Xhc               The XHCI Device.\r
  @param  TrbNum            The number of TRB in the ring.\r
  @param  TransferRing      The created transfer ring.\r
\r
**/\r
VOID\r
XhcPeiCreateTransferRing (\r
  IN PEI_XHC_DEV            *Xhc,\r
  IN UINTN                  TrbNum,\r
  OUT TRANSFER_RING         *TransferRing\r
  )\r
{\r
  VOID                  *Buf;\r
  LINK_TRB              *EndTrb;\r
  EFI_PHYSICAL_ADDRESS  PhyAddr;\r
\r
  Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);\r
  ASSERT (Buf != NULL);\r
  ASSERT (((UINTN) Buf & 0x3F) == 0);\r
  ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);\r
\r
  TransferRing->RingSeg0     = Buf;\r
  TransferRing->TrbNumber    = TrbNum;\r
  TransferRing->RingEnqueue  = (TRB_TEMPLATE *) TransferRing->RingSeg0;\r
  TransferRing->RingDequeue  = (TRB_TEMPLATE *) TransferRing->RingSeg0;\r
  TransferRing->RingPCS      = 1;\r
  //\r
  // 4.9.2 Transfer Ring Management\r
  // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to\r
  // point to the first TRB in the ring.\r
  //\r
  EndTrb        = (LINK_TRB *) ((UINTN) Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));\r
  EndTrb->Type  = TRB_TYPE_LINK;\r
  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);\r
  EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);\r
  EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
  //\r
  // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.\r
  //\r
  EndTrb->TC    = 1;\r
  //\r
  // Set Cycle bit as other TRB PCS init value\r
  //\r
  EndTrb->CycleBit = 0;\r
}\r
\r
/**\r
  Initialize the XHCI host controller for schedule.\r
\r
  @param  Xhc       The XHCI device to be initialized.\r
\r
**/\r
VOID\r
XhcPeiInitSched (\r
  IN PEI_XHC_DEV        *Xhc\r
  )\r
{\r
  VOID                  *Dcbaa;\r
  EFI_PHYSICAL_ADDRESS  DcbaaPhy;\r
  UINTN                 Size;\r
  EFI_PHYSICAL_ADDRESS  CmdRingPhy;\r
  UINT32                MaxScratchpadBufs;\r
  UINT64                *ScratchBuf;\r
  EFI_PHYSICAL_ADDRESS  ScratchPhy;\r
  UINT64                *ScratchEntry;\r
  EFI_PHYSICAL_ADDRESS  ScratchEntryPhy;\r
  UINT32                Index;\r
  EFI_STATUS            Status;\r
\r
  //\r
  // Initialize memory management.\r
  //\r
  Xhc->MemPool = UsbHcInitMemPool ();\r
  ASSERT (Xhc->MemPool != NULL);\r
\r
  //\r
  // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)\r
  // to enable the device slots that system software is going to use.\r
  //\r
  Xhc->MaxSlotsEn = Xhc->HcSParams1.Data.MaxSlots;\r
  ASSERT (Xhc->MaxSlotsEn >= 1 && Xhc->MaxSlotsEn <= 255);\r
  XhcPeiWriteOpReg (Xhc, XHC_CONFIG_OFFSET, (XhcPeiReadOpReg (Xhc, XHC_CONFIG_OFFSET) & ~XHC_CONFIG_MASK) | Xhc->MaxSlotsEn);\r
\r
  //\r
  // The Device Context Base Address Array entry associated with each allocated Device Slot\r
  // shall contain a 64-bit pointer to the base of the associated Device Context.\r
  // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.\r
  // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.\r
  //\r
  Size = (Xhc->MaxSlotsEn + 1) * sizeof (UINT64);\r
  Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Size);\r
  ASSERT (Dcbaa != NULL);\r
\r
  //\r
  // A Scratchpad Buffer is a PAGESIZE block of system memory located on a PAGESIZE boundary.\r
  // System software shall allocate the Scratchpad Buffer(s) before placing the xHC in to Run\r
  // mode (Run/Stop(R/S) ='1').\r
  //\r
  MaxScratchpadBufs      = ((Xhc->HcSParams2.Data.ScratchBufHi) << 5) | (Xhc->HcSParams2.Data.ScratchBufLo);\r
  Xhc->MaxScratchpadBufs = MaxScratchpadBufs;\r
  ASSERT (MaxScratchpadBufs <= 1023);\r
  if (MaxScratchpadBufs != 0) {\r
    //\r
    // Allocate the buffer to record the host address for each entry\r
    //\r
    ScratchEntry = AllocateZeroPool (sizeof (UINT64) * MaxScratchpadBufs);\r
    ASSERT (ScratchEntry != NULL);\r
    Xhc->ScratchEntry = ScratchEntry;\r
\r
    ScratchPhy = 0;\r
    Status = UsbHcAllocateAlignedPages (\r
               EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),\r
               Xhc->PageSize,\r
               (VOID **) &ScratchBuf,\r
               &ScratchPhy\r
               );\r
    ASSERT_EFI_ERROR (Status);\r
\r
    ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));\r
    Xhc->ScratchBuf = ScratchBuf;\r
\r
    //\r
    // Allocate each scratch buffer\r
    //\r
    for (Index = 0; Index < MaxScratchpadBufs; Index++) {\r
      ScratchEntryPhy = 0;\r
      Status = UsbHcAllocateAlignedPages (\r
                 EFI_SIZE_TO_PAGES (Xhc->PageSize),\r
                 Xhc->PageSize,\r
                 (VOID **) &ScratchEntry[Index],\r
                 &ScratchEntryPhy\r
                 );\r
      ASSERT_EFI_ERROR (Status);\r
      ZeroMem ((VOID *) (UINTN) ScratchEntry[Index], Xhc->PageSize);\r
      //\r
      // Fill with the PCI device address\r
      //\r
      *ScratchBuf++ = ScratchEntryPhy;\r
    }\r
    //\r
    // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the\r
    // Device Context Base Address Array points to the Scratchpad Buffer Array.\r
    //\r
    *(UINT64 *) Dcbaa = (UINT64) (UINTN) ScratchPhy;\r
  }\r
\r
  //\r
  // Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with\r
  // a 64-bit address pointing to where the Device Context Base Address Array is located.\r
  //\r
  Xhc->DCBAA = (UINT64 *) (UINTN) Dcbaa;\r
  //\r
  // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
  // So divide it to two 32-bytes width register access.\r
  //\r
  DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Size);\r
  XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT (DcbaaPhy));\r
  XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));\r
\r
  DEBUG ((EFI_D_INFO, "XhcPeiInitSched:DCBAA=0x%x\n", Xhc->DCBAA));\r
\r
  //\r
  // Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register\r
  // (5.4.5) with a 64-bit address pointing to the starting address of the first TRB of the Command Ring.\r
  // Note: The Command Ring is 64 byte aligned, so the low order 6 bits of the Command Ring Pointer shall\r
  // always be '0'.\r
  //\r
  XhcPeiCreateTransferRing (Xhc, CMD_RING_TRB_NUMBER, &Xhc->CmdRing);\r
  //\r
  // The xHC uses the Enqueue Pointer to determine when a Transfer Ring is empty. As it fetches TRBs from a\r
  // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.\r
  // So we set RCS as inverted PCS init value to let Command Ring empty\r
  //\r
  CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);\r
  ASSERT ((CmdRingPhy & 0x3F) == 0);\r
  CmdRingPhy |= XHC_CRCR_RCS;\r
  //\r
  // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
  // So divide it to two 32-bytes width register access.\r
  //\r
  XhcPeiWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT (CmdRingPhy));\r
  XhcPeiWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRingPhy));\r
\r
  DEBUG ((EFI_D_INFO, "XhcPeiInitSched:XHC_CRCR=0x%x\n", Xhc->CmdRing.RingSeg0));\r
\r
  //\r
  // Disable the 'interrupter enable' bit in USB_CMD\r
  // and clear IE & IP bit in all Interrupter X Management Registers.\r
  //\r
  XhcPeiClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_INTE);\r
  for (Index = 0; Index < (UINT16)(Xhc->HcSParams1.Data.MaxIntrs); Index++) {\r
    XhcPeiClearRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IE);\r
    XhcPeiSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IP);\r
  }\r
\r
  //\r
  // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer\r
  //\r
  XhcPeiCreateEventRing (Xhc, &Xhc->EventRing);\r
  DEBUG ((EFI_D_INFO, "XhcPeiInitSched:XHC_EVENTRING=0x%x\n", Xhc->EventRing.EventRingSeg0));\r
}\r
\r
/**\r
  Free the resouce allocated at initializing schedule.\r
\r
  @param  Xhc       The XHCI device.\r
\r
**/\r
VOID\r
XhcPeiFreeSched (\r
  IN PEI_XHC_DEV    *Xhc\r
  )\r
{\r
  UINT32                  Index;\r
  UINT64                  *ScratchEntry;\r
\r
  if (Xhc->ScratchBuf != NULL) {\r
    ScratchEntry = Xhc->ScratchEntry;\r
    for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) {\r
      //\r
      // Free Scratchpad Buffers\r
      //\r
      UsbHcFreeAlignedPages ((VOID*) (UINTN) ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize));\r
    }\r
    //\r
    // Free Scratchpad Buffer Array\r
    //\r
    UsbHcFreeAlignedPages (Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScratchpadBufs * sizeof (UINT64)));\r
    FreePool (Xhc->ScratchEntry);\r
  }\r
\r
  if (Xhc->CmdRing.RingSeg0 != NULL) {\r
    UsbHcFreeMem (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);\r
    Xhc->CmdRing.RingSeg0 = NULL;\r
  }\r
\r
  XhcPeiFreeEventRing (Xhc,&Xhc->EventRing);\r
\r
  if (Xhc->DCBAA != NULL) {\r
    UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof (UINT64));\r
    Xhc->DCBAA = NULL;\r
  }\r
\r
  //\r
  // Free memory pool at last\r
  //\r
  if (Xhc->MemPool != NULL) {\r
    UsbHcFreeMemPool (Xhc->MemPool);\r
    Xhc->MemPool = NULL;\r
  }\r
}\r
\r