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504214c4 LG |
1 | /** @file \r |
2 | \r | |
3 | Task priority (TPL) function \r | |
28a00297 | 4 | \r |
504214c4 | 5 | Copyright (c) 2006 - 2008, Intel Corporation \r |
28a00297 | 6 | All rights reserved. This program and the accompanying materials \r |
7 | are licensed and made available under the terms and conditions of the BSD License \r | |
8 | which accompanies this distribution. The full text of the license may be found at \r | |
9 | http://opensource.org/licenses/bsd-license.php \r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | \r | |
504214c4 | 14 | **/\r |
28a00297 | 15 | \r |
16 | #include <DxeMain.h>\r | |
17 | \r | |
162ed594 | 18 | \r |
19 | /**\r | |
20 | Set Interrupt State.\r | |
21 | \r | |
22 | @param Enable The state of enable or disable interrupt\r | |
23 | \r | |
24 | **/\r | |
28a00297 | 25 | STATIC\r |
26 | VOID\r | |
27 | CoreSetInterruptState (\r | |
28 | IN BOOLEAN Enable\r | |
29 | )\r | |
28a00297 | 30 | {\r |
31 | if (gCpu != NULL) {\r | |
32 | if (Enable) {\r | |
33 | gCpu->EnableInterrupt(gCpu);\r | |
34 | } else {\r | |
35 | gCpu->DisableInterrupt(gCpu);\r | |
36 | }\r | |
37 | }\r | |
38 | }\r | |
39 | \r | |
40 | //\r | |
41 | // Return the highest set bit\r | |
42 | //\r | |
162ed594 | 43 | \r |
44 | /**\r | |
45 | Return the highest set bit.\r | |
46 | \r | |
47 | @param Number The value to check \r | |
48 | \r | |
49 | @return Bit position of the highest set bit\r | |
50 | \r | |
51 | **/\r | |
28a00297 | 52 | UINTN\r |
53 | CoreHighestSetBit (\r | |
54 | IN UINTN Number\r | |
55 | )\r | |
28a00297 | 56 | {\r |
57 | UINTN msb;\r | |
58 | \r | |
59 | msb = 31;\r | |
60 | while ((msb > 0) && ((Number & (UINTN)(1 << msb)) == 0)) {\r | |
61 | msb--;\r | |
62 | }\r | |
63 | \r | |
64 | return msb;\r | |
65 | }\r | |
66 | \r | |
67 | \r | |
68 | \r | |
28a00297 | 69 | \r |
162ed594 | 70 | /**\r |
28a00297 | 71 | Raise the task priority level to the new level.\r |
72 | High level is implemented by disabling processor interrupts.\r | |
73 | \r | |
162ed594 | 74 | @param NewTpl New task priority level \r |
28a00297 | 75 | \r |
162ed594 | 76 | @return The previous task priority level\r |
28a00297 | 77 | \r |
162ed594 | 78 | **/\r |
79 | EFI_TPL\r | |
80 | EFIAPI\r | |
81 | CoreRaiseTpl (\r | |
82 | IN EFI_TPL NewTpl\r | |
83 | )\r | |
28a00297 | 84 | {\r |
85 | EFI_TPL OldTpl;\r | |
86 | \r | |
87 | OldTpl = gEfiCurrentTpl;\r | |
88 | ASSERT (OldTpl <= NewTpl);\r | |
89 | ASSERT (VALID_TPL (NewTpl));\r | |
90 | \r | |
91 | //\r | |
92 | // If raising to high level, disable interrupts\r | |
93 | //\r | |
94 | if (NewTpl >= TPL_HIGH_LEVEL && OldTpl < TPL_HIGH_LEVEL) {\r | |
95 | CoreSetInterruptState (FALSE);\r | |
96 | }\r | |
97 | \r | |
98 | //\r | |
99 | // Set the new value\r | |
100 | //\r | |
101 | gEfiCurrentTpl = NewTpl;\r | |
102 | \r | |
103 | return OldTpl;\r | |
104 | }\r | |
105 | \r | |
106 | \r | |
107 | \r | |
162ed594 | 108 | \r |
109 | /**\r | |
110 | Lowers the task priority to the previous value. If the new\r | |
111 | priority unmasks events at a higher priority, they are dispatched.\r | |
112 | \r | |
113 | @param NewTpl New, lower, task priority\r | |
114 | \r | |
115 | **/\r | |
28a00297 | 116 | VOID\r |
117 | EFIAPI\r | |
118 | CoreRestoreTpl (\r | |
119 | IN EFI_TPL NewTpl\r | |
120 | )\r | |
28a00297 | 121 | {\r |
122 | EFI_TPL OldTpl;\r | |
123 | \r | |
124 | OldTpl = gEfiCurrentTpl;\r | |
125 | ASSERT (NewTpl <= OldTpl);\r | |
126 | ASSERT (VALID_TPL (NewTpl));\r | |
127 | \r | |
128 | //\r | |
129 | // If lowering below HIGH_LEVEL, make sure\r | |
130 | // interrupts are enabled\r | |
131 | //\r | |
132 | \r | |
133 | if (OldTpl >= TPL_HIGH_LEVEL && NewTpl < TPL_HIGH_LEVEL) {\r | |
134 | gEfiCurrentTpl = TPL_HIGH_LEVEL; \r | |
135 | }\r | |
136 | \r | |
137 | //\r | |
138 | // Dispatch any pending events\r | |
139 | //\r | |
140 | \r | |
141 | while ((-2 << NewTpl) & gEventPending) {\r | |
142 | gEfiCurrentTpl = CoreHighestSetBit (gEventPending);\r | |
143 | if (gEfiCurrentTpl < TPL_HIGH_LEVEL) {\r | |
144 | CoreSetInterruptState (TRUE);\r | |
145 | }\r | |
146 | CoreDispatchEventNotifies (gEfiCurrentTpl);\r | |
147 | }\r | |
148 | \r | |
149 | //\r | |
150 | // Set the new value\r | |
151 | //\r | |
152 | \r | |
153 | gEfiCurrentTpl = NewTpl;\r | |
154 | \r | |
155 | //\r | |
156 | // If lowering below HIGH_LEVEL, make sure\r | |
157 | // interrupts are enabled\r | |
158 | //\r | |
159 | if (gEfiCurrentTpl < TPL_HIGH_LEVEL) {\r | |
160 | CoreSetInterruptState (TRUE);\r | |
161 | }\r | |
162 | \r | |
163 | }\r |