[mirror_edk2.git] / MdeModulePkg / Core / DxeIplPeim / Ia32 / DxeLoadFunc.c

/** @file\r
  Ia32-specific functionality for DxeLoad.\r
\r
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "DxeIpl.h"\r
#include "VirtualMemory.h"\r
\r
#define IDT_ENTRY_COUNT       32\r
\r
typedef struct _X64_IDT_TABLE {\r
  //\r
  // Reserved 4 bytes preceding PeiService and IdtTable,\r
  // since IDT base address should be 8-byte alignment.\r
  //\r
  UINT32                   Reserved;\r
  CONST EFI_PEI_SERVICES   **PeiService;\r
  X64_IDT_GATE_DESCRIPTOR  IdtTable[IDT_ENTRY_COUNT];\r
} X64_IDT_TABLE;\r
\r
//\r
// Global Descriptor Table (GDT)\r
//\r
GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT gGdtEntries[] = {\r
/* selector { Global Segment Descriptor                              } */\r
/* 0x00 */  {{0,      0,  0,  0,    0,  0,  0,  0,    0,  0, 0,  0,  0}}, //null descriptor\r
/* 0x08 */  {{0xffff, 0,  0,  0x2,  1,  0,  1,  0xf,  0,  0, 1,  1,  0}}, //linear data segment descriptor\r
/* 0x10 */  {{0xffff, 0,  0,  0xf,  1,  0,  1,  0xf,  0,  0, 1,  1,  0}}, //linear code segment descriptor\r
/* 0x18 */  {{0xffff, 0,  0,  0x3,  1,  0,  1,  0xf,  0,  0, 1,  1,  0}}, //system data segment descriptor\r
/* 0x20 */  {{0xffff, 0,  0,  0xa,  1,  0,  1,  0xf,  0,  0, 1,  1,  0}}, //system code segment descriptor\r
/* 0x28 */  {{0,      0,  0,  0,    0,  0,  0,  0,    0,  0, 0,  0,  0}}, //spare segment descriptor\r
/* 0x30 */  {{0xffff, 0,  0,  0x2,  1,  0,  1,  0xf,  0,  0, 1,  1,  0}}, //system data segment descriptor\r
/* 0x38 */  {{0xffff, 0,  0,  0xa,  1,  0,  1,  0xf,  0,  1, 0,  1,  0}}, //system code segment descriptor\r
/* 0x40 */  {{0,      0,  0,  0,    0,  0,  0,  0,    0,  0, 0,  0,  0}}, //spare segment descriptor\r
};\r
\r
//\r
// IA32 Gdt register\r
//\r
GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR gGdt = {\r
  sizeof (gGdtEntries) - 1,\r
  (UINTN) gGdtEntries\r
  };\r
\r
GLOBAL_REMOVE_IF_UNREFERENCED  IA32_DESCRIPTOR gLidtDescriptor = {\r
  sizeof (X64_IDT_GATE_DESCRIPTOR) * IDT_ENTRY_COUNT - 1,\r
  0\r
};\r
\r
/**\r
  Allocates and fills in the Page Directory and Page Table Entries to\r
  establish a 4G page table.\r
\r
  @param[in] StackBase  Stack base address.\r
  @param[in] StackSize  Stack size.\r
\r
  @return The address of page table.\r
\r
**/\r
UINTN\r
Create4GPageTablesIa32Pae (\r
  IN EFI_PHYSICAL_ADDRESS   StackBase,\r
  IN UINTN                  StackSize\r
  )\r
{\r
  UINT8                                         PhysicalAddressBits;\r
  EFI_PHYSICAL_ADDRESS                          PhysicalAddress;\r
  UINTN                                         IndexOfPdpEntries;\r
  UINTN                                         IndexOfPageDirectoryEntries;\r
  UINT32                                        NumberOfPdpEntriesNeeded;\r
  PAGE_MAP_AND_DIRECTORY_POINTER                *PageMap;\r
  PAGE_MAP_AND_DIRECTORY_POINTER                *PageDirectoryPointerEntry;\r
  PAGE_TABLE_ENTRY                              *PageDirectoryEntry;\r
  UINTN                                         TotalPagesNum;\r
  UINTN                                         PageAddress;\r
  UINT64                                        AddressEncMask;\r
\r
  //\r
  // Make sure AddressEncMask is contained to smallest supported address field\r
  //\r
  AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
\r
  PhysicalAddressBits = 32;\r
\r
  //\r
  // Calculate the table entries needed.\r
  //\r
  NumberOfPdpEntriesNeeded = (UINT32) LShiftU64 (1, (PhysicalAddressBits - 30));\r
\r
  TotalPagesNum = NumberOfPdpEntriesNeeded + 1;\r
  PageAddress = (UINTN) AllocatePageTableMemory (TotalPagesNum);\r
  ASSERT (PageAddress != 0);\r
\r
  PageMap = (VOID *) PageAddress;\r
  PageAddress += SIZE_4KB;\r
\r
  PageDirectoryPointerEntry = PageMap;\r
  PhysicalAddress = 0;\r
\r
  for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
    //\r
    // Each Directory Pointer entries points to a page of Page Directory entires.\r
    // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
    //\r
    PageDirectoryEntry = (VOID *) PageAddress;\r
    PageAddress += SIZE_4KB;\r
\r
    //\r
    // Fill in a Page Directory Pointer Entries\r
    //\r
    PageDirectoryPointerEntry->Uint64 = (UINT64) (UINTN) PageDirectoryEntry | AddressEncMask;\r
    PageDirectoryPointerEntry->Bits.Present = 1;\r
\r
    for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress += SIZE_2MB) {\r
      if ((IsNullDetectionEnabled () && PhysicalAddress == 0)\r
          || ((PhysicalAddress < StackBase + StackSize)\r
              && ((PhysicalAddress + SIZE_2MB) > StackBase))) {\r
        //\r
        // Need to split this 2M page that covers stack range.\r
        //\r
        Split2MPageTo4K (PhysicalAddress, (UINT64 *) PageDirectoryEntry, StackBase, StackSize, 0, 0);\r
      } else {\r
        //\r
        // Fill in the Page Directory entries\r
        //\r
        PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress | AddressEncMask;\r
        PageDirectoryEntry->Bits.ReadWrite = 1;\r
        PageDirectoryEntry->Bits.Present = 1;\r
        PageDirectoryEntry->Bits.MustBe1 = 1;\r
      }\r
    }\r
  }\r
\r
  for (; IndexOfPdpEntries < 512; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
    ZeroMem (\r
      PageDirectoryPointerEntry,\r
      sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)\r
      );\r
  }\r
\r
  //\r
  // Protect the page table by marking the memory used for page table to be\r
  // read-only.\r
  //\r
  EnablePageTableProtection ((UINTN)PageMap, FALSE);\r
\r
  return (UINTN) PageMap;\r
}\r
\r
/**\r
  The function will check if IA32 PAE is supported.\r
\r
  @retval TRUE      IA32 PAE is supported.\r
  @retval FALSE     IA32 PAE is not supported.\r
\r
**/\r
BOOLEAN\r
IsIa32PaeSupport (\r
  VOID\r
  )\r
{\r
  UINT32            RegEax;\r
  UINT32            RegEdx;\r
  BOOLEAN           Ia32PaeSupport;\r
\r
  Ia32PaeSupport = FALSE;\r
  AsmCpuid (0x0, &RegEax, NULL, NULL, NULL);\r
  if (RegEax >= 0x1) {\r
    AsmCpuid (0x1, NULL, NULL, NULL, &RegEdx);\r
    if ((RegEdx & BIT6) != 0) {\r
      Ia32PaeSupport = TRUE;\r
    }\r
  }\r
\r
  return Ia32PaeSupport;\r
}\r
\r
/**\r
  The function will check if page table should be setup or not.\r
\r
  @retval TRUE      Page table should be created.\r
  @retval FALSE     Page table should not be created.\r
\r
**/\r
BOOLEAN\r
ToBuildPageTable (\r
  VOID\r
  )\r
{\r
  if (!IsIa32PaeSupport ()) {\r
    return FALSE;\r
  }\r
\r
  if (IsNullDetectionEnabled ()) {\r
    return TRUE;\r
  }\r
\r
  if (PcdGet8 (PcdHeapGuardPropertyMask) != 0) {\r
    return TRUE;\r
  }\r
\r
  if (PcdGetBool (PcdCpuStackGuard)) {\r
    return TRUE;\r
  }\r
\r
  if (IsEnableNonExecNeeded ()) {\r
    return TRUE;\r
  }\r
\r
  return FALSE;\r
}\r
\r
/**\r
   Transfers control to DxeCore.\r
\r
   This function performs a CPU architecture specific operations to execute\r
   the entry point of DxeCore with the parameters of HobList.\r
   It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.\r
\r
   @param DxeCoreEntryPoint         The entry point of DxeCore.\r
   @param HobList                   The start of HobList passed to DxeCore.\r
\r
**/\r
VOID\r
HandOffToDxeCore (\r
  IN EFI_PHYSICAL_ADDRESS   DxeCoreEntryPoint,\r
  IN EFI_PEI_HOB_POINTERS   HobList\r
  )\r
{\r
  EFI_STATUS                Status;\r
  EFI_PHYSICAL_ADDRESS      BaseOfStack;\r
  EFI_PHYSICAL_ADDRESS      TopOfStack;\r
  UINTN                     PageTables;\r
  X64_IDT_GATE_DESCRIPTOR   *IdtTable;\r
  UINTN                     SizeOfTemplate;\r
  VOID                      *TemplateBase;\r
  EFI_PHYSICAL_ADDRESS      VectorAddress;\r
  UINT32                    Index;\r
  X64_IDT_TABLE             *IdtTableForX64;\r
  EFI_VECTOR_HANDOFF_INFO   *VectorInfo;\r
  EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi;\r
  BOOLEAN                   BuildPageTablesIa32Pae;\r
\r
  //\r
  // Clear page 0 and mark it as allocated if NULL pointer detection is enabled.\r
  //\r
  if (IsNullDetectionEnabled ()) {\r
    ClearFirst4KPage (HobList.Raw);\r
    BuildMemoryAllocationHob (0, EFI_PAGES_TO_SIZE (1), EfiBootServicesData);\r
  }\r
\r
  Status = PeiServicesAllocatePages (EfiBootServicesData, EFI_SIZE_TO_PAGES (STACK_SIZE), &BaseOfStack);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  if (FeaturePcdGet(PcdDxeIplSwitchToLongMode)) {\r
    //\r
    // Compute the top of the stack we were allocated, which is used to load X64 dxe core.\r
    // Pre-allocate a 32 bytes which confroms to x64 calling convention.\r
    //\r
    // The first four parameters to a function are passed in rcx, rdx, r8 and r9.\r
    // Any further parameters are pushed on the stack. Furthermore, space (4 * 8bytes) for the\r
    // register parameters is reserved on the stack, in case the called function\r
    // wants to spill them; this is important if the function is variadic.\r
    //\r
    TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - 32;\r
\r
    //\r
    //  x64 Calling Conventions requires that the stack must be aligned to 16 bytes\r
    //\r
    TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, 16);\r
\r
    //\r
    // Load the GDT of Go64. Since the GDT of 32-bit Tiano locates in the BS_DATA\r
    // memory, it may be corrupted when copying FV to high-end memory\r
    //\r
    AsmWriteGdtr (&gGdt);\r
    //\r
    // Create page table and save PageMapLevel4 to CR3\r
    //\r
    PageTables = CreateIdentityMappingPageTables (BaseOfStack, STACK_SIZE, 0, 0);\r
\r
    //\r
    // End of PEI phase signal\r
    //\r
    PERF_EVENT_SIGNAL_BEGIN (gEndOfPeiSignalPpi.Guid);\r
    Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);\r
    PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid);\r
    ASSERT_EFI_ERROR (Status);\r
\r
    //\r
    // Paging might be already enabled. To avoid conflict configuration,\r
    // disable paging first anyway.\r
    //\r
    AsmWriteCr0 (AsmReadCr0 () & (~BIT31));\r
    AsmWriteCr3 (PageTables);\r
\r
    //\r
    // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.\r
    //\r
    UpdateStackHob (BaseOfStack, STACK_SIZE);\r
\r
    SizeOfTemplate = AsmGetVectorTemplatInfo (&TemplateBase);\r
\r
    Status = PeiServicesAllocatePages (\r
               EfiBootServicesData,\r
               EFI_SIZE_TO_PAGES(sizeof (X64_IDT_TABLE) + SizeOfTemplate * IDT_ENTRY_COUNT),\r
               &VectorAddress\r
               );\r
    ASSERT_EFI_ERROR (Status);\r
\r
    //\r
    // Store EFI_PEI_SERVICES** in the 4 bytes immediately preceding IDT to avoid that\r
    // it may not be gotten correctly after IDT register is re-written.\r
    //\r
    IdtTableForX64 = (X64_IDT_TABLE *) (UINTN) VectorAddress;\r
    IdtTableForX64->PeiService = GetPeiServicesTablePointer ();\r
\r
    VectorAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) (IdtTableForX64 + 1);\r
    IdtTable      = IdtTableForX64->IdtTable;\r
    for (Index = 0; Index < IDT_ENTRY_COUNT; Index++) {\r
      IdtTable[Index].Ia32IdtEntry.Bits.GateType    =  0x8e;\r
      IdtTable[Index].Ia32IdtEntry.Bits.Reserved_0  =  0;\r
      IdtTable[Index].Ia32IdtEntry.Bits.Selector    =  SYS_CODE64_SEL;\r
\r
      IdtTable[Index].Ia32IdtEntry.Bits.OffsetLow   = (UINT16) VectorAddress;\r
      IdtTable[Index].Ia32IdtEntry.Bits.OffsetHigh  = (UINT16) (RShiftU64 (VectorAddress, 16));\r
      IdtTable[Index].Offset32To63                  = (UINT32) (RShiftU64 (VectorAddress, 32));\r
      IdtTable[Index].Reserved                      = 0;\r
\r
      CopyMem ((VOID *) (UINTN) VectorAddress, TemplateBase, SizeOfTemplate);\r
      AsmVectorFixup ((VOID *) (UINTN) VectorAddress, (UINT8) Index);\r
\r
      VectorAddress += SizeOfTemplate;\r
    }\r
\r
    gLidtDescriptor.Base = (UINTN) IdtTable;\r
\r
    //\r
    // Disable interrupt of Debug timer, since new IDT table cannot handle it.\r
    //\r
    SaveAndSetDebugTimerInterrupt (FALSE);\r
\r
    AsmWriteIdtr (&gLidtDescriptor);\r
\r
    DEBUG ((\r
      DEBUG_INFO,\r
      "%a() Stack Base: 0x%lx, Stack Size: 0x%x\n",\r
      __FUNCTION__,\r
      BaseOfStack,\r
      STACK_SIZE\r
      ));\r
\r
    //\r
    // Go to Long Mode and transfer control to DxeCore.\r
    // Interrupts will not get turned on until the CPU AP is loaded.\r
    // Call x64 drivers passing in single argument, a pointer to the HOBs.\r
    //\r
    AsmEnablePaging64 (\r
      SYS_CODE64_SEL,\r
      DxeCoreEntryPoint,\r
      (EFI_PHYSICAL_ADDRESS)(UINTN)(HobList.Raw),\r
      0,\r
      TopOfStack\r
      );\r
  } else {\r
    //\r
    // Get Vector Hand-off Info PPI and build Guided HOB\r
    //\r
    Status = PeiServicesLocatePpi (\r
               &gEfiVectorHandoffInfoPpiGuid,\r
               0,\r
               NULL,\r
               (VOID **)&VectorHandoffInfoPpi\r
               );\r
    if (Status == EFI_SUCCESS) {\r
      DEBUG ((DEBUG_INFO, "Vector Hand-off Info PPI is gotten, GUIDed HOB is created!\n"));\r
      VectorInfo = VectorHandoffInfoPpi->Info;\r
      Index = 1;\r
      while (VectorInfo->Attribute != EFI_VECTOR_HANDOFF_LAST_ENTRY) {\r
        VectorInfo ++;\r
        Index ++;\r
      }\r
      BuildGuidDataHob (\r
        &gEfiVectorHandoffInfoPpiGuid,\r
        VectorHandoffInfoPpi->Info,\r
        sizeof (EFI_VECTOR_HANDOFF_INFO) * Index\r
        );\r
    }\r
\r
    //\r
    // Compute the top of the stack we were allocated. Pre-allocate a UINTN\r
    // for safety.\r
    //\r
    TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT;\r
    TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);\r
\r
    PageTables = 0;\r
    BuildPageTablesIa32Pae = ToBuildPageTable ();\r
    if (BuildPageTablesIa32Pae) {\r
      PageTables = Create4GPageTablesIa32Pae (BaseOfStack, STACK_SIZE);\r
      if (IsEnableNonExecNeeded ()) {\r
        EnableExecuteDisableBit();\r
      }\r
    }\r
\r
    //\r
    // End of PEI phase signal\r
    //\r
    PERF_EVENT_SIGNAL_BEGIN (gEndOfPeiSignalPpi.Guid);\r
    Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);\r
    PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid);\r
    ASSERT_EFI_ERROR (Status);\r
\r
    if (BuildPageTablesIa32Pae) {\r
      //\r
      // Paging might be already enabled. To avoid conflict configuration,\r
      // disable paging first anyway.\r
      //\r
      AsmWriteCr0 (AsmReadCr0 () & (~BIT31));\r
      AsmWriteCr3 (PageTables);\r
      //\r
      // Set Physical Address Extension (bit 5 of CR4).\r
      //\r
      AsmWriteCr4 (AsmReadCr4 () | BIT5);\r
    }\r
\r
    //\r
    // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.\r
    //\r
    UpdateStackHob (BaseOfStack, STACK_SIZE);\r
\r
    DEBUG ((\r
      DEBUG_INFO,\r
      "%a() Stack Base: 0x%lx, Stack Size: 0x%x\n",\r
      __FUNCTION__,\r
      BaseOfStack,\r
      STACK_SIZE\r
      ));\r
\r
    //\r
    // Transfer the control to the entry point of DxeCore.\r
    //\r
    if (BuildPageTablesIa32Pae) {\r
      AsmEnablePaging32 (\r
        (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,\r
        HobList.Raw,\r
        NULL,\r
        (VOID *) (UINTN) TopOfStack\r
        );\r
    } else {\r
      SwitchStack (\r
        (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,\r
        HobList.Raw,\r
        NULL,\r
        (VOID *) (UINTN) TopOfStack\r
        );\r
    }\r
  }\r
}\r
Commit	Line	Data
96226baa	1	/** @file\r
48557c65	2	Ia32-specific functionality for DxeLoad.\r
95276127	3	\r
d1102dba	4	Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
5997daf7 LD	5	Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
5997daf7 LD	6	\r
9d510e61	7	SPDX-License-Identifier: BSD-2-Clause-Patent\r
95276127	8	\r
96226baa	9	**/\r
95276127	10	\r
95276127	11	#include "DxeIpl.h"\r
	12	#include "VirtualMemory.h"\r
	13	\r
df7aaeb9	14	#define IDT_ENTRY_COUNT 32\r
e7af83ae	15	\r
bdfbe63e	16	typedef struct _X64_IDT_TABLE {\r
	17	//\r
	18	// Reserved 4 bytes preceding PeiService and IdtTable,\r
	19	// since IDT base address should be 8-byte alignment.\r
	20	//\r
	21	UINT32 Reserved;\r
	22	CONST EFI_PEI_SERVICES **PeiService;\r
	23	X64_IDT_GATE_DESCRIPTOR IdtTable[IDT_ENTRY_COUNT];\r
	24	} X64_IDT_TABLE;\r
	25	\r
95276127	26	//\r
	27	// Global Descriptor Table (GDT)\r
	28	//\r
b98da1b1	29	GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT gGdtEntries[] = {\r
0cf27ce0	30	/* selector { Global Segment Descriptor } */\r
0cf27ce0	31	/* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //null descriptor\r
95276127	32	/* 0x08 */ {{0xffff, 0, 0, 0x2, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //linear data segment descriptor\r
	33	/* 0x10 */ {{0xffff, 0, 0, 0xf, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //linear code segment descriptor\r
	34	/* 0x18 */ {{0xffff, 0, 0, 0x3, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system data segment descriptor\r
	35	/* 0x20 */ {{0xffff, 0, 0, 0xa, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system code segment descriptor\r
	36	/* 0x28 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //spare segment descriptor\r
	37	/* 0x30 */ {{0xffff, 0, 0, 0x2, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system data segment descriptor\r
	38	/* 0x38 */ {{0xffff, 0, 0, 0xa, 1, 0, 1, 0xf, 0, 1, 0, 1, 0}}, //system code segment descriptor\r
	39	/* 0x40 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //spare segment descriptor\r
	40	};\r
	41	\r
	42	//\r
	43	// IA32 Gdt register\r
	44	//\r
	45	GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR gGdt = {\r
	46	sizeof (gGdtEntries) - 1,\r
	47	(UINTN) gGdtEntries\r
	48	};\r
	49	\r
5d582956	50	GLOBAL_REMOVE_IF_UNREFERENCED IA32_DESCRIPTOR gLidtDescriptor = {\r
e7af83ae	51	sizeof (X64_IDT_GATE_DESCRIPTOR) * IDT_ENTRY_COUNT - 1,\r
5d582956	52	0\r
	53	};\r
	54	\r
5630cdfe SZ	55	/**\r
	56	Allocates and fills in the Page Directory and Page Table Entries to\r
	57	establish a 4G page table.\r
	58	\r
	59	@param[in] StackBase Stack base address.\r
	60	@param[in] StackSize Stack size.\r
	61	\r
	62	@return The address of page table.\r
	63	\r
	64	**/\r
	65	UINTN\r
	66	Create4GPageTablesIa32Pae (\r
	67	IN EFI_PHYSICAL_ADDRESS StackBase,\r
	68	IN UINTN StackSize\r
	69	)\r
d1102dba	70	{\r
5630cdfe SZ	71	UINT8 PhysicalAddressBits;\r
	72	EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
	73	UINTN IndexOfPdpEntries;\r
	74	UINTN IndexOfPageDirectoryEntries;\r
	75	UINT32 NumberOfPdpEntriesNeeded;\r
	76	PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;\r
	77	PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;\r
	78	PAGE_TABLE_ENTRY *PageDirectoryEntry;\r
	79	UINTN TotalPagesNum;\r
	80	UINTN PageAddress;\r
5997daf7 LD	81	UINT64 AddressEncMask;\r
	82	\r
	83	//\r
	84	// Make sure AddressEncMask is contained to smallest supported address field\r
	85	//\r
	86	AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
5630cdfe SZ	87	\r
	88	PhysicalAddressBits = 32;\r
	89	\r
	90	//\r
	91	// Calculate the table entries needed.\r
	92	//\r
	93	NumberOfPdpEntriesNeeded = (UINT32) LShiftU64 (1, (PhysicalAddressBits - 30));\r
	94	\r
	95	TotalPagesNum = NumberOfPdpEntriesNeeded + 1;\r
2ac1730b	96	PageAddress = (UINTN) AllocatePageTableMemory (TotalPagesNum);\r
5630cdfe SZ	97	ASSERT (PageAddress != 0);\r
	98	\r
	99	PageMap = (VOID *) PageAddress;\r
	100	PageAddress += SIZE_4KB;\r
	101	\r
	102	PageDirectoryPointerEntry = PageMap;\r
	103	PhysicalAddress = 0;\r
	104	\r
	105	for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
	106	//\r
	107	// Each Directory Pointer entries points to a page of Page Directory entires.\r
	108	// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
d1102dba	109	//\r
5630cdfe SZ	110	PageDirectoryEntry = (VOID *) PageAddress;\r
	111	PageAddress += SIZE_4KB;\r
	112	\r
	113	//\r
	114	// Fill in a Page Directory Pointer Entries\r
	115	//\r
5997daf7	116	PageDirectoryPointerEntry->Uint64 = (UINT64) (UINTN) PageDirectoryEntry \| AddressEncMask;\r
5630cdfe SZ	117	PageDirectoryPointerEntry->Bits.Present = 1;\r
	118	\r
	119	for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress += SIZE_2MB) {\r
9189ec20 JW	120	if ((IsNullDetectionEnabled () && PhysicalAddress == 0)\r
	121	\|\| ((PhysicalAddress < StackBase + StackSize)\r
	122	&& ((PhysicalAddress + SIZE_2MB) > StackBase))) {\r
5630cdfe SZ	123	//\r
	124	// Need to split this 2M page that covers stack range.\r
	125	//\r
b098f5e9	126	Split2MPageTo4K (PhysicalAddress, (UINT64 *) PageDirectoryEntry, StackBase, StackSize, 0, 0);\r
5630cdfe SZ	127	} else {\r
	128	//\r
	129	// Fill in the Page Directory entries\r
	130	//\r
5997daf7	131	PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress \| AddressEncMask;\r
5630cdfe SZ	132	PageDirectoryEntry->Bits.ReadWrite = 1;\r
	133	PageDirectoryEntry->Bits.Present = 1;\r
	134	PageDirectoryEntry->Bits.MustBe1 = 1;\r
	135	}\r
	136	}\r
	137	}\r
	138	\r
	139	for (; IndexOfPdpEntries < 512; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
	140	ZeroMem (\r
	141	PageDirectoryPointerEntry,\r
	142	sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)\r
	143	);\r
	144	}\r
	145	\r
2ac1730b JW	146	//\r
	147	// Protect the page table by marking the memory used for page table to be\r
	148	// read-only.\r
	149	//\r
	150	EnablePageTableProtection ((UINTN)PageMap, FALSE);\r
	151	\r
5630cdfe SZ	152	return (UINTN) PageMap;\r
	153	}\r
	154	\r
	155	/**\r
	156	The function will check if IA32 PAE is supported.\r
	157	\r
	158	@retval TRUE IA32 PAE is supported.\r
	159	@retval FALSE IA32 PAE is not supported.\r
	160	\r
	161	**/\r
	162	BOOLEAN\r
	163	IsIa32PaeSupport (\r
	164	VOID\r
	165	)\r
	166	{\r
	167	UINT32 RegEax;\r
	168	UINT32 RegEdx;\r
	169	BOOLEAN Ia32PaeSupport;\r
	170	\r
	171	Ia32PaeSupport = FALSE;\r
	172	AsmCpuid (0x0, &RegEax, NULL, NULL, NULL);\r
	173	if (RegEax >= 0x1) {\r
	174	AsmCpuid (0x1, NULL, NULL, NULL, &RegEdx);\r
	175	if ((RegEdx & BIT6) != 0) {\r
	176	Ia32PaeSupport = TRUE;\r
	177	}\r
	178	}\r
	179	\r
	180	return Ia32PaeSupport;\r
	181	}\r
	182	\r
e63da9f0 JW	183	/**\r
	184	The function will check if page table should be setup or not.\r
	185	\r
	186	@retval TRUE Page table should be created.\r
	187	@retval FALSE Page table should not be created.\r
	188	\r
	189	**/\r
	190	BOOLEAN\r
	191	ToBuildPageTable (\r
	192	VOID\r
	193	)\r
	194	{\r
	195	if (!IsIa32PaeSupport ()) {\r
	196	return FALSE;\r
	197	}\r
	198	\r
	199	if (IsNullDetectionEnabled ()) {\r
	200	return TRUE;\r
	201	}\r
	202	\r
	203	if (PcdGet8 (PcdHeapGuardPropertyMask) != 0) {\r
	204	return TRUE;\r
	205	}\r
	206	\r
50255363 JW	207	if (PcdGetBool (PcdCpuStackGuard)) {\r
	208	return TRUE;\r
	209	}\r
	210	\r
52679261	211	if (IsEnableNonExecNeeded ()) {\r
e63da9f0 JW	212	return TRUE;\r
	213	}\r
	214	\r
	215	return FALSE;\r
	216	}\r
	217	\r
91d92e25	218	/**\r
	219	Transfers control to DxeCore.\r
	220	\r
	221	This function performs a CPU architecture specific operations to execute\r
	222	the entry point of DxeCore with the parameters of HobList.\r
48557c65	223	It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.\r
91d92e25	224	\r
48557c65	225	@param DxeCoreEntryPoint The entry point of DxeCore.\r
91d92e25	226	@param HobList The start of HobList passed to DxeCore.\r
91d92e25	227	\r
91d92e25	228	**/\r
95276127	229	VOID\r
	230	HandOffToDxeCore (\r
	231	IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,\r
9b937a73	232	IN EFI_PEI_HOB_POINTERS HobList\r
95276127	233	)\r
	234	{\r
	235	EFI_STATUS Status;\r
	236	EFI_PHYSICAL_ADDRESS BaseOfStack;\r
	237	EFI_PHYSICAL_ADDRESS TopOfStack;\r
	238	UINTN PageTables;\r
5d582956	239	X64_IDT_GATE_DESCRIPTOR *IdtTable;\r
	240	UINTN SizeOfTemplate;\r
	241	VOID *TemplateBase;\r
	242	EFI_PHYSICAL_ADDRESS VectorAddress;\r
	243	UINT32 Index;\r
bdfbe63e	244	X64_IDT_TABLE *IdtTableForX64;\r
57f360f2 JF	245	EFI_VECTOR_HANDOFF_INFO *VectorInfo;\r
57f360f2 JF	246	EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi;\r
5630cdfe	247	BOOLEAN BuildPageTablesIa32Pae;\r
95276127	248	\r
f9d0e5da JW	249	//\r
	250	// Clear page 0 and mark it as allocated if NULL pointer detection is enabled.\r
	251	//\r
9189ec20 JW	252	if (IsNullDetectionEnabled ()) {\r
9189ec20 JW	253	ClearFirst4KPage (HobList.Raw);\r
f9d0e5da	254	BuildMemoryAllocationHob (0, EFI_PAGES_TO_SIZE (1), EfiBootServicesData);\r
9189ec20 JW	255	}\r
9189ec20 JW	256	\r
95276127	257	Status = PeiServicesAllocatePages (EfiBootServicesData, EFI_SIZE_TO_PAGES (STACK_SIZE), &BaseOfStack);\r
95276127	258	ASSERT_EFI_ERROR (Status);\r
0cf27ce0	259	\r
95276127	260	if (FeaturePcdGet(PcdDxeIplSwitchToLongMode)) {\r
95276127	261	//\r
0cf27ce0	262	// Compute the top of the stack we were allocated, which is used to load X64 dxe core.\r
95276127	263	// Pre-allocate a 32 bytes which confroms to x64 calling convention.\r
95276127	264	//\r
0cf27ce0	265	// The first four parameters to a function are passed in rcx, rdx, r8 and r9.\r
	266	// Any further parameters are pushed on the stack. Furthermore, space (4 * 8bytes) for the\r
	267	// register parameters is reserved on the stack, in case the called function\r
	268	// wants to spill them; this is important if the function is variadic.\r
95276127	269	//\r
	270	TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - 32;\r
	271	\r
	272	//\r
b98da1b1	273	// x64 Calling Conventions requires that the stack must be aligned to 16 bytes\r
95276127	274	//\r
	275	TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, 16);\r
	276	\r
	277	//\r
	278	// Load the GDT of Go64. Since the GDT of 32-bit Tiano locates in the BS_DATA\r
0cf27ce0	279	// memory, it may be corrupted when copying FV to high-end memory\r
95276127	280	//\r
	281	AsmWriteGdtr (&gGdt);\r
	282	//\r
	283	// Create page table and save PageMapLevel4 to CR3\r
	284	//\r
b098f5e9	285	PageTables = CreateIdentityMappingPageTables (BaseOfStack, STACK_SIZE, 0, 0);\r
95276127	286	\r
95276127	287	//\r
48557c65	288	// End of PEI phase signal\r
95276127	289	//\r
98d20e44	290	PERF_EVENT_SIGNAL_BEGIN (gEndOfPeiSignalPpi.Guid);\r
9b937a73	291	Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);\r
98d20e44	292	PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid);\r
95276127	293	ASSERT_EFI_ERROR (Status);\r
0cf27ce0	294	\r
2af2988f JW	295	//\r
	296	// Paging might be already enabled. To avoid conflict configuration,\r
	297	// disable paging first anyway.\r
	298	//\r
	299	AsmWriteCr0 (AsmReadCr0 () & (~BIT31));\r
95276127	300	AsmWriteCr3 (PageTables);\r
5d582956	301	\r
30c8f861	302	//\r
30c8f861	303	// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.\r
0cf27ce0	304	//\r
30c8f861	305	UpdateStackHob (BaseOfStack, STACK_SIZE);\r
5d582956	306	\r
4bfa7dc4	307	SizeOfTemplate = AsmGetVectorTemplatInfo (&TemplateBase);\r
	308	\r
	309	Status = PeiServicesAllocatePages (\r
0cf27ce0	310	EfiBootServicesData,\r
bdfbe63e	311	EFI_SIZE_TO_PAGES(sizeof (X64_IDT_TABLE) + SizeOfTemplate * IDT_ENTRY_COUNT),\r
b028c102	312	&VectorAddress\r
4bfa7dc4	313	);\r
	314	ASSERT_EFI_ERROR (Status);\r
	315	\r
bdfbe63e	316	//\r
	317	// Store EFI_PEI_SERVICES** in the 4 bytes immediately preceding IDT to avoid that\r
	318	// it may not be gotten correctly after IDT register is re-written.\r
	319	//\r
b028c102	320	IdtTableForX64 = (X64_IDT_TABLE *) (UINTN) VectorAddress;\r
bdfbe63e	321	IdtTableForX64->PeiService = GetPeiServicesTablePointer ();\r
	322	\r
	323	VectorAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) (IdtTableForX64 + 1);\r
	324	IdtTable = IdtTableForX64->IdtTable;\r
e7af83ae	325	for (Index = 0; Index < IDT_ENTRY_COUNT; Index++) {\r
4bfa7dc4	326	IdtTable[Index].Ia32IdtEntry.Bits.GateType = 0x8e;\r
	327	IdtTable[Index].Ia32IdtEntry.Bits.Reserved_0 = 0;\r
	328	IdtTable[Index].Ia32IdtEntry.Bits.Selector = SYS_CODE64_SEL;\r
	329	\r
	330	IdtTable[Index].Ia32IdtEntry.Bits.OffsetLow = (UINT16) VectorAddress;\r
	331	IdtTable[Index].Ia32IdtEntry.Bits.OffsetHigh = (UINT16) (RShiftU64 (VectorAddress, 16));\r
	332	IdtTable[Index].Offset32To63 = (UINT32) (RShiftU64 (VectorAddress, 32));\r
	333	IdtTable[Index].Reserved = 0;\r
	334	\r
	335	CopyMem ((VOID *) (UINTN) VectorAddress, TemplateBase, SizeOfTemplate);\r
	336	AsmVectorFixup ((VOID *) (UINTN) VectorAddress, (UINT8) Index);\r
	337	\r
	338	VectorAddress += SizeOfTemplate;\r
5d582956	339	}\r
4bfa7dc4	340	\r
4bfa7dc4	341	gLidtDescriptor.Base = (UINTN) IdtTable;\r
0cf27ce0	342	\r
e7af83ae	343	//\r
	344	// Disable interrupt of Debug timer, since new IDT table cannot handle it.\r
	345	//\r
	346	SaveAndSetDebugTimerInterrupt (FALSE);\r
	347	\r
4bfa7dc4	348	AsmWriteIdtr (&gLidtDescriptor);\r
4bfa7dc4	349	\r
6fb389d0 JF	350	DEBUG ((\r
	351	DEBUG_INFO,\r
	352	"%a() Stack Base: 0x%lx, Stack Size: 0x%x\n",\r
	353	__FUNCTION__,\r
	354	BaseOfStack,\r
	355	STACK_SIZE\r
	356	));\r
	357	\r
5d582956	358	//\r
b98da1b1	359	// Go to Long Mode and transfer control to DxeCore.\r
b98da1b1	360	// Interrupts will not get turned on until the CPU AP is loaded.\r
95276127	361	// Call x64 drivers passing in single argument, a pointer to the HOBs.\r
0cf27ce0	362	//\r
95276127	363	AsmEnablePaging64 (\r
	364	SYS_CODE64_SEL,\r
	365	DxeCoreEntryPoint,\r
	366	(EFI_PHYSICAL_ADDRESS)(UINTN)(HobList.Raw),\r
	367	0,\r
	368	TopOfStack\r
	369	);\r
	370	} else {\r
57f360f2 JF	371	//\r
	372	// Get Vector Hand-off Info PPI and build Guided HOB\r
	373	//\r
	374	Status = PeiServicesLocatePpi (\r
	375	&gEfiVectorHandoffInfoPpiGuid,\r
	376	0,\r
	377	NULL,\r
	378	(VOID **)&VectorHandoffInfoPpi\r
	379	);\r
	380	if (Status == EFI_SUCCESS) {\r
87000d77	381	DEBUG ((DEBUG_INFO, "Vector Hand-off Info PPI is gotten, GUIDed HOB is created!\n"));\r
57f360f2 JF	382	VectorInfo = VectorHandoffInfoPpi->Info;\r
	383	Index = 1;\r
	384	while (VectorInfo->Attribute != EFI_VECTOR_HANDOFF_LAST_ENTRY) {\r
	385	VectorInfo ++;\r
	386	Index ++;\r
	387	}\r
	388	BuildGuidDataHob (\r
	389	&gEfiVectorHandoffInfoPpiGuid,\r
	390	VectorHandoffInfoPpi->Info,\r
	391	sizeof (EFI_VECTOR_HANDOFF_INFO) * Index\r
	392	);\r
	393	}\r
	394	\r
95276127	395	//\r
	396	// Compute the top of the stack we were allocated. Pre-allocate a UINTN\r
	397	// for safety.\r
	398	//\r
	399	TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT;\r
	400	TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);\r
	401	\r
09e4a8fd	402	PageTables = 0;\r
e63da9f0	403	BuildPageTablesIa32Pae = ToBuildPageTable ();\r
5630cdfe SZ	404	if (BuildPageTablesIa32Pae) {\r
5630cdfe SZ	405	PageTables = Create4GPageTablesIa32Pae (BaseOfStack, STACK_SIZE);\r
52679261	406	if (IsEnableNonExecNeeded ()) {\r
9189ec20 JW	407	EnableExecuteDisableBit();\r
9189ec20 JW	408	}\r
5630cdfe SZ	409	}\r
5630cdfe SZ	410	\r
95276127	411	//\r
48557c65	412	// End of PEI phase signal\r
95276127	413	//\r
98d20e44	414	PERF_EVENT_SIGNAL_BEGIN (gEndOfPeiSignalPpi.Guid);\r
9b937a73	415	Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);\r
98d20e44	416	PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid);\r
95276127	417	ASSERT_EFI_ERROR (Status);\r
95276127	418	\r
5630cdfe	419	if (BuildPageTablesIa32Pae) {\r
2af2988f JW	420	//\r
	421	// Paging might be already enabled. To avoid conflict configuration,\r
	422	// disable paging first anyway.\r
	423	//\r
	424	AsmWriteCr0 (AsmReadCr0 () & (~BIT31));\r
5630cdfe SZ	425	AsmWriteCr3 (PageTables);\r
	426	//\r
	427	// Set Physical Address Extension (bit 5 of CR4).\r
	428	//\r
	429	AsmWriteCr4 (AsmReadCr4 () \| BIT5);\r
	430	}\r
	431	\r
30c8f861	432	//\r
30c8f861	433	// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.\r
0cf27ce0	434	//\r
30c8f861	435	UpdateStackHob (BaseOfStack, STACK_SIZE);\r
0cf27ce0	436	\r
6fb389d0 JF	437	DEBUG ((\r
	438	DEBUG_INFO,\r
	439	"%a() Stack Base: 0x%lx, Stack Size: 0x%x\n",\r
	440	__FUNCTION__,\r
	441	BaseOfStack,\r
	442	STACK_SIZE\r
	443	));\r
	444	\r
b98da1b1	445	//\r
	446	// Transfer the control to the entry point of DxeCore.\r
	447	//\r
5630cdfe SZ	448	if (BuildPageTablesIa32Pae) {\r
	449	AsmEnablePaging32 (\r
	450	(SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,\r
	451	HobList.Raw,\r
	452	NULL,\r
	453	(VOID *) (UINTN) TopOfStack\r
	454	);\r
	455	} else {\r
	456	SwitchStack (\r
	457	(SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,\r
	458	HobList.Raw,\r
	459	NULL,\r
	460	(VOID *) (UINTN) TopOfStack\r
	461	);\r
	462	}\r
0cf27ce0	463	}\r
95276127	464	}\r