Enable Nt32 platform boot to DXE phase.
[mirror_edk2.git] / MdeModulePkg / Core / DxeIplPeim / Ia32 / VirtualMemory.c
CommitLineData
95276127 1/*++\r
2\r
3Copyright (c) 2006, Intel Corporation \r
4All rights reserved. This program and the accompanying materials \r
5are licensed and made available under the terms and conditions of the BSD License \r
6which accompanies this distribution. The full text of the license may be found at \r
7http://opensource.org/licenses/bsd-license.php \r
8 \r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
11\r
12Module Name:\r
13 VirtualMemory.c\r
14 \r
15Abstract:\r
16\r
17 x64 Virtual Memory Management Services in the form of an IA-32 driver. \r
18 Used to establish a 1:1 Virtual to Physical Mapping that is required to\r
19 enter Long Mode (x64 64-bit mode).\r
20\r
21 While we make a 1:1 mapping (identity mapping) for all physical pages \r
22 we still need to use the MTRR's to ensure that the cachability attirbutes\r
23 for all memory regions is correct.\r
24\r
25 The basic idea is to use 2MB page table entries where ever possible. If\r
26 more granularity of cachability is required then 4K page tables are used.\r
27\r
28 References:\r
29 1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
30 2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
31 3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
32 \r
33--*/ \r
34\r
35//\r
36// Include common header file for this module.\r
37//\r
38#include "CommonHeader.h"\r
39\r
40#include "VirtualMemory.h"\r
41\r
42UINTN\r
43CreateIdentityMappingPageTables (\r
44 VOID\r
45 )\r
46/*++\r
47\r
48Routine Description:\r
49\r
50 Allocates and fills in the Page Directory and Page Table Entries to\r
51 establish a 1:1 Virtual to Physical mapping.\r
52\r
53Arguments:\r
54\r
55 NumberOfProcessorPhysicalAddressBits - Number of processor address bits to use.\r
56 Limits the number of page table entries \r
57 to the physical address space.\r
58\r
59Returns:\r
60\r
61 EFI_SUCCESS The 1:1 Virtual to Physical identity mapping was created\r
62\r
63--*/\r
64{ \r
65 UINT8 PhysicalAddressBits;\r
66 EFI_PHYSICAL_ADDRESS PageAddress;\r
67 UINTN IndexOfPml4Entries;\r
68 UINTN IndexOfPdpEntries;\r
69 UINTN IndexOfPageDirectoryEntries;\r
70 UINTN NumberOfPml4EntriesNeeded;\r
71 UINTN NumberOfPdpEntriesNeeded;\r
72 PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry;\r
73 PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;\r
74 PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;\r
75 PAGE_TABLE_ENTRY *PageDirectoryEntry;\r
76 UINTN TotalPagesNum;\r
77 UINTN BigPageAddress;\r
78 VOID *Hob;\r
79\r
80 //\r
81 // Get physical address bits supported from CPU HOB.\r
82 //\r
83 PhysicalAddressBits = 36;\r
84 \r
85 Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
86 if (Hob != NULL) {\r
87 PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace; \r
88 }\r
89\r
90 //\r
91 // Calculate the table entries needed.\r
92 //\r
93 if (PhysicalAddressBits <= 39 ) {\r
94 NumberOfPml4EntriesNeeded = 1;\r
95 NumberOfPdpEntriesNeeded = 1 << (PhysicalAddressBits - 30);\r
96 } else {\r
97 NumberOfPml4EntriesNeeded = 1 << (PhysicalAddressBits - 39);\r
98 NumberOfPdpEntriesNeeded = 512;\r
99 }\r
100\r
101 //\r
102 // Pre-allocate big pages to avoid later allocations. \r
103 //\r
104 TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;\r
105 BigPageAddress = (UINTN) AllocatePages (TotalPagesNum);\r
106 ASSERT (BigPageAddress != 0);\r
107\r
108 //\r
109 // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
110 //\r
111 PageMap = (VOID *) BigPageAddress;\r
112 BigPageAddress += EFI_PAGE_SIZE;\r
113\r
114 PageMapLevel4Entry = PageMap;\r
115 PageAddress = 0;\r
116 for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
117 //\r
118 // Each PML4 entry points to a page of Page Directory Pointer entires.\r
119 // So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.\r
120 //\r
121 PageDirectoryPointerEntry = (VOID *) BigPageAddress;\r
122 BigPageAddress += EFI_PAGE_SIZE;\r
123\r
124 //\r
125 // Make a PML4 Entry\r
126 //\r
127 PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;\r
128 PageMapLevel4Entry->Bits.ReadWrite = 1;\r
129 PageMapLevel4Entry->Bits.Present = 1;\r
130\r
131 for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
132 //\r
133 // Each Directory Pointer entries points to a page of Page Directory entires.\r
134 // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
135 // \r
136 PageDirectoryEntry = (VOID *) BigPageAddress;\r
137 BigPageAddress += EFI_PAGE_SIZE;\r
138\r
139 //\r
140 // Fill in a Page Directory Pointer Entries\r
141 //\r
142 PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;\r
143 PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
144 PageDirectoryPointerEntry->Bits.Present = 1;\r
145\r
146 for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += 0x200000) {\r
147 //\r
148 // Fill in the Page Directory entries\r
149 //\r
150 PageDirectoryEntry->Uint64 = (UINT64)PageAddress;\r
151 PageDirectoryEntry->Bits.ReadWrite = 1;\r
152 PageDirectoryEntry->Bits.Present = 1;\r
153 PageDirectoryEntry->Bits.MustBe1 = 1;\r
154\r
155 }\r
156 }\r
157 }\r
158\r
159 //\r
160 // For the PML4 entries we are not using fill in a null entry.\r
161 // For now we just copy the first entry.\r
162 //\r
163 for (; IndexOfPml4Entries < 512; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
164 CopyMem (\r
165 PageMapLevel4Entry,\r
166 PageMap,\r
167 sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)\r
168 );\r
169 }\r
170\r
171 return (UINTN)PageMap; // FIXME\r
172}\r
173\r