[mirror_edk2.git] / MdeModulePkg / Core / DxeIplPeim / Ia32 / VirtualMemory.c

/*++\r
\r
Copyright (c) 2006, Intel Corporation                                                         \r
All rights reserved. This program and the accompanying materials                          \r
are licensed and made available under the terms and conditions of the BSD License         \r
which accompanies this distribution.  The full text of the license may be found at        \r
http://opensource.org/licenses/bsd-license.php                                            \r
                                                                                          \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
Module Name:\r
  VirtualMemory.c\r
  \r
Abstract:\r
\r
  x64 Virtual Memory Management Services in the form of an IA-32 driver.  \r
  Used to establish a 1:1 Virtual to Physical Mapping that is required to\r
  enter Long Mode (x64 64-bit mode).\r
\r
  While we make a 1:1 mapping (identity mapping) for all physical pages \r
  we still need to use the MTRR's to ensure that the cachability attirbutes\r
  for all memory regions is correct.\r
\r
  The basic idea is to use 2MB page table entries where ever possible. If\r
  more granularity of cachability is required then 4K page tables are used.\r
\r
  References:\r
    1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
    2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
    3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
  \r
--*/  \r
\r
#include "DxeIpl.h"\r
#include "VirtualMemory.h"\r
\r
\r
UINTN\r
CreateIdentityMappingPageTables (\r
  VOID\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Allocates and fills in the Page Directory and Page Table Entries to\r
  establish a 1:1 Virtual to Physical mapping.\r
\r
Arguments:\r
\r
  NumberOfProcessorPhysicalAddressBits - Number of processor address bits to use.\r
                                         Limits the number of page table entries \r
                                         to the physical address space.\r
\r
Returns:\r
\r
  EFI_SUCCESS           The 1:1 Virtual to Physical identity mapping was created\r
\r
--*/\r
{  \r
  UINT8                                         PhysicalAddressBits;\r
  EFI_PHYSICAL_ADDRESS                          PageAddress;\r
  UINTN                                         IndexOfPml4Entries;\r
  UINTN                                         IndexOfPdpEntries;\r
  UINTN                                         IndexOfPageDirectoryEntries;\r
  UINTN                                         NumberOfPml4EntriesNeeded;\r
  UINTN                                         NumberOfPdpEntriesNeeded;\r
  PAGE_MAP_AND_DIRECTORY_POINTER                *PageMapLevel4Entry;\r
  PAGE_MAP_AND_DIRECTORY_POINTER                *PageMap;\r
  PAGE_MAP_AND_DIRECTORY_POINTER                *PageDirectoryPointerEntry;\r
  PAGE_TABLE_ENTRY                              *PageDirectoryEntry;\r
  UINTN                                         TotalPagesNum;\r
  UINTN                                         BigPageAddress;\r
  VOID                                          *Hob;\r
\r
  //\r
  // Get physical address bits supported from CPU HOB.\r
  //\r
  PhysicalAddressBits = 36;\r
  \r
  Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
  if (Hob != NULL) {\r
    PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;    \r
  }\r
\r
  //\r
  // Calculate the table entries needed.\r
  //\r
  if (PhysicalAddressBits <= 39 ) {\r
    NumberOfPml4EntriesNeeded = 1;\r
    NumberOfPdpEntriesNeeded =  1 << (PhysicalAddressBits - 30);\r
  } else {\r
    NumberOfPml4EntriesNeeded = 1 << (PhysicalAddressBits - 39);\r
    NumberOfPdpEntriesNeeded = 512;\r
  }\r
\r
  //\r
  // Pre-allocate big pages to avoid later allocations. \r
  //\r
  TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;\r
  BigPageAddress = (UINTN) AllocatePages (TotalPagesNum);\r
  ASSERT (BigPageAddress != 0);\r
\r
  //\r
  // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
  //\r
  PageMap         = (VOID *) BigPageAddress;\r
  BigPageAddress += EFI_PAGE_SIZE;\r
\r
  PageMapLevel4Entry = PageMap;\r
  PageAddress        = 0;\r
  for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
    //\r
    // Each PML4 entry points to a page of Page Directory Pointer entires.\r
    // So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.\r
    //\r
    PageDirectoryPointerEntry = (VOID *) BigPageAddress;\r
    BigPageAddress += EFI_PAGE_SIZE;\r
\r
    //\r
    // Make a PML4 Entry\r
    //\r
    PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;\r
    PageMapLevel4Entry->Bits.ReadWrite = 1;\r
    PageMapLevel4Entry->Bits.Present = 1;\r
\r
    for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
      //\r
      // Each Directory Pointer entries points to a page of Page Directory entires.\r
      // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
      //       \r
      PageDirectoryEntry = (VOID *) BigPageAddress;\r
      BigPageAddress += EFI_PAGE_SIZE;\r
\r
      //\r
      // Fill in a Page Directory Pointer Entries\r
      //\r
      PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;\r
      PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
      PageDirectoryPointerEntry->Bits.Present = 1;\r
\r
      for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += 0x200000) {\r
        //\r
        // Fill in the Page Directory entries\r
        //\r
        PageDirectoryEntry->Uint64 = (UINT64)PageAddress;\r
        PageDirectoryEntry->Bits.ReadWrite = 1;\r
        PageDirectoryEntry->Bits.Present = 1;\r
        PageDirectoryEntry->Bits.MustBe1 = 1;\r
\r
      }\r
    }\r
  }\r
\r
  //\r
  // For the PML4 entries we are not using fill in a null entry.\r
  // For now we just copy the first entry.\r
  //\r
  for (; IndexOfPml4Entries < 512; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
     CopyMem (\r
       PageMapLevel4Entry,\r
       PageMap,\r
       sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)\r
       );\r
  }\r
\r
  return (UINTN)PageMap; // FIXME\r
}\r
\r
Commit	Line	Data
95276127	1	/*++\r
	2	\r
	3	Copyright (c) 2006, Intel Corporation \r
	4	All rights reserved. This program and the accompanying materials \r
	5	are licensed and made available under the terms and conditions of the BSD License \r
	6	which accompanies this distribution. The full text of the license may be found at \r
	7	http://opensource.org/licenses/bsd-license.php \r
	8	\r
	9	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	\r
	12	Module Name:\r
	13	VirtualMemory.c\r
	14	\r
	15	Abstract:\r
	16	\r
	17	x64 Virtual Memory Management Services in the form of an IA-32 driver. \r
	18	Used to establish a 1:1 Virtual to Physical Mapping that is required to\r
	19	enter Long Mode (x64 64-bit mode).\r
	20	\r
	21	While we make a 1:1 mapping (identity mapping) for all physical pages \r
	22	we still need to use the MTRR's to ensure that the cachability attirbutes\r
	23	for all memory regions is correct.\r
	24	\r
	25	The basic idea is to use 2MB page table entries where ever possible. If\r
	26	more granularity of cachability is required then 4K page tables are used.\r
	27	\r
	28	References:\r
	29	1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
	30	2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
	31	3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
	32	\r
	33	--*/ \r
	34	\r
859b72fa	35	#include "DxeIpl.h"\r
95276127	36	#include "VirtualMemory.h"\r
95276127	37	\r
859b72fa	38	\r
95276127	39	UINTN\r
	40	CreateIdentityMappingPageTables (\r
	41	VOID\r
	42	)\r
	43	/*++\r
	44	\r
	45	Routine Description:\r
	46	\r
	47	Allocates and fills in the Page Directory and Page Table Entries to\r
	48	establish a 1:1 Virtual to Physical mapping.\r
	49	\r
	50	Arguments:\r
	51	\r
	52	NumberOfProcessorPhysicalAddressBits - Number of processor address bits to use.\r
	53	Limits the number of page table entries \r
	54	to the physical address space.\r
	55	\r
	56	Returns:\r
	57	\r
	58	EFI_SUCCESS The 1:1 Virtual to Physical identity mapping was created\r
	59	\r
	60	--*/\r
	61	{ \r
	62	UINT8 PhysicalAddressBits;\r
	63	EFI_PHYSICAL_ADDRESS PageAddress;\r
	64	UINTN IndexOfPml4Entries;\r
	65	UINTN IndexOfPdpEntries;\r
	66	UINTN IndexOfPageDirectoryEntries;\r
	67	UINTN NumberOfPml4EntriesNeeded;\r
	68	UINTN NumberOfPdpEntriesNeeded;\r
	69	PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry;\r
	70	PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;\r
	71	PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;\r
	72	PAGE_TABLE_ENTRY *PageDirectoryEntry;\r
	73	UINTN TotalPagesNum;\r
	74	UINTN BigPageAddress;\r
	75	VOID *Hob;\r
	76	\r
	77	//\r
	78	// Get physical address bits supported from CPU HOB.\r
	79	//\r
	80	PhysicalAddressBits = 36;\r
	81	\r
	82	Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
	83	if (Hob != NULL) {\r
	84	PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace; \r
	85	}\r
	86	\r
	87	//\r
	88	// Calculate the table entries needed.\r
	89	//\r
	90	if (PhysicalAddressBits <= 39 ) {\r
	91	NumberOfPml4EntriesNeeded = 1;\r
	92	NumberOfPdpEntriesNeeded = 1 << (PhysicalAddressBits - 30);\r
	93	} else {\r
	94	NumberOfPml4EntriesNeeded = 1 << (PhysicalAddressBits - 39);\r
	95	NumberOfPdpEntriesNeeded = 512;\r
	96	}\r
	97	\r
	98	//\r
	99	// Pre-allocate big pages to avoid later allocations. \r
	100	//\r
	101	TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;\r
	102	BigPageAddress = (UINTN) AllocatePages (TotalPagesNum);\r
103	ASSERT (BigPageAddress != 0);\r
104	\r
105	//\r
106	// By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
107	//\r
108	PageMap = (VOID *) BigPageAddress;\r
109	BigPageAddress += EFI_PAGE_SIZE;\r
110	\r
111	PageMapLevel4Entry = PageMap;\r
112	PageAddress = 0;\r
113	for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
114	//\r
115	// Each PML4 entry points to a page of Page Directory Pointer entires.\r
116	// So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.\r
117	//\r
118	PageDirectoryPointerEntry = (VOID *) BigPageAddress;\r
119	BigPageAddress += EFI_PAGE_SIZE;\r
120	\r
121	//\r
122	// Make a PML4 Entry\r
123	//\r
124	PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;\r
125	PageMapLevel4Entry->Bits.ReadWrite = 1;\r
126	PageMapLevel4Entry->Bits.Present = 1;\r
127	\r
128	for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
129	//\r
130	// Each Directory Pointer entries points to a page of Page Directory entires.\r
131	// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
132	// \r
133	PageDirectoryEntry = (VOID *) BigPageAddress;\r
134	BigPageAddress += EFI_PAGE_SIZE;\r
135	\r
136	//\r
137	// Fill in a Page Directory Pointer Entries\r
138	//\r
139	PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;\r
140	PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
141	PageDirectoryPointerEntry->Bits.Present = 1;\r
142	\r
143	for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += 0x200000) {\r
144	//\r
145	// Fill in the Page Directory entries\r
146	//\r
147	PageDirectoryEntry->Uint64 = (UINT64)PageAddress;\r
148	PageDirectoryEntry->Bits.ReadWrite = 1;\r
149	PageDirectoryEntry->Bits.Present = 1;\r
150	PageDirectoryEntry->Bits.MustBe1 = 1;\r
151	\r
152	}\r
153	}\r
154	}\r
155	\r
156	//\r
157	// For the PML4 entries we are not using fill in a null entry.\r
158	// For now we just copy the first entry.\r
159	//\r
160	for (; IndexOfPml4Entries < 512; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
161	CopyMem (\r
162	PageMapLevel4Entry,\r
163	PageMap,\r
164	sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)\r
165	);\r
166	}\r
167	\r
168	return (UINTN)PageMap; // FIXME\r
169	}\r
170	\r