Enable Nt32 platform boot to DXE phase.
[mirror_edk2.git] / MdeModulePkg / Core / DxeIplPeim / Ia32 / VirtualMemory.h
CommitLineData
95276127 1/*++ \r
2\r
3Copyright (c) 2006, Intel Corporation \r
4All rights reserved. This program and the accompanying materials \r
5are licensed and made available under the terms and conditions of the BSD License \r
6which accompanies this distribution. The full text of the license may be found at \r
7http://opensource.org/licenses/bsd-license.php \r
8 \r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
11\r
12Module Name:\r
13 VirtualMemory.h\r
14 \r
15Abstract:\r
16\r
17 x64 Long Mode Virtual Memory Management Definitions \r
18\r
19 References:\r
20 1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
21 2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
22 3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
23 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
24--*/ \r
25#ifndef _VIRTUAL_MEMORY_H_\r
26#define _VIRTUAL_MEMORY_H_\r
27\r
28\r
29//\r
30// Include common header file for this module.\r
31//\r
32#include "CommonHeader.h"\r
33\r
34#define SYS_CODE64_SEL 0x38\r
35\r
36#pragma pack(1)\r
37\r
38typedef union {\r
39 struct {\r
40 UINT32 LimitLow : 16;\r
41 UINT32 BaseLow : 16;\r
42 UINT32 BaseMid : 8;\r
43 UINT32 Type : 4;\r
44 UINT32 System : 1;\r
45 UINT32 Dpl : 2;\r
46 UINT32 Present : 1;\r
47 UINT32 LimitHigh : 4;\r
48 UINT32 Software : 1;\r
49 UINT32 Reserved : 1;\r
50 UINT32 DefaultSize : 1;\r
51 UINT32 Granularity : 1;\r
52 UINT32 BaseHigh : 8;\r
53 } Bits;\r
54 UINT64 Uint64;\r
55} IA32_GDT;\r
56\r
57//\r
58// Page-Map Level-4 Offset (PML4) and\r
59// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
60//\r
61\r
62typedef union {\r
63 struct {\r
64 UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
65 UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
66 UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
67 UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
68 UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
69 UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
70 UINT64 Reserved:1; // Reserved\r
71 UINT64 MustBeZero:2; // Must Be Zero\r
72 UINT64 Available:3; // Available for use by system software\r
73 UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
74 UINT64 AvabilableHigh:11; // Available for use by system software\r
75 UINT64 Nx:1; // No Execute bit\r
76 } Bits;\r
77 UINT64 Uint64;\r
78} PAGE_MAP_AND_DIRECTORY_POINTER;\r
79\r
80//\r
81// Page Table Entry 2MB\r
82//\r
83typedef union {\r
84 struct {\r
85 UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
86 UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
87 UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
88 UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
89 UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
90 UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
91 UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
92 UINT64 MustBe1:1; // Must be 1 \r
93 UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
94 UINT64 Available:3; // Available for use by system software\r
95 UINT64 PAT:1; //\r
96 UINT64 MustBeZero:8; // Must be zero;\r
97 UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
98 UINT64 AvabilableHigh:11; // Available for use by system software\r
99 UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
100 } Bits;\r
101 UINT64 Uint64;\r
102} PAGE_TABLE_ENTRY;\r
103\r
104#pragma pack()\r
105\r
106UINTN\r
107CreateIdentityMappingPageTables (\r
108 VOID\r
109 )\r
110;\r
111\r
112#endif \r