ArmPkg: only attempt buildin MmCommunicationDxe for AArch64
[mirror_edk2.git] / MdeModulePkg / Core / DxeIplPeim / X64 / VirtualMemory.c
CommitLineData
f3b33289 1/** @file\r
d1102dba 2 x64 Virtual Memory Management Services in the form of an IA-32 driver.\r
f3b33289 3 Used to establish a 1:1 Virtual to Physical Mapping that is required to\r
4 enter Long Mode (x64 64-bit mode).\r
5\r
d1102dba 6 While we make a 1:1 mapping (identity mapping) for all physical pages\r
4140a663 7 we still need to use the MTRR's to ensure that the cachability attributes\r
f3b33289 8 for all memory regions is correct.\r
9\r
10 The basic idea is to use 2MB page table entries where ever possible. If\r
11 more granularity of cachability is required then 4K page tables are used.\r
12\r
13 References:\r
4140a663 14 1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
15 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
16 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
f3b33289 17\r
b3527ded 18Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
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19Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
20\r
9d510e61 21SPDX-License-Identifier: BSD-2-Clause-Patent\r
f3b33289 22\r
d1102dba 23**/\r
f3b33289 24\r
b3527ded 25#include <Register/Intel/Cpuid.h>\r
f3b33289 26#include "DxeIpl.h"\r
27#include "VirtualMemory.h"\r
28\r
2ac1730b
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29//\r
30// Global variable to keep track current available memory used as page table.\r
31//\r
32PAGE_TABLE_POOL *mPageTablePool = NULL;\r
33\r
9189ec20 34/**\r
382aeac2 35 Clear legacy memory located at the first 4K-page, if available.\r
9189ec20 36\r
382aeac2
DB
37 This function traverses the whole HOB list to check if memory from 0 to 4095\r
38 exists and has not been allocated, and then clear it if so.\r
9189ec20 39\r
382aeac2 40 @param HobStart The start of HobList passed to DxeCore.\r
9189ec20
JW
41\r
42**/\r
43VOID\r
44ClearFirst4KPage (\r
45 IN VOID *HobStart\r
46 )\r
47{\r
48 EFI_PEI_HOB_POINTERS RscHob;\r
49 EFI_PEI_HOB_POINTERS MemHob;\r
50 BOOLEAN DoClear;\r
51\r
52 RscHob.Raw = HobStart;\r
53 MemHob.Raw = HobStart;\r
54 DoClear = FALSE;\r
55\r
56 //\r
57 // Check if page 0 exists and free\r
58 //\r
59 while ((RscHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,\r
60 RscHob.Raw)) != NULL) {\r
61 if (RscHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY &&\r
62 RscHob.ResourceDescriptor->PhysicalStart == 0) {\r
63 DoClear = TRUE;\r
64 //\r
65 // Make sure memory at 0-4095 has not been allocated.\r
66 //\r
67 while ((MemHob.Raw = GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION,\r
68 MemHob.Raw)) != NULL) {\r
69 if (MemHob.MemoryAllocation->AllocDescriptor.MemoryBaseAddress\r
70 < EFI_PAGE_SIZE) {\r
71 DoClear = FALSE;\r
72 break;\r
73 }\r
74 MemHob.Raw = GET_NEXT_HOB (MemHob);\r
75 }\r
76 break;\r
77 }\r
78 RscHob.Raw = GET_NEXT_HOB (RscHob);\r
79 }\r
80\r
81 if (DoClear) {\r
82 DEBUG ((DEBUG_INFO, "Clearing first 4K-page!\r\n"));\r
83 SetMem (NULL, EFI_PAGE_SIZE, 0);\r
84 }\r
85\r
86 return;\r
87}\r
88\r
382aeac2
DB
89/**\r
90 Return configure status of NULL pointer detection feature.\r
91\r
92 @return TRUE NULL pointer detection feature is enabled\r
93 @return FALSE NULL pointer detection feature is disabled\r
94\r
95**/\r
9189ec20
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96BOOLEAN\r
97IsNullDetectionEnabled (\r
98 VOID\r
99 )\r
100{\r
101 return ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT0) != 0);\r
102}\r
5997daf7 103\r
52679261
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104/**\r
105 The function will check if Execute Disable Bit is available.\r
106\r
107 @retval TRUE Execute Disable Bit is available.\r
108 @retval FALSE Execute Disable Bit is not available.\r
109\r
110**/\r
111BOOLEAN\r
112IsExecuteDisableBitAvailable (\r
113 VOID\r
114 )\r
115{\r
116 UINT32 RegEax;\r
117 UINT32 RegEdx;\r
118 BOOLEAN Available;\r
119\r
120 Available = FALSE;\r
121 AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
122 if (RegEax >= 0x80000001) {\r
123 AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
124 if ((RegEdx & BIT20) != 0) {\r
125 //\r
126 // Bit 20: Execute Disable Bit available.\r
127 //\r
128 Available = TRUE;\r
129 }\r
130 }\r
131\r
132 return Available;\r
133}\r
134\r
135/**\r
136 Check if Execute Disable Bit (IA32_EFER.NXE) should be enabled or not.\r
137\r
138 @retval TRUE IA32_EFER.NXE should be enabled.\r
139 @retval FALSE IA32_EFER.NXE should not be enabled.\r
140\r
141**/\r
142BOOLEAN\r
143IsEnableNonExecNeeded (\r
144 VOID\r
145 )\r
146{\r
147 if (!IsExecuteDisableBitAvailable ()) {\r
148 return FALSE;\r
149 }\r
150\r
151 //\r
152 // XD flag (BIT63) in page table entry is only valid if IA32_EFER.NXE is set.\r
153 // Features controlled by Following PCDs need this feature to be enabled.\r
154 //\r
155 return (PcdGetBool (PcdSetNxForStack) ||\r
156 PcdGet64 (PcdDxeNxMemoryProtectionPolicy) != 0 ||\r
157 PcdGet32 (PcdImageProtectionPolicy) != 0);\r
158}\r
159\r
5630cdfe
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160/**\r
161 Enable Execute Disable Bit.\r
162\r
163**/\r
164VOID\r
165EnableExecuteDisableBit (\r
166 VOID\r
167 )\r
168{\r
169 UINT64 MsrRegisters;\r
170\r
171 MsrRegisters = AsmReadMsr64 (0xC0000080);\r
172 MsrRegisters |= BIT11;\r
173 AsmWriteMsr64 (0xC0000080, MsrRegisters);\r
174}\r
175\r
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176/**\r
177 The function will check if page table entry should be splitted to smaller\r
178 granularity.\r
179\r
9db7e9fd
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180 @param Address Physical memory address.\r
181 @param Size Size of the given physical memory.\r
182 @param StackBase Base address of stack.\r
183 @param StackSize Size of stack.\r
184\r
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185 @retval TRUE Page table should be split.\r
186 @retval FALSE Page table should not be split.\r
187**/\r
188BOOLEAN\r
189ToSplitPageTable (\r
190 IN EFI_PHYSICAL_ADDRESS Address,\r
191 IN UINTN Size,\r
192 IN EFI_PHYSICAL_ADDRESS StackBase,\r
193 IN UINTN StackSize\r
194 )\r
195{\r
196 if (IsNullDetectionEnabled () && Address == 0) {\r
197 return TRUE;\r
198 }\r
199\r
200 if (PcdGetBool (PcdCpuStackGuard)) {\r
201 if (StackBase >= Address && StackBase < (Address + Size)) {\r
202 return TRUE;\r
203 }\r
204 }\r
205\r
206 if (PcdGetBool (PcdSetNxForStack)) {\r
207 if ((Address < StackBase + StackSize) && ((Address + Size) > StackBase)) {\r
208 return TRUE;\r
209 }\r
210 }\r
211\r
212 return FALSE;\r
213}\r
2ac1730b
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214/**\r
215 Initialize a buffer pool for page table use only.\r
216\r
217 To reduce the potential split operation on page table, the pages reserved for\r
218 page table should be allocated in the times of PAGE_TABLE_POOL_UNIT_PAGES and\r
219 at the boundary of PAGE_TABLE_POOL_ALIGNMENT. So the page pool is always\r
220 initialized with number of pages greater than or equal to the given PoolPages.\r
221\r
222 Once the pages in the pool are used up, this method should be called again to\r
223 reserve at least another PAGE_TABLE_POOL_UNIT_PAGES. But usually this won't\r
224 happen in practice.\r
225\r
226 @param PoolPages The least page number of the pool to be created.\r
227\r
228 @retval TRUE The pool is initialized successfully.\r
229 @retval FALSE The memory is out of resource.\r
230**/\r
231BOOLEAN\r
232InitializePageTablePool (\r
233 IN UINTN PoolPages\r
234 )\r
235{\r
236 VOID *Buffer;\r
237\r
238 //\r
239 // Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one page for\r
240 // header.\r
241 //\r
242 PoolPages += 1; // Add one page for header.\r
243 PoolPages = ((PoolPages - 1) / PAGE_TABLE_POOL_UNIT_PAGES + 1) *\r
244 PAGE_TABLE_POOL_UNIT_PAGES;\r
245 Buffer = AllocateAlignedPages (PoolPages, PAGE_TABLE_POOL_ALIGNMENT);\r
246 if (Buffer == NULL) {\r
247 DEBUG ((DEBUG_ERROR, "ERROR: Out of aligned pages\r\n"));\r
248 return FALSE;\r
249 }\r
250\r
251 //\r
252 // Link all pools into a list for easier track later.\r
253 //\r
254 if (mPageTablePool == NULL) {\r
255 mPageTablePool = Buffer;\r
256 mPageTablePool->NextPool = mPageTablePool;\r
257 } else {\r
258 ((PAGE_TABLE_POOL *)Buffer)->NextPool = mPageTablePool->NextPool;\r
259 mPageTablePool->NextPool = Buffer;\r
260 mPageTablePool = Buffer;\r
261 }\r
262\r
263 //\r
264 // Reserve one page for pool header.\r
265 //\r
266 mPageTablePool->FreePages = PoolPages - 1;\r
267 mPageTablePool->Offset = EFI_PAGES_TO_SIZE (1);\r
268\r
269 return TRUE;\r
270}\r
271\r
272/**\r
273 This API provides a way to allocate memory for page table.\r
274\r
275 This API can be called more than once to allocate memory for page tables.\r
276\r
277 Allocates the number of 4KB pages and returns a pointer to the allocated\r
278 buffer. The buffer returned is aligned on a 4KB boundary.\r
279\r
280 If Pages is 0, then NULL is returned.\r
281 If there is not enough memory remaining to satisfy the request, then NULL is\r
282 returned.\r
283\r
284 @param Pages The number of 4 KB pages to allocate.\r
285\r
286 @return A pointer to the allocated buffer or NULL if allocation fails.\r
287\r
288**/\r
289VOID *\r
290AllocatePageTableMemory (\r
291 IN UINTN Pages\r
292 )\r
293{\r
294 VOID *Buffer;\r
295\r
296 if (Pages == 0) {\r
297 return NULL;\r
298 }\r
299\r
300 //\r
301 // Renew the pool if necessary.\r
302 //\r
303 if (mPageTablePool == NULL ||\r
304 Pages > mPageTablePool->FreePages) {\r
305 if (!InitializePageTablePool (Pages)) {\r
306 return NULL;\r
307 }\r
308 }\r
309\r
310 Buffer = (UINT8 *)mPageTablePool + mPageTablePool->Offset;\r
311\r
312 mPageTablePool->Offset += EFI_PAGES_TO_SIZE (Pages);\r
313 mPageTablePool->FreePages -= Pages;\r
314\r
315 return Buffer;\r
316}\r
317\r
5630cdfe
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318/**\r
319 Split 2M page to 4K.\r
320\r
321 @param[in] PhysicalAddress Start physical address the 2M page covered.\r
322 @param[in, out] PageEntry2M Pointer to 2M page entry.\r
323 @param[in] StackBase Stack base address.\r
324 @param[in] StackSize Stack size.\r
325\r
326**/\r
327VOID\r
328Split2MPageTo4K (\r
329 IN EFI_PHYSICAL_ADDRESS PhysicalAddress,\r
330 IN OUT UINT64 *PageEntry2M,\r
331 IN EFI_PHYSICAL_ADDRESS StackBase,\r
332 IN UINTN StackSize\r
333 )\r
334{\r
335 EFI_PHYSICAL_ADDRESS PhysicalAddress4K;\r
336 UINTN IndexOfPageTableEntries;\r
337 PAGE_TABLE_4K_ENTRY *PageTableEntry;\r
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338 UINT64 AddressEncMask;\r
339\r
340 //\r
341 // Make sure AddressEncMask is contained to smallest supported address field\r
342 //\r
343 AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
5630cdfe 344\r
2ac1730b 345 PageTableEntry = AllocatePageTableMemory (1);\r
36829e67 346 ASSERT (PageTableEntry != NULL);\r
5997daf7 347\r
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348 //\r
349 // Fill in 2M page entry.\r
350 //\r
5997daf7 351 *PageEntry2M = (UINT64) (UINTN) PageTableEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW;\r
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352\r
353 PhysicalAddress4K = PhysicalAddress;\r
354 for (IndexOfPageTableEntries = 0; IndexOfPageTableEntries < 512; IndexOfPageTableEntries++, PageTableEntry++, PhysicalAddress4K += SIZE_4KB) {\r
355 //\r
356 // Fill in the Page Table entries\r
357 //\r
5997daf7 358 PageTableEntry->Uint64 = (UINT64) PhysicalAddress4K | AddressEncMask;\r
5630cdfe 359 PageTableEntry->Bits.ReadWrite = 1;\r
9189ec20 360\r
50255363
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361 if ((IsNullDetectionEnabled () && PhysicalAddress4K == 0) ||\r
362 (PcdGetBool (PcdCpuStackGuard) && PhysicalAddress4K == StackBase)) {\r
9189ec20
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363 PageTableEntry->Bits.Present = 0;\r
364 } else {\r
365 PageTableEntry->Bits.Present = 1;\r
366 }\r
367\r
368 if (PcdGetBool (PcdSetNxForStack)\r
369 && (PhysicalAddress4K >= StackBase)\r
370 && (PhysicalAddress4K < StackBase + StackSize)) {\r
5630cdfe
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371 //\r
372 // Set Nx bit for stack.\r
373 //\r
374 PageTableEntry->Bits.Nx = 1;\r
375 }\r
376 }\r
377}\r
378\r
379/**\r
380 Split 1G page to 2M.\r
381\r
382 @param[in] PhysicalAddress Start physical address the 1G page covered.\r
383 @param[in, out] PageEntry1G Pointer to 1G page entry.\r
384 @param[in] StackBase Stack base address.\r
385 @param[in] StackSize Stack size.\r
386\r
387**/\r
388VOID\r
389Split1GPageTo2M (\r
390 IN EFI_PHYSICAL_ADDRESS PhysicalAddress,\r
391 IN OUT UINT64 *PageEntry1G,\r
392 IN EFI_PHYSICAL_ADDRESS StackBase,\r
393 IN UINTN StackSize\r
394 )\r
395{\r
396 EFI_PHYSICAL_ADDRESS PhysicalAddress2M;\r
397 UINTN IndexOfPageDirectoryEntries;\r
398 PAGE_TABLE_ENTRY *PageDirectoryEntry;\r
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399 UINT64 AddressEncMask;\r
400\r
401 //\r
402 // Make sure AddressEncMask is contained to smallest supported address field\r
403 //\r
404 AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
5630cdfe 405\r
2ac1730b 406 PageDirectoryEntry = AllocatePageTableMemory (1);\r
36829e67 407 ASSERT (PageDirectoryEntry != NULL);\r
5997daf7 408\r
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409 //\r
410 // Fill in 1G page entry.\r
411 //\r
5997daf7 412 *PageEntry1G = (UINT64) (UINTN) PageDirectoryEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW;\r
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413\r
414 PhysicalAddress2M = PhysicalAddress;\r
415 for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += SIZE_2MB) {\r
50255363 416 if (ToSplitPageTable (PhysicalAddress2M, SIZE_2MB, StackBase, StackSize)) {\r
5630cdfe 417 //\r
9189ec20 418 // Need to split this 2M page that covers NULL or stack range.\r
5630cdfe
SZ
419 //\r
420 Split2MPageTo4K (PhysicalAddress2M, (UINT64 *) PageDirectoryEntry, StackBase, StackSize);\r
421 } else {\r
422 //\r
423 // Fill in the Page Directory entries\r
424 //\r
5997daf7 425 PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress2M | AddressEncMask;\r
5630cdfe
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426 PageDirectoryEntry->Bits.ReadWrite = 1;\r
427 PageDirectoryEntry->Bits.Present = 1;\r
428 PageDirectoryEntry->Bits.MustBe1 = 1;\r
429 }\r
430 }\r
431}\r
432\r
2ac1730b
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433/**\r
434 Set one page of page table pool memory to be read-only.\r
435\r
436 @param[in] PageTableBase Base address of page table (CR3).\r
437 @param[in] Address Start address of a page to be set as read-only.\r
438 @param[in] Level4Paging Level 4 paging flag.\r
439\r
440**/\r
441VOID\r
442SetPageTablePoolReadOnly (\r
443 IN UINTN PageTableBase,\r
444 IN EFI_PHYSICAL_ADDRESS Address,\r
445 IN BOOLEAN Level4Paging\r
446 )\r
447{\r
448 UINTN Index;\r
449 UINTN EntryIndex;\r
450 UINT64 AddressEncMask;\r
451 EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
452 UINT64 *PageTable;\r
453 UINT64 *NewPageTable;\r
454 UINT64 PageAttr;\r
455 UINT64 LevelSize[5];\r
456 UINT64 LevelMask[5];\r
457 UINTN LevelShift[5];\r
458 UINTN Level;\r
459 UINT64 PoolUnitSize;\r
460\r
461 ASSERT (PageTableBase != 0);\r
462\r
463 //\r
464 // Since the page table is always from page table pool, which is always\r
465 // located at the boundary of PcdPageTablePoolAlignment, we just need to\r
466 // set the whole pool unit to be read-only.\r
467 //\r
468 Address = Address & PAGE_TABLE_POOL_ALIGN_MASK;\r
469\r
470 LevelShift[1] = PAGING_L1_ADDRESS_SHIFT;\r
471 LevelShift[2] = PAGING_L2_ADDRESS_SHIFT;\r
472 LevelShift[3] = PAGING_L3_ADDRESS_SHIFT;\r
473 LevelShift[4] = PAGING_L4_ADDRESS_SHIFT;\r
474\r
475 LevelMask[1] = PAGING_4K_ADDRESS_MASK_64;\r
476 LevelMask[2] = PAGING_2M_ADDRESS_MASK_64;\r
477 LevelMask[3] = PAGING_1G_ADDRESS_MASK_64;\r
478 LevelMask[4] = PAGING_1G_ADDRESS_MASK_64;\r
479\r
480 LevelSize[1] = SIZE_4KB;\r
481 LevelSize[2] = SIZE_2MB;\r
482 LevelSize[3] = SIZE_1GB;\r
483 LevelSize[4] = SIZE_512GB;\r
484\r
485 AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &\r
486 PAGING_1G_ADDRESS_MASK_64;\r
487 PageTable = (UINT64 *)(UINTN)PageTableBase;\r
488 PoolUnitSize = PAGE_TABLE_POOL_UNIT_SIZE;\r
489\r
490 for (Level = (Level4Paging) ? 4 : 3; Level > 0; --Level) {\r
491 Index = ((UINTN)RShiftU64 (Address, LevelShift[Level]));\r
492 Index &= PAGING_PAE_INDEX_MASK;\r
493\r
494 PageAttr = PageTable[Index];\r
495 if ((PageAttr & IA32_PG_PS) == 0) {\r
496 //\r
497 // Go to next level of table.\r
498 //\r
499 PageTable = (UINT64 *)(UINTN)(PageAttr & ~AddressEncMask &\r
500 PAGING_4K_ADDRESS_MASK_64);\r
501 continue;\r
502 }\r
503\r
504 if (PoolUnitSize >= LevelSize[Level]) {\r
505 //\r
506 // Clear R/W bit if current page granularity is not larger than pool unit\r
507 // size.\r
508 //\r
509 if ((PageAttr & IA32_PG_RW) != 0) {\r
510 while (PoolUnitSize > 0) {\r
511 //\r
512 // PAGE_TABLE_POOL_UNIT_SIZE and PAGE_TABLE_POOL_ALIGNMENT are fit in\r
513 // one page (2MB). Then we don't need to update attributes for pages\r
514 // crossing page directory. ASSERT below is for that purpose.\r
515 //\r
516 ASSERT (Index < EFI_PAGE_SIZE/sizeof (UINT64));\r
517\r
518 PageTable[Index] &= ~(UINT64)IA32_PG_RW;\r
519 PoolUnitSize -= LevelSize[Level];\r
520\r
521 ++Index;\r
522 }\r
523 }\r
524\r
525 break;\r
526\r
527 } else {\r
528 //\r
529 // The smaller granularity of page must be needed.\r
530 //\r
41b4600c
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531 ASSERT (Level > 1);\r
532\r
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533 NewPageTable = AllocatePageTableMemory (1);\r
534 ASSERT (NewPageTable != NULL);\r
535\r
536 PhysicalAddress = PageAttr & LevelMask[Level];\r
537 for (EntryIndex = 0;\r
538 EntryIndex < EFI_PAGE_SIZE/sizeof (UINT64);\r
539 ++EntryIndex) {\r
540 NewPageTable[EntryIndex] = PhysicalAddress | AddressEncMask |\r
541 IA32_PG_P | IA32_PG_RW;\r
41b4600c 542 if (Level > 2) {\r
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543 NewPageTable[EntryIndex] |= IA32_PG_PS;\r
544 }\r
41b4600c 545 PhysicalAddress += LevelSize[Level - 1];\r
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546 }\r
547\r
548 PageTable[Index] = (UINT64)(UINTN)NewPageTable | AddressEncMask |\r
549 IA32_PG_P | IA32_PG_RW;\r
550 PageTable = NewPageTable;\r
551 }\r
552 }\r
553}\r
554\r
555/**\r
556 Prevent the memory pages used for page table from been overwritten.\r
557\r
558 @param[in] PageTableBase Base address of page table (CR3).\r
559 @param[in] Level4Paging Level 4 paging flag.\r
560\r
561**/\r
562VOID\r
563EnablePageTableProtection (\r
564 IN UINTN PageTableBase,\r
565 IN BOOLEAN Level4Paging\r
566 )\r
567{\r
568 PAGE_TABLE_POOL *HeadPool;\r
569 PAGE_TABLE_POOL *Pool;\r
570 UINT64 PoolSize;\r
571 EFI_PHYSICAL_ADDRESS Address;\r
572\r
573 if (mPageTablePool == NULL) {\r
574 return;\r
575 }\r
576\r
577 //\r
578 // Disable write protection, because we need to mark page table to be write\r
579 // protected.\r
580 //\r
581 AsmWriteCr0 (AsmReadCr0() & ~CR0_WP);\r
582\r
583 //\r
584 // SetPageTablePoolReadOnly might update mPageTablePool. It's safer to\r
585 // remember original one in advance.\r
586 //\r
587 HeadPool = mPageTablePool;\r
588 Pool = HeadPool;\r
589 do {\r
590 Address = (EFI_PHYSICAL_ADDRESS)(UINTN)Pool;\r
591 PoolSize = Pool->Offset + EFI_PAGES_TO_SIZE (Pool->FreePages);\r
592\r
593 //\r
594 // The size of one pool must be multiple of PAGE_TABLE_POOL_UNIT_SIZE, which\r
595 // is one of page size of the processor (2MB by default). Let's apply the\r
596 // protection to them one by one.\r
597 //\r
598 while (PoolSize > 0) {\r
599 SetPageTablePoolReadOnly(PageTableBase, Address, Level4Paging);\r
600 Address += PAGE_TABLE_POOL_UNIT_SIZE;\r
601 PoolSize -= PAGE_TABLE_POOL_UNIT_SIZE;\r
602 }\r
603\r
604 Pool = Pool->NextPool;\r
605 } while (Pool != HeadPool);\r
606\r
607 //\r
608 // Enable write protection, after page table attribute updated.\r
609 //\r
610 AsmWriteCr0 (AsmReadCr0() | CR0_WP);\r
611}\r
612\r
f3b33289 613/**\r
614 Allocates and fills in the Page Directory and Page Table Entries to\r
615 establish a 1:1 Virtual to Physical mapping.\r
616\r
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617 @param[in] StackBase Stack base address.\r
618 @param[in] StackSize Stack size.\r
f3b33289 619\r
48557c65 620 @return The address of 4 level page map.\r
f3b33289 621\r
622**/\r
623UINTN\r
624CreateIdentityMappingPageTables (\r
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625 IN EFI_PHYSICAL_ADDRESS StackBase,\r
626 IN UINTN StackSize\r
f3b33289 627 )\r
d1102dba 628{\r
c56b6566 629 UINT32 RegEax;\r
b3527ded 630 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX EcxFlags;\r
c56b6566 631 UINT32 RegEdx;\r
f3b33289 632 UINT8 PhysicalAddressBits;\r
633 EFI_PHYSICAL_ADDRESS PageAddress;\r
b3527ded 634 UINTN IndexOfPml5Entries;\r
f3b33289 635 UINTN IndexOfPml4Entries;\r
636 UINTN IndexOfPdpEntries;\r
637 UINTN IndexOfPageDirectoryEntries;\r
b3527ded 638 UINT32 NumberOfPml5EntriesNeeded;\r
4140a663 639 UINT32 NumberOfPml4EntriesNeeded;\r
640 UINT32 NumberOfPdpEntriesNeeded;\r
b3527ded 641 PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel5Entry;\r
f3b33289 642 PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry;\r
643 PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;\r
644 PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;\r
645 PAGE_TABLE_ENTRY *PageDirectoryEntry;\r
646 UINTN TotalPagesNum;\r
647 UINTN BigPageAddress;\r
648 VOID *Hob;\r
b3527ded 649 BOOLEAN Page5LevelSupport;\r
c56b6566
JY
650 BOOLEAN Page1GSupport;\r
651 PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;\r
5997daf7 652 UINT64 AddressEncMask;\r
b3527ded 653 IA32_CR4 Cr4;\r
5997daf7 654\r
0680d086
SZ
655 //\r
656 // Set PageMapLevel5Entry to suppress incorrect compiler/analyzer warnings\r
657 //\r
658 PageMapLevel5Entry = NULL;\r
659\r
5997daf7
LD
660 //\r
661 // Make sure AddressEncMask is contained to smallest supported address field\r
662 //\r
663 AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
c56b6566
JY
664\r
665 Page1GSupport = FALSE;\r
378175d2
JY
666 if (PcdGetBool(PcdUse1GPageTable)) {\r
667 AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
668 if (RegEax >= 0x80000001) {\r
669 AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
670 if ((RegEdx & BIT26) != 0) {\r
671 Page1GSupport = TRUE;\r
672 }\r
c56b6566
JY
673 }\r
674 }\r
f3b33289 675\r
676 //\r
c56b6566 677 // Get physical address bits supported.\r
f3b33289 678 //\r
f3b33289 679 Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
680 if (Hob != NULL) {\r
48557c65 681 PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;\r
c56b6566
JY
682 } else {\r
683 AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
684 if (RegEax >= 0x80000008) {\r
685 AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
686 PhysicalAddressBits = (UINT8) RegEax;\r
687 } else {\r
688 PhysicalAddressBits = 36;\r
689 }\r
f3b33289 690 }\r
691\r
b3527ded
RN
692 Page5LevelSupport = FALSE;\r
693 if (PcdGetBool (PcdUse5LevelPageTable)) {\r
694 AsmCpuidEx (\r
695 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL,\r
696 &EcxFlags.Uint32, NULL, NULL\r
697 );\r
698 if (EcxFlags.Bits.FiveLevelPage != 0) {\r
699 Page5LevelSupport = TRUE;\r
700 }\r
701 }\r
702\r
703 DEBUG ((DEBUG_INFO, "AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Page5LevelSupport, Page1GSupport));\r
704\r
4140a663 705 //\r
b3527ded
RN
706 // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses\r
707 // when 5-Level Paging is disabled,\r
708 // due to either unsupported by HW, or disabled by PCD.\r
4140a663 709 //\r
710 ASSERT (PhysicalAddressBits <= 52);\r
b3527ded 711 if (!Page5LevelSupport && PhysicalAddressBits > 48) {\r
4140a663 712 PhysicalAddressBits = 48;\r
713 }\r
714\r
f3b33289 715 //\r
716 // Calculate the table entries needed.\r
717 //\r
b3527ded
RN
718 NumberOfPml5EntriesNeeded = 1;\r
719 if (PhysicalAddressBits > 48) {\r
720 NumberOfPml5EntriesNeeded = (UINT32) LShiftU64 (1, PhysicalAddressBits - 48);\r
721 PhysicalAddressBits = 48;\r
722 }\r
723\r
724 NumberOfPml4EntriesNeeded = 1;\r
725 if (PhysicalAddressBits > 39) {\r
726 NumberOfPml4EntriesNeeded = (UINT32) LShiftU64 (1, PhysicalAddressBits - 39);\r
727 PhysicalAddressBits = 39;\r
f3b33289 728 }\r
729\r
b3527ded
RN
730 NumberOfPdpEntriesNeeded = 1;\r
731 ASSERT (PhysicalAddressBits > 30);\r
732 NumberOfPdpEntriesNeeded = (UINT32) LShiftU64 (1, PhysicalAddressBits - 30);\r
733\r
f3b33289 734 //\r
d1102dba 735 // Pre-allocate big pages to avoid later allocations.\r
f3b33289 736 //\r
c56b6566 737 if (!Page1GSupport) {\r
b3527ded 738 TotalPagesNum = ((NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1) * NumberOfPml5EntriesNeeded + 1;\r
c56b6566 739 } else {\r
b3527ded
RN
740 TotalPagesNum = (NumberOfPml4EntriesNeeded + 1) * NumberOfPml5EntriesNeeded + 1;\r
741 }\r
742\r
743 //\r
744 // Substract the one page occupied by PML5 entries if 5-Level Paging is disabled.\r
745 //\r
746 if (!Page5LevelSupport) {\r
747 TotalPagesNum--;\r
c56b6566 748 }\r
b3527ded
RN
749\r
750 DEBUG ((DEBUG_INFO, "Pml5=%u Pml4=%u Pdp=%u TotalPage=%Lu\n",\r
751 NumberOfPml5EntriesNeeded, NumberOfPml4EntriesNeeded,\r
752 NumberOfPdpEntriesNeeded, (UINT64)TotalPagesNum));\r
753\r
2ac1730b 754 BigPageAddress = (UINTN) AllocatePageTableMemory (TotalPagesNum);\r
f3b33289 755 ASSERT (BigPageAddress != 0);\r
756\r
757 //\r
758 // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
759 //\r
760 PageMap = (VOID *) BigPageAddress;\r
b3527ded 761 if (Page5LevelSupport) {\r
f3b33289 762 //\r
b3527ded 763 // By architecture only one PageMapLevel5 exists - so lets allocate storage for it.\r
f3b33289 764 //\r
b3527ded
RN
765 PageMapLevel5Entry = PageMap;\r
766 BigPageAddress += SIZE_4KB;\r
767 }\r
768 PageAddress = 0;\r
f3b33289 769\r
b3527ded
RN
770 for ( IndexOfPml5Entries = 0\r
771 ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded\r
46f8a689 772 ; IndexOfPml5Entries++) {\r
f3b33289 773 //\r
b3527ded
RN
774 // Each PML5 entry points to a page of PML4 entires.\r
775 // So lets allocate space for them and fill them in in the IndexOfPml4Entries loop.\r
776 // When 5-Level Paging is disabled, below allocation happens only once.\r
f3b33289 777 //\r
b3527ded
RN
778 PageMapLevel4Entry = (VOID *) BigPageAddress;\r
779 BigPageAddress += SIZE_4KB;\r
f3b33289 780\r
b3527ded
RN
781 if (Page5LevelSupport) {\r
782 //\r
783 // Make a PML5 Entry\r
784 //\r
785 PageMapLevel5Entry->Uint64 = (UINT64) (UINTN) PageMapLevel4Entry | AddressEncMask;\r
786 PageMapLevel5Entry->Bits.ReadWrite = 1;\r
787 PageMapLevel5Entry->Bits.Present = 1;\r
46f8a689 788 PageMapLevel5Entry++;\r
b3527ded 789 }\r
d1102dba 790\r
b3527ded
RN
791 for ( IndexOfPml4Entries = 0\r
792 ; IndexOfPml4Entries < (NumberOfPml5EntriesNeeded == 1 ? NumberOfPml4EntriesNeeded : 512)\r
793 ; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
794 //\r
795 // Each PML4 entry points to a page of Page Directory Pointer entires.\r
796 // So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.\r
797 //\r
798 PageDirectoryPointerEntry = (VOID *) BigPageAddress;\r
799 BigPageAddress += SIZE_4KB;\r
c56b6566 800\r
b3527ded
RN
801 //\r
802 // Make a PML4 Entry\r
803 //\r
804 PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask;\r
805 PageMapLevel4Entry->Bits.ReadWrite = 1;\r
806 PageMapLevel4Entry->Bits.Present = 1;\r
c56b6566 807\r
b3527ded
RN
808 if (Page1GSupport) {\r
809 PageDirectory1GEntry = (VOID *) PageDirectoryPointerEntry;\r
810\r
811 for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {\r
812 if (ToSplitPageTable (PageAddress, SIZE_1GB, StackBase, StackSize)) {\r
813 Split1GPageTo2M (PageAddress, (UINT64 *) PageDirectory1GEntry, StackBase, StackSize);\r
5630cdfe
SZ
814 } else {\r
815 //\r
816 // Fill in the Page Directory entries\r
817 //\r
b3527ded
RN
818 PageDirectory1GEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;\r
819 PageDirectory1GEntry->Bits.ReadWrite = 1;\r
820 PageDirectory1GEntry->Bits.Present = 1;\r
821 PageDirectory1GEntry->Bits.MustBe1 = 1;\r
5630cdfe 822 }\r
c56b6566 823 }\r
b3527ded
RN
824 } else {\r
825 for ( IndexOfPdpEntries = 0\r
826 ; IndexOfPdpEntries < (NumberOfPml4EntriesNeeded == 1 ? NumberOfPdpEntriesNeeded : 512)\r
827 ; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
828 //\r
829 // Each Directory Pointer entries points to a page of Page Directory entires.\r
830 // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
831 //\r
832 PageDirectoryEntry = (VOID *) BigPageAddress;\r
833 BigPageAddress += SIZE_4KB;\r
f3b33289 834\r
b3527ded
RN
835 //\r
836 // Fill in a Page Directory Pointer Entries\r
837 //\r
838 PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask;\r
839 PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
840 PageDirectoryPointerEntry->Bits.Present = 1;\r
841\r
842 for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {\r
843 if (ToSplitPageTable (PageAddress, SIZE_2MB, StackBase, StackSize)) {\r
844 //\r
845 // Need to split this 2M page that covers NULL or stack range.\r
846 //\r
847 Split2MPageTo4K (PageAddress, (UINT64 *) PageDirectoryEntry, StackBase, StackSize);\r
848 } else {\r
849 //\r
850 // Fill in the Page Directory entries\r
851 //\r
852 PageDirectoryEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;\r
853 PageDirectoryEntry->Bits.ReadWrite = 1;\r
854 PageDirectoryEntry->Bits.Present = 1;\r
855 PageDirectoryEntry->Bits.MustBe1 = 1;\r
856 }\r
857 }\r
858 }\r
859\r
860 //\r
861 // Fill with null entry for unused PDPTE\r
862 //\r
863 ZeroMem (PageDirectoryPointerEntry, (512 - IndexOfPdpEntries) * sizeof(PAGE_MAP_AND_DIRECTORY_POINTER));\r
f3b33289 864 }\r
865 }\r
b3527ded
RN
866\r
867 //\r
868 // For the PML4 entries we are not using fill in a null entry.\r
869 //\r
870 ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PAGE_MAP_AND_DIRECTORY_POINTER));\r
f3b33289 871 }\r
872\r
b3527ded
RN
873 if (Page5LevelSupport) {\r
874 Cr4.UintN = AsmReadCr4 ();\r
875 Cr4.Bits.LA57 = 1;\r
876 AsmWriteCr4 (Cr4.UintN);\r
877 //\r
878 // For the PML5 entries we are not using fill in a null entry.\r
879 //\r
880 ZeroMem (PageMapLevel5Entry, (512 - IndexOfPml5Entries) * sizeof (PAGE_MAP_AND_DIRECTORY_POINTER));\r
f3b33289 881 }\r
882\r
2ac1730b
JW
883 //\r
884 // Protect the page table by marking the memory used for page table to be\r
885 // read-only.\r
886 //\r
887 EnablePageTableProtection ((UINTN)PageMap, TRUE);\r
888\r
52679261
JW
889 //\r
890 // Set IA32_EFER.NXE if necessary.\r
891 //\r
892 if (IsEnableNonExecNeeded ()) {\r
5630cdfe
SZ
893 EnableExecuteDisableBit ();\r
894 }\r
895\r
f3b33289 896 return (UINTN)PageMap;\r
897}\r
898\r