[mirror_edk2.git] / MdeModulePkg / Core / DxeIplPeim / X64 / VirtualMemory.h

/** @file\r
  x64 Long Mode Virtual Memory Management Definitions  \r
\r
  References:\r
    1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
    2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
    3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
    4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
\r
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/  \r
#ifndef _VIRTUAL_MEMORY_H_\r
#define _VIRTUAL_MEMORY_H_\r
\r
\r
#define SYS_CODE64_SEL 0x38\r
\r
#pragma pack(1)\r
\r
typedef union {\r
  struct {\r
    UINT32  LimitLow    : 16;\r
    UINT32  BaseLow     : 16;\r
    UINT32  BaseMid     : 8;\r
    UINT32  Type        : 4;\r
    UINT32  System      : 1;\r
    UINT32  Dpl         : 2;\r
    UINT32  Present     : 1;\r
    UINT32  LimitHigh   : 4;\r
    UINT32  Software    : 1;\r
    UINT32  Reserved    : 1;\r
    UINT32  DefaultSize : 1;\r
    UINT32  Granularity : 1;\r
    UINT32  BaseHigh    : 8;\r
  } Bits;\r
  UINT64  Uint64;\r
} IA32_GDT;\r
\r
typedef struct {\r
  IA32_IDT_GATE_DESCRIPTOR  Ia32IdtEntry;\r
  UINT32                    Offset32To63;\r
  UINT32                    Reserved;\r
} X64_IDT_GATE_DESCRIPTOR;\r
\r
//\r
// Page-Map Level-4 Offset (PML4) and\r
// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
//\r
\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Reserved:1;               // Reserved\r
    UINT64  MustBeZero:2;             // Must Be Zero\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // No Execute bit\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_MAP_AND_DIRECTORY_POINTER;\r
\r
//\r
// Page Table Entry 4KB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  PAT:1;                    //\r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_4K_ENTRY;\r
\r
//\r
// Page Table Entry 2MB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  MustBe1:1;                // Must be 1 \r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PAT:1;                    //\r
    UINT64  MustBeZero:8;             // Must be zero;\r
    UINT64  PageTableBaseAddress:31;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_ENTRY;\r
\r
//\r
// Page Table Entry 1GB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  MustBe1:1;                // Must be 1 \r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PAT:1;                    //\r
    UINT64  MustBeZero:17;            // Must be zero;\r
    UINT64  PageTableBaseAddress:22;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_1G_ENTRY;\r
\r
#pragma pack()\r
\r
#define IA32_PG_P                   BIT0\r
#define IA32_PG_RW                  BIT1\r
\r
/**\r
  Enable Execute Disable Bit.\r
\r
**/\r
VOID\r
EnableExecuteDisableBit (\r
  VOID\r
  );\r
\r
/**\r
  Split 2M page to 4K.\r
\r
  @param[in]      PhysicalAddress       Start physical address the 2M page covered.\r
  @param[in, out] PageEntry2M           Pointer to 2M page entry.\r
  @param[in]      StackBase             Stack base address.\r
  @param[in]      StackSize             Stack size.\r
\r
**/\r
VOID\r
Split2MPageTo4K (\r
  IN EFI_PHYSICAL_ADDRESS               PhysicalAddress,\r
  IN OUT UINT64                         *PageEntry2M,\r
  IN EFI_PHYSICAL_ADDRESS               StackBase,\r
  IN UINTN                              StackSize\r
  );\r
\r
/**\r
  Allocates and fills in the Page Directory and Page Table Entries to\r
  establish a 1:1 Virtual to Physical mapping.\r
\r
  @param[in] StackBase  Stack base address.\r
  @param[in] StackSize  Stack size.\r
\r
  @return The address of 4 level page map.\r
\r
**/\r
UINTN\r
CreateIdentityMappingPageTables (\r
  IN EFI_PHYSICAL_ADDRESS   StackBase,\r
  IN UINTN                  StackSize\r
  );\r
\r
\r
/**\r
 \r
  Fix up the vector number in the vector code.\r
 \r
  @param VectorBase   Base address of the vector handler.\r
  @param VectorNum    Index of vector.\r
\r
**/\r
VOID\r
EFIAPI\r
AsmVectorFixup (\r
  VOID    *VectorBase,\r
  UINT8   VectorNum\r
  );\r
\r
\r
/**\r
 \r
  Get the information of vector template.\r
  \r
  @param TemplateBase   Base address of the template code.\r
 \r
  @return               Size of the Template code.\r
\r
**/\r
UINTN\r
EFIAPI\r
AsmGetVectorTemplatInfo (\r
  OUT   VOID  **TemplateBase\r
  );\r
\r
\r
#endif \r
Commit	Line	Data
f3b33289	1	/** @file\r
	2	x64 Long Mode Virtual Memory Management Definitions \r
	3	\r
	4	References:\r
48557c65	5	1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
	6	2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
	7	3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
f3b33289	8	4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
f3b33289	9	\r
5630cdfe	10	Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
cd5ebaa0	11	This program and the accompanying materials\r
f3b33289	12	are licensed and made available under the terms and conditions of the BSD License\r
	13	which accompanies this distribution. The full text of the license may be found at\r
	14	http://opensource.org/licenses/bsd-license.php\r
	15	\r
	16	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	17	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	18	\r
	19	**/ \r
	20	#ifndef _VIRTUAL_MEMORY_H_\r
	21	#define _VIRTUAL_MEMORY_H_\r
	22	\r
	23	\r
	24	#define SYS_CODE64_SEL 0x38\r
	25	\r
	26	#pragma pack(1)\r
	27	\r
	28	typedef union {\r
	29	struct {\r
	30	UINT32 LimitLow : 16;\r
	31	UINT32 BaseLow : 16;\r
	32	UINT32 BaseMid : 8;\r
	33	UINT32 Type : 4;\r
	34	UINT32 System : 1;\r
	35	UINT32 Dpl : 2;\r
	36	UINT32 Present : 1;\r
	37	UINT32 LimitHigh : 4;\r
	38	UINT32 Software : 1;\r
	39	UINT32 Reserved : 1;\r
	40	UINT32 DefaultSize : 1;\r
	41	UINT32 Granularity : 1;\r
	42	UINT32 BaseHigh : 8;\r
	43	} Bits;\r
	44	UINT64 Uint64;\r
	45	} IA32_GDT;\r
	46	\r
	47	typedef struct {\r
	48	IA32_IDT_GATE_DESCRIPTOR Ia32IdtEntry;\r
	49	UINT32 Offset32To63;\r
	50	UINT32 Reserved;\r
	51	} X64_IDT_GATE_DESCRIPTOR;\r
	52	\r
	53	//\r
	54	// Page-Map Level-4 Offset (PML4) and\r
	55	// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
	56	//\r
	57	\r
	58	typedef union {\r
	59	struct {\r
	60	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	61	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	62	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	63	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	64	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	65	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	66	UINT64 Reserved:1; // Reserved\r
	67	UINT64 MustBeZero:2; // Must Be Zero\r
	68	UINT64 Available:3; // Available for use by system software\r
	69	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
	70	UINT64 AvabilableHigh:11; // Available for use by system software\r
	71	UINT64 Nx:1; // No Execute bit\r
	72	} Bits;\r
	73	UINT64 Uint64;\r
	74	} PAGE_MAP_AND_DIRECTORY_POINTER;\r
	75	\r
5630cdfe SZ	76	//\r
	77	// Page Table Entry 4KB\r
	78	//\r
	79	typedef union {\r
	80	struct {\r
	81	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	82	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	83	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	84	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	85	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	86	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	87	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
	88	UINT64 PAT:1; //\r
	89	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
	90	UINT64 Available:3; // Available for use by system software\r
	91	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
	92	UINT64 AvabilableHigh:11; // Available for use by system software\r
	93	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
	94	} Bits;\r
	95	UINT64 Uint64;\r
	96	} PAGE_TABLE_4K_ENTRY;\r
	97	\r
f3b33289	98	//\r
	99	// Page Table Entry 2MB\r
	100	//\r
	101	typedef union {\r
	102	struct {\r
	103	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	104	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	105	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	106	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	107	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	108	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	109	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
	110	UINT64 MustBe1:1; // Must be 1 \r
	111	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
	112	UINT64 Available:3; // Available for use by system software\r
	113	UINT64 PAT:1; //\r
	114	UINT64 MustBeZero:8; // Must be zero;\r
	115	UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
	116	UINT64 AvabilableHigh:11; // Available for use by system software\r
	117	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
	118	} Bits;\r
	119	UINT64 Uint64;\r
	120	} PAGE_TABLE_ENTRY;\r
	121	\r
c56b6566 JY	122	//\r
	123	// Page Table Entry 1GB\r
	124	//\r
	125	typedef union {\r
	126	struct {\r
	127	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	128	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	129	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	130	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	131	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	132	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	133	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
	134	UINT64 MustBe1:1; // Must be 1 \r
	135	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
	136	UINT64 Available:3; // Available for use by system software\r
	137	UINT64 PAT:1; //\r
	138	UINT64 MustBeZero:17; // Must be zero;\r
	139	UINT64 PageTableBaseAddress:22; // Page Table Base Address\r
	140	UINT64 AvabilableHigh:11; // Available for use by system software\r
	141	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
	142	} Bits;\r
	143	UINT64 Uint64;\r
	144	} PAGE_TABLE_1G_ENTRY;\r
	145	\r
f3b33289	146	#pragma pack()\r
f3b33289	147	\r
5630cdfe SZ	148	#define IA32_PG_P BIT0\r
	149	#define IA32_PG_RW BIT1\r
	150	\r
	151	/**\r
	152	Enable Execute Disable Bit.\r
	153	\r
	154	**/\r
	155	VOID\r
	156	EnableExecuteDisableBit (\r
	157	VOID\r
	158	);\r
	159	\r
	160	/**\r
	161	Split 2M page to 4K.\r
	162	\r
	163	@param[in] PhysicalAddress Start physical address the 2M page covered.\r
	164	@param[in, out] PageEntry2M Pointer to 2M page entry.\r
	165	@param[in] StackBase Stack base address.\r
	166	@param[in] StackSize Stack size.\r
	167	\r
	168	**/\r
	169	VOID\r
	170	Split2MPageTo4K (\r
	171	IN EFI_PHYSICAL_ADDRESS PhysicalAddress,\r
	172	IN OUT UINT64 *PageEntry2M,\r
	173	IN EFI_PHYSICAL_ADDRESS StackBase,\r
	174	IN UINTN StackSize\r
	175	);\r
f3b33289	176	\r
f3b33289	177	/**\r
	178	Allocates and fills in the Page Directory and Page Table Entries to\r
	179	establish a 1:1 Virtual to Physical mapping.\r
	180	\r
5630cdfe SZ	181	@param[in] StackBase Stack base address.\r
5630cdfe SZ	182	@param[in] StackSize Stack size.\r
f3b33289	183	\r
48557c65	184	@return The address of 4 level page map.\r
f3b33289	185	\r
	186	**/\r
	187	UINTN\r
	188	CreateIdentityMappingPageTables (\r
5630cdfe SZ	189	IN EFI_PHYSICAL_ADDRESS StackBase,\r
5630cdfe SZ	190	IN UINTN StackSize\r
f3b33289	191	);\r
	192	\r
	193	\r
f3b33289	194	/**\r
	195	\r
	196	Fix up the vector number in the vector code.\r
	197	\r
	198	@param VectorBase Base address of the vector handler.\r
f3b33289	199	@param VectorNum Index of vector.\r
	200	\r
	201	**/\r
	202	VOID\r
	203	EFIAPI\r
	204	AsmVectorFixup (\r
	205	VOID *VectorBase,\r
	206	UINT8 VectorNum\r
	207	);\r
	208	\r
	209	\r
f3b33289	210	/**\r
	211	\r
	212	Get the information of vector template.\r
	213	\r
	214	@param TemplateBase Base address of the template code.\r
	215	\r
	216	@return Size of the Template code.\r
	217	\r
	218	**/\r
	219	UINTN\r
	220	EFIAPI\r
	221	AsmGetVectorTemplatInfo (\r
	222	OUT VOID **TemplateBase\r
	223	);\r
	224	\r
	225	\r
	226	#endif \r